Searched refs:Src0 (Results 1 - 5 of 5) sorted by relevance
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600ExpandSpecialInstrs.cpp | 97 unsigned Src0 = MI.getOperand(1).getReg(); local 106 Src0 = TRI.getSubReg(Src0, SubRegIndex); 112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); 113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); 152 .addReg(Src0)
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ExpandSpecialInstrs.cpp | 97 unsigned Src0 = MI.getOperand(1).getReg(); local 106 Src0 = TRI.getSubReg(Src0, SubRegIndex); 112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); 113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); 152 .addReg(Src0)
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/external/llvm/lib/Target/R600/ |
H A D | R600ExpandSpecialInstrs.cpp | 195 unsigned Src0 = BMI->getOperand( local 201 (void) Src0; 203 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && 205 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); 247 unsigned Src0 = MI.getOperand( local 260 Src0 = TRI.getSubReg(Src0, SubRegIndex); 266 Src1 = TRI.getSubReg(Src0, SubRegIndex1); 267 Src0 = TRI.getSubReg(Src0, SubRegIndex [all...] |
H A D | R600InstrInfo.cpp | 1177 MachineOperand &Src0 = MI->getOperand( 1182 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 1106 SDValue Src0 = N->getOperand(1); local 1124 EVT Src0VT = Src0.getValueType(); 1133 SDValue LoOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src0, Zero); 1136 SDValue HiOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src0, LoElts);
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