Searched refs:UREG (Results 1 - 14 of 14) sorted by relevance

/external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/
H A Di915_fpc_emit.c68 return UREG(REG_TYPE_U, (bit - 1));
82 uint reg = UREG(type, nr);
122 dest = UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest));
194 const uint k = UREG(GET_UREG_TYPE(coord), GET_UREG_NR(coord));
223 tempReg = UREG(REG_TYPE_R, temp); /* make i915 register */
245 assert(dest == UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest)));
290 return swizzle(UREG(REG_TYPE_R, 0), ZERO, ZERO, ZERO, ZERO);
292 return swizzle(UREG(REG_TYPE_R, 0), ONE, ONE, ONE, ONE);
304 return swizzle(UREG(REG_TYPE_CONST, reg), idx, ZERO, ZERO, ONE);
342 return swizzle(UREG(REG_TYPE_CONS
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H A Di915_state_emit.c448 int cst0_reg = swizzle(UREG(REG_TYPE_CONST, cst_idx), X, X, X, X);
449 int cst1_reg = swizzle(UREG(REG_TYPE_CONST, cst_idx), Y, Y, Y, Y);
450 int cst2_reg = swizzle(UREG(REG_TYPE_CONST, cst_idx), Z, Z, Z, Z);
451 int t1_reg = UREG(REG_TYPE_R, 1);
452 int t1x_reg = swizzle(UREG(REG_TYPE_R, 1), X, X, X, X);
453 int t1y_reg = swizzle(UREG(REG_TYPE_R, 1), Y, Y, Y, Y);
454 int t1z_reg = swizzle(UREG(REG_TYPE_R, 1), Z, Z, Z, Z);
H A Di915_fpc_translate.c116 /* Another neat thing about the UREG representation */
193 src = UREG(REG_TYPE_R, index);
256 src = UREG(REG_TYPE_CONST, index);
304 return UREG(REG_TYPE_OD, 0);
306 return UREG(REG_TYPE_OC, 0);
313 return UREG(REG_TYPE_R, dest->Register.Index);
1346 const uint depth = UREG(REG_TYPE_OD, 0);
H A Di915_fpc.h118 #define UREG( type, nr ) (((type)<< UREG_TYPE_SHIFT) | \ macro
137 /* One neat thing about the UREG representation:
170 /* Macros for translating UREG's into the various register fields used
/external/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_emit.c68 return UREG(REG_TYPE_U, (bit - 1));
82 uint reg = UREG(type, nr);
122 dest = UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest));
194 const uint k = UREG(GET_UREG_TYPE(coord), GET_UREG_NR(coord));
223 tempReg = UREG(REG_TYPE_R, temp); /* make i915 register */
245 assert(dest == UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest)));
290 return swizzle(UREG(REG_TYPE_R, 0), ZERO, ZERO, ZERO, ZERO);
292 return swizzle(UREG(REG_TYPE_R, 0), ONE, ONE, ONE, ONE);
304 return swizzle(UREG(REG_TYPE_CONST, reg), idx, ZERO, ZERO, ONE);
342 return swizzle(UREG(REG_TYPE_CONS
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H A Di915_state_emit.c448 int cst0_reg = swizzle(UREG(REG_TYPE_CONST, cst_idx), X, X, X, X);
449 int cst1_reg = swizzle(UREG(REG_TYPE_CONST, cst_idx), Y, Y, Y, Y);
450 int cst2_reg = swizzle(UREG(REG_TYPE_CONST, cst_idx), Z, Z, Z, Z);
451 int t1_reg = UREG(REG_TYPE_R, 1);
452 int t1x_reg = swizzle(UREG(REG_TYPE_R, 1), X, X, X, X);
453 int t1y_reg = swizzle(UREG(REG_TYPE_R, 1), Y, Y, Y, Y);
454 int t1z_reg = swizzle(UREG(REG_TYPE_R, 1), Z, Z, Z, Z);
H A Di915_fpc_translate.c116 /* Another neat thing about the UREG representation */
193 src = UREG(REG_TYPE_R, index);
256 src = UREG(REG_TYPE_CONST, index);
304 return UREG(REG_TYPE_OD, 0);
306 return UREG(REG_TYPE_OC, 0);
313 return UREG(REG_TYPE_R, dest->Register.Index);
1346 const uint depth = UREG(REG_TYPE_OD, 0);
H A Di915_fpc.h118 #define UREG( type, nr ) (((type)<< UREG_TYPE_SHIFT) | \ macro
137 /* One neat thing about the UREG representation:
170 /* Macros for translating UREG's into the various register fields used
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/
H A Di915_program.c58 /* Macros for translating UREG's into the various register fields used
85 return UREG(REG_TYPE_R, (bit - 1));
99 return UREG(REG_TYPE_U, (bit - 1));
113 GLuint reg = UREG(type, nr);
150 dest = UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest));
214 return UREG(REG_TYPE_R, bit - 1);
225 if (coord != UREG(GET_UREG_TYPE(coord), GET_UREG_NR(coord))) {
248 assert(dest == UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest)));
306 return swizzle(UREG(REG_TYPE_R, 0), ZERO, ZERO, ZERO, ZERO);
308 return swizzle(UREG(REG_TYPE_
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H A Di915_program.h66 #define UREG( type, nr ) (((type)<< UREG_TYPE_SHIFT) | \ macro
85 /* One neat thing about the UREG representation:
97 /* Another neat thing about the UREG representation:
H A Di915_fragprog.c96 src = UREG(REG_TYPE_R, source->Index);
149 src = UREG(REG_TYPE_OC, 0);
152 src = UREG(REG_TYPE_OD, 0);
212 return UREG(REG_TYPE_OC, 0);
215 return UREG(REG_TYPE_OD, 0);
222 return UREG(REG_TYPE_R, inst->DstReg.Index);
389 UREG(REG_TYPE_OC, 0),
1138 GLuint depth = UREG(REG_TYPE_OD, 0);
/external/mesa3d/src/mesa/drivers/dri/i915/
H A Di915_program.c58 /* Macros for translating UREG's into the various register fields used
85 return UREG(REG_TYPE_R, (bit - 1));
99 return UREG(REG_TYPE_U, (bit - 1));
113 GLuint reg = UREG(type, nr);
150 dest = UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest));
214 return UREG(REG_TYPE_R, bit - 1);
225 if (coord != UREG(GET_UREG_TYPE(coord), GET_UREG_NR(coord))) {
248 assert(dest == UREG(GET_UREG_TYPE(dest), GET_UREG_NR(dest)));
306 return swizzle(UREG(REG_TYPE_R, 0), ZERO, ZERO, ZERO, ZERO);
308 return swizzle(UREG(REG_TYPE_
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H A Di915_program.h66 #define UREG( type, nr ) (((type)<< UREG_TYPE_SHIFT) | \ macro
85 /* One neat thing about the UREG representation:
97 /* Another neat thing about the UREG representation:
H A Di915_fragprog.c96 src = UREG(REG_TYPE_R, source->Index);
149 src = UREG(REG_TYPE_OC, 0);
152 src = UREG(REG_TYPE_OD, 0);
212 return UREG(REG_TYPE_OC, 0);
215 return UREG(REG_TYPE_OD, 0);
222 return UREG(REG_TYPE_R, inst->DstReg.Index);
389 UREG(REG_TYPE_OC, 0),
1138 GLuint depth = UREG(REG_TYPE_OD, 0);

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