/external/proguard/src/proguard/optimize/evaluation/ |
H A D | EvaluationShrinker.java | 1054 byte newOpcode = 0; 1072 newOpcode = InstructionConstants.OP_DUP; 1097 newOpcode = (byte)(InstructionConstants.OP_DUP + skipCount); 1102 newOpcode = InstructionConstants.OP_SWAP; 1129 newOpcode = (byte)(InstructionConstants.OP_DUP + skipCount); 1134 newOpcode = InstructionConstants.OP_SWAP; 1158 newOpcode = InstructionConstants.OP_DUP2; 1182 newOpcode = (byte)(InstructionConstants.OP_DUP2 + skipCount); 1214 newOpcode = (byte)(InstructionConstants.OP_DUP2 + skipCount); 1238 newOpcode [all...] |
/external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
H A D | OutputFinisher.java | 460 Dop newOpcode = findOpcodeForInsn(insn, originalOpcode); 462 if (newOpcode == null) { 473 } else if (originalOpcode == newOpcode) { 477 opcodes[i] = newOpcode;
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/external/dexmaker/src/dx/java/com/android/dx/ssa/ |
H A D | LiteralOpUpgrader.java | 183 * @param newOpcode A RegOp from {@link RegOps} 187 RegisterSpecList newSources, int newOpcode, Constant cst) { 190 Rop newRop = Rops.ropFor(newOpcode, insn.getResult(), newSources, cst); 186 replacePlainInsn(NormalSsaInsn insn, RegisterSpecList newSources, int newOpcode, Constant cst) argument
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H A D | EscapeAnalysis.java | 781 * @param newOpcode opcode of new instruction 785 RegisterSpecList newSources, RegisterSpec newResult, int newOpcode, 790 if (newOpcode == RegOps.MOVE_RESULT_PSEUDO) { 793 newRop = Rops.ropFor(newOpcode, newResult, newSources, cst); 819 * @param newOpcode opcode of new instruction 823 RegisterSpecList newSources, RegisterSpec newResult, int newOpcode, 827 Rop newRop = Rops.ropFor(newOpcode, newResult, newSources, cst); 784 insertPlainInsnBefore(SsaInsn insn, RegisterSpecList newSources, RegisterSpec newResult, int newOpcode, Constant cst) argument 822 insertThrowingInsnBefore(SsaInsn insn, RegisterSpecList newSources, RegisterSpec newResult, int newOpcode, Constant cst) argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDILCFGStructurizer.cpp | 1728 int newOpcode = CFGTraits::getBreakZeroOpcode(oldOpcode); local 1729 CFGTraits::insertCondBranchBefore(branchInstrPos, newOpcode, passRep, DL); 1734 int newOpcode = CFGTraits::getBreakZeroOpcode(oldOpcode); local 1735 CFGTraits::insertCondBranchBefore(branchInstrPos, newOpcode, passRep, DL); 3006 static MachineInstr *insertInstrBefore(MachineBasicBlock *blk, int newOpcode, argument 3008 return insertInstrBefore(blk,newOpcode,passRep,DebugLoc()); 3011 static MachineInstr *insertInstrBefore(MachineBasicBlock *blk, int newOpcode, argument 3015 blk->getParent()->CreateMachineInstr(tii->get(newOpcode), DL); 3029 static void insertInstrEnd(MachineBasicBlock *blk, int newOpcode, argument 3031 insertInstrEnd(blk,newOpcode,passRe 3034 insertInstrEnd(MachineBasicBlock *blk, int newOpcode, AMDGPUCFGStructurizer *passRep, DebugLoc DL) argument 3046 insertInstrBefore(MachineBasicBlock::iterator instrPos, int newOpcode, AMDGPUCFGStructurizer *passRep) argument 3063 insertCondBranchBefore(MachineBasicBlock::iterator instrPos, int newOpcode, AMDGPUCFGStructurizer *passRep, DebugLoc DL) argument 3082 insertCondBranchBefore(MachineBasicBlock *blk, MachineBasicBlock::iterator insertPos, int newOpcode, AMDGPUCFGStructurizer *passRep, RegiT regNum, DebugLoc DL) argument 3100 insertCondBranchEnd(MachineBasicBlock *blk, int newOpcode, AMDGPUCFGStructurizer *passRep, RegiT regNum) argument [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILCFGStructurizer.cpp | 1728 int newOpcode = CFGTraits::getBreakZeroOpcode(oldOpcode); local 1729 CFGTraits::insertCondBranchBefore(branchInstrPos, newOpcode, passRep, DL); 1734 int newOpcode = CFGTraits::getBreakZeroOpcode(oldOpcode); local 1735 CFGTraits::insertCondBranchBefore(branchInstrPos, newOpcode, passRep, DL); 3006 static MachineInstr *insertInstrBefore(MachineBasicBlock *blk, int newOpcode, argument 3008 return insertInstrBefore(blk,newOpcode,passRep,DebugLoc()); 3011 static MachineInstr *insertInstrBefore(MachineBasicBlock *blk, int newOpcode, argument 3015 blk->getParent()->CreateMachineInstr(tii->get(newOpcode), DL); 3029 static void insertInstrEnd(MachineBasicBlock *blk, int newOpcode, argument 3031 insertInstrEnd(blk,newOpcode,passRe 3034 insertInstrEnd(MachineBasicBlock *blk, int newOpcode, AMDGPUCFGStructurizer *passRep, DebugLoc DL) argument 3046 insertInstrBefore(MachineBasicBlock::iterator instrPos, int newOpcode, AMDGPUCFGStructurizer *passRep) argument 3063 insertCondBranchBefore(MachineBasicBlock::iterator instrPos, int newOpcode, AMDGPUCFGStructurizer *passRep, DebugLoc DL) argument 3082 insertCondBranchBefore(MachineBasicBlock *blk, MachineBasicBlock::iterator insertPos, int newOpcode, AMDGPUCFGStructurizer *passRep, RegiT regNum, DebugLoc DL) argument 3100 insertCondBranchEnd(MachineBasicBlock *blk, int newOpcode, AMDGPUCFGStructurizer *passRep, RegiT regNum) argument [all...] |