Searched refs:registers (Results 1 - 25 of 150) sorted by relevance

123456

/external/dexmaker/src/dx/java/com/android/dx/dex/code/
H A DSimpleInsn.java33 * @param registers {@code non-null;} register list, including a
34 * result register if appropriate (that is, registers may be either
38 RegisterSpecList registers) {
39 super(opcode, position, registers);
50 public DalvInsn withRegisters(RegisterSpecList registers) { argument
51 return new SimpleInsn(getOpcode(), getPosition(), registers);
37 SimpleInsn(Dop opcode, SourcePosition position, RegisterSpecList registers) argument
H A DHighRegisterPrefix.java27 * {@code move*} instructions to move a set of registers into
28 * registers starting at {@code 0} sequentially. This is used
41 * @param registers {@code non-null;} source registers
44 RegisterSpecList registers) {
45 super(position, registers);
47 if (registers.size() == 0) {
48 throw new IllegalArgumentException("registers.size() == 0");
87 RegisterSpecList registers = getRegisters();
88 int sz = registers
43 HighRegisterPrefix(SourcePosition position, RegisterSpecList registers) argument
101 withRegisters(RegisterSpecList registers) argument
[all...]
H A DVariableSizeInsn.java31 * @param registers {@code non-null;} source registers
34 RegisterSpecList registers) {
35 super(Dops.SPECIAL_FORMAT, position, registers);
33 VariableSizeInsn(SourcePosition position, RegisterSpecList registers) argument
H A DCstInsn.java49 * @param registers {@code non-null;} register list, including a
50 * result register if appropriate (that is, registers may be either
55 RegisterSpecList registers, Constant constant) {
56 super(opcode, position, registers);
86 public DalvInsn withRegisters(RegisterSpecList registers) { argument
88 new CstInsn(getOpcode(), getPosition(), registers, constant);
54 CstInsn(Dop opcode, SourcePosition position, RegisterSpecList registers, Constant constant) argument
H A DDalvInsn.java45 private final RegisterSpecList registers; field in class:DalvInsn
83 * absolutely no registers (e.g., a {@code nop} or a
90 * @param registers {@code non-null;} register list, including a
91 * result register if appropriate (that is, registers may be either
95 RegisterSpecList registers) {
104 if (registers == null) {
105 throw new NullPointerException("registers == null");
111 this.registers = registers;
127 if (registers
94 DalvInsn(Dop opcode, SourcePosition position, RegisterSpecList registers) argument
426 withRegisters(RegisterSpecList registers) argument
[all...]
H A DTargetInsn.java36 * @param registers {@code non-null;} register list, including a
37 * result register if appropriate (that is, registers may be either
42 RegisterSpecList registers, CodeAddress target) {
43 super(opcode, position, registers);
60 public DalvInsn withRegisters(RegisterSpecList registers) { argument
61 return new TargetInsn(getOpcode(), getPosition(), registers, target);
41 TargetInsn(Dop opcode, SourcePosition position, RegisterSpecList registers, CodeAddress target) argument
H A DFixedSizeInsn.java34 * absolutely no registers (e.g., a {@code nop} or a
41 * @param registers {@code non-null;} register list, including a
42 * result register if appropriate (that is, registers may be either
46 RegisterSpecList registers) {
47 super(opcode, position, registers);
45 FixedSizeInsn(Dop opcode, SourcePosition position, RegisterSpecList registers) argument
H A DCodeAddress.java42 public final DalvInsn withRegisters(RegisterSpecList registers) { argument
H A DLocalEnd.java65 public DalvInsn withRegisters(RegisterSpecList registers) { argument
H A DLocalStart.java73 public DalvInsn withRegisters(RegisterSpecList registers) { argument
H A DOddSpacer.java57 public DalvInsn withRegisters(RegisterSpecList registers) { argument
/external/chromium_org/third_party/mesa/src/src/mapi/glapi/gen/
H A Dgl_x86-64_asm.py32 def should_use_push(registers):
33 for [reg, offset] in registers:
37 N = len(registers)
41 def local_size(registers):
48 N = (len(registers) | 1)
52 def save_all_regs(registers):
54 if not should_use_push(registers):
55 adjust_stack = local_size(registers)
58 for [reg, stack_offset] in registers:
63 def restore_all_regs(registers)
[all...]
/external/mesa3d/src/mapi/glapi/gen/
H A Dgl_x86-64_asm.py32 def should_use_push(registers):
33 for [reg, offset] in registers:
37 N = len(registers)
41 def local_size(registers):
48 N = (len(registers) | 1)
52 def save_all_regs(registers):
54 if not should_use_push(registers):
55 adjust_stack = local_size(registers)
58 for [reg, stack_offset] in registers:
63 def restore_all_regs(registers)
[all...]
/external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/
H A DPreInstructionRegisterInfoMethodItem.java64 BitSet registers = new BitSet(registerCount);
67 registers.set(0, registerCount);
70 registers.set(0, registerCount);
73 addArgsRegs(registers);
76 addMergeRegs(registers, registerCount);
79 addParamRegs(registers, registerCount);
86 printedSomething = writeFullMergeRegs(writer, registers, registerCount);
89 printedSomething |= writeRegisterInfo(writer, registers, printedSomething);
94 private void addArgsRegs(BitSet registers) { argument
98 registers
134 addMergeRegs(BitSet registers, int registerCount) argument
158 addParamRegs(BitSet registers, int registerCount) argument
168 writeFullMergeRegs(IndentingWriter writer, BitSet registers, int registerCount) argument
236 writeRegisterInfo(IndentingWriter writer, BitSet registers, boolean addNewline) argument
[all...]
H A DPostInstructionRegisterInfoMethodItem.java62 BitSet registers = new BitSet(registerCount);
65 registers.set(0, registerCount);
68 registers.set(0, registerCount);
70 addDestRegs(registers, registerCount);
74 return writeRegisterInfo(writer, registers);
86 private boolean writeRegisterInfo(IndentingWriter writer, BitSet registers) throws IOException { argument
89 int registerNum = registers.nextSetBit(0);
95 for (; registerNum >= 0; registerNum = registers.nextSetBit(registerNum + 1)) {
/external/valgrind/main/coregrind/m_gdbserver/
H A Dregcache.c33 unsigned char *registers; member in struct:inferior_regcache_data
55 /* FIXME - fetch registers for INF */
99 in case there are registers the target never fetches. This way they'll
101 regcache->registers = calloc (1, register_bytes);
102 if (regcache->registers == NULL)
119 free (regcache->registers);
125 This is needed if the shadow registers are added.
162 unsigned char *registers = get_regcache (current_inferior, 1)->registers; local
164 convert_int_to_ascii (registers, bu
170 unsigned char *registers = get_regcache (current_inferior, 1)->registers; local
205 unsigned char *registers local
215 unsigned char *registers = cache->registers; local
[all...]
/external/chromium_org/chrome/browser/nacl_host/test/
H A Ddebug_stub_browser_tests.py33 registers = connection.RspRequest('g')
38 return ReverseBytes(registers[8 * 8 : 8 * 8 + 8])
41 return ReverseBytes(registers[16 * 16 : 16 * 16 + 8])
44 return ReverseBytes(registers[15 * 8 : 15 * 8 + 8])
60 registers = connection.RspRequest('g')
70 # Check that registers haven't changed
72 assert result == registers, (result, registers)
/external/chromium_org/v8/src/
H A Dinterpreter-irregexp.cc200 int* registers,
240 *backtrack_sp++ = registers[insn >> BYTECODE_SHIFT];
244 registers[insn >> BYTECODE_SHIFT] = Load32Aligned(pc + 4);
248 registers[insn >> BYTECODE_SHIFT] += Load32Aligned(pc + 4);
252 registers[insn >> BYTECODE_SHIFT] = current + Load32Aligned(pc + 4);
256 current = registers[insn >> BYTECODE_SHIFT];
260 registers[insn >> BYTECODE_SHIFT] =
265 backtrack_sp = backtrack_stack_base + registers[insn >> BYTECODE_SHIFT];
284 registers[insn >> BYTECODE_SHIFT] = *backtrack_sp;
509 if (registers[ins
197 RawMatch(Isolate* isolate, const byte* code_base, Vector<const Char> subject, int* registers, int current, uint32_t current_char) argument
613 Match( Isolate* isolate, Handle<ByteArray> code_array, Handle<String> subject, int* registers, int start_position) argument
[all...]
/external/v8/src/
H A Dinterpreter-irregexp.cc193 int* registers,
233 *backtrack_sp++ = registers[insn >> BYTECODE_SHIFT];
237 registers[insn >> BYTECODE_SHIFT] = Load32Aligned(pc + 4);
241 registers[insn >> BYTECODE_SHIFT] += Load32Aligned(pc + 4);
245 registers[insn >> BYTECODE_SHIFT] = current + Load32Aligned(pc + 4);
249 current = registers[insn >> BYTECODE_SHIFT];
253 registers[insn >> BYTECODE_SHIFT] =
258 backtrack_sp = backtrack_stack_base + registers[insn >> BYTECODE_SHIFT];
277 registers[insn >> BYTECODE_SHIFT] = *backtrack_sp;
471 if (registers[ins
190 RawMatch(Isolate* isolate, const byte* code_base, Vector<const Char> subject, int* registers, int current, uint32_t current_char) argument
628 Match( Isolate* isolate, Handle<ByteArray> code_array, Handle<String> subject, int* registers, int start_position) argument
[all...]
/external/llvm/lib/Target/X86/
H A DX86CompilationCallback_Win64.asm23 ; Save all int arg registers
33 ; Save all XMM arg registers. Also allocate reg spill area.
47 ; Restore all XMM arg registers.
56 ; Restore all int arg registers
/external/jpeg/
H A Djmemdosa.asm17 ; we save and restore all 8086 registers, even though most compilers only
46 push si ; save all registers for safety
61 open_err: pop ds ; restore registers and exit
81 push si ; save all registers for safety
93 close_err: pop ds ; restore registers and exit
113 push si ; save all registers for safety
127 seek_err: pop ds ; restore registers and exit
147 push si ; save all registers for safety
165 read_err: pop ds ; restore registers and exit
185 push si ; save all registers fo
[all...]
/external/qemu/distrib/jpeg-6b/
H A Djmemdosa.asm17 ; we save and restore all 8086 registers, even though most compilers only
46 push si ; save all registers for safety
61 open_err: pop ds ; restore registers and exit
81 push si ; save all registers for safety
93 close_err: pop ds ; restore registers and exit
113 push si ; save all registers for safety
127 seek_err: pop ds ; restore registers and exit
147 push si ; save all registers for safety
165 read_err: pop ds ; restore registers and exit
185 push si ; save all registers fo
[all...]
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp73 int registers[4];
74 __cpuid(registers, value);
75 *rEAX = registers[0];
76 *rEBX = registers[1];
77 *rECX = registers[2];
78 *rEDX = registers[3];
137 int registers[4];
138 __cpuidex(registers, value, subleaf);
139 *rEAX = registers[0];
140 *rEBX = registers[
[all...]
/external/llvm/test/MC/Mips/
H A Dnabi-regs.s2 # set for the A and T registers because the NABI allows
3 # for 4 more register parameters (A registers) offsetting
4 # the T registers.
/external/qemu/distrib/sdl-1.2.15/src/hermes/
H A Dmmx_main.asm37 ; Save the registers used by the blitters, necessary for optimized code
62 ; Restore the registers used by the blitters, necessary for optimized code

Completed in 730 milliseconds

123456