1f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#ifndef __NV40_SHADER_H__ 2f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define __NV40_SHADER_H__ 3f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 4f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* Vertex programs instruction set 5f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 6f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * The NV40 instruction set is very similar to NV30. Most fields are in 7f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * a slightly different position in the instruction however. 8f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 9f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Merged instructions 10f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * In some cases it is possible to put two instructions into one opcode 11f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * slot. The rules for when this is OK is not entirely clear to me yet. 12f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 13f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * There are separate writemasks and dest temp register fields for each 14f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * grouping of instructions. There is however only one field with the 15f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * ID of a result register. Writing to temp/result regs is selected by 16f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * setting VEC_RESULT/SCA_RESULT. 17f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 18f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Temporary registers 19f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * The source/dest temp register fields have been extended by 1 bit, to 20f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * give a total of 32 temporary registers. 21f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 22f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Relative Addressing 23f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * NV40 can use an address register to index into vertex attribute regs. 24f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * This is done by putting the offset value into INPUT_SRC and setting 25f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * the INDEX_INPUT flag. 26f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 27f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Conditional execution (see NV_vertex_program{2,3} for details) 28f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * There is a second condition code register on NV40, it's use is enabled 29f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * by setting the COND_REG_SELECT_1 flag. 30f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 31f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Texture lookup 32f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * TODO 33f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 34f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 35f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* ---- OPCODE BITS 127:96 / data DWORD 0 --- */ 36f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_VEC_RESULT (1 << 30) 37f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* uncertain.. */ 38f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_UPDATE_ENABLE ((1 << 14)|1<<29) 39f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* use address reg as index into attribs */ 40f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_INDEX_INPUT (1 << 27) 41f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SATURATE (1 << 26) 42f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_REG_SELECT_1 (1 << 25) 43f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_ADDR_REG_SELECT_1 (1 << 24) 44f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC2_ABS (1 << 23) 45f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC1_ABS (1 << 22) 46f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC0_ABS (1 << 21) 47f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_VEC_DEST_TEMP_SHIFT 15 48f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_VEC_DEST_TEMP_MASK (0x3F << 15) 49f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_TEST_ENABLE (1 << 13) 50f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_SHIFT 10 51f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_MASK (0x7 << 10) 52f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_SWZ_X_SHIFT 8 53f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_SWZ_X_MASK (3 << 8) 54f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_SWZ_Y_SHIFT 6 55f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_SWZ_Y_MASK (3 << 6) 56f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_SWZ_Z_SHIFT 4 57f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_SWZ_Z_MASK (3 << 4) 58f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_SWZ_W_SHIFT 2 59f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_SWZ_W_MASK (3 << 2) 60f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_SWZ_ALL_SHIFT 2 61f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_COND_SWZ_ALL_MASK (0xFF << 2) 62f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_ADDR_SWZ_SHIFT 0 63f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_ADDR_SWZ_MASK (0x03 << 0) 64f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST0_KNOWN ( \ 65f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_INDEX_INPUT | \ 66f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_COND_REG_SELECT_1 | \ 67f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_ADDR_REG_SELECT_1 | \ 68f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_SRC2_ABS | \ 69f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_SRC1_ABS | \ 70f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_SRC0_ABS | \ 71f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_VEC_DEST_TEMP_MASK | \ 72f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_COND_TEST_ENABLE | \ 73f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_COND_MASK | \ 74f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_COND_SWZ_ALL_MASK | \ 75f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_ADDR_SWZ_MASK) 76f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 77f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* ---- OPCODE BITS 95:64 / data DWORD 1 --- */ 78f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_VEC_OPCODE_SHIFT 22 79f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_VEC_OPCODE_MASK (0x1F << 22) 80f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SCA_OPCODE_SHIFT 27 81f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SCA_OPCODE_MASK (0x1F << 27) 82f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_CONST_SRC_SHIFT 12 83f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_CONST_SRC_MASK (0xFF << 12) 84f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_INPUT_SRC_SHIFT 8 85f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_INPUT_SRC_MASK (0x0F << 8) 86f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC0H_SHIFT 0 87f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC0H_MASK (0xFF << 0) 88f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST1_KNOWN ( \ 89f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_VEC_OPCODE_MASK | \ 90f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_SCA_OPCODE_MASK | \ 91f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_CONST_SRC_MASK | \ 92f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_INPUT_SRC_MASK | \ 93f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_SRC0H_MASK \ 94f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org ) 95f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 96f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* ---- OPCODE BITS 63:32 / data DWORD 2 --- */ 97f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC0L_SHIFT 23 98f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC0L_MASK (0x1FF << 23) 99f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC1_SHIFT 6 100f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC1_MASK (0x1FFFF << 6) 101f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC2H_SHIFT 0 102f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC2H_MASK (0x3F << 0) 103f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_IADDRH_SHIFT 0 104f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_IADDRH_MASK (0x3F << 0) 105f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 106f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* ---- OPCODE BITS 31:0 / data DWORD 3 --- */ 107f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_IADDRL_SHIFT 29 108f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_IADDRL_MASK (7 << 29) 109f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC2L_SHIFT 21 110f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SRC2L_MASK (0x7FF << 21) 111f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SCA_WRITEMASK_SHIFT 17 112f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SCA_WRITEMASK_MASK (0xF << 17) 113f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_SCA_WRITEMASK_X (1 << 20) 114f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_SCA_WRITEMASK_Y (1 << 19) 115f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_SCA_WRITEMASK_Z (1 << 18) 116f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_SCA_WRITEMASK_W (1 << 17) 117f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_VEC_WRITEMASK_SHIFT 13 118f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_VEC_WRITEMASK_MASK (0xF << 13) 119f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_VEC_WRITEMASK_X (1 << 16) 120f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_VEC_WRITEMASK_Y (1 << 15) 121f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_VEC_WRITEMASK_Z (1 << 14) 122f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_VEC_WRITEMASK_W (1 << 13) 123f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SCA_RESULT (1 << 12) 124f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SCA_DEST_TEMP_SHIFT 7 125f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_SCA_DEST_TEMP_MASK (0x1F << 7) 126f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_DEST_SHIFT 2 127f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_DEST_MASK (31 << 2) 128f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_DEST_POS 0 129f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_DEST_COL0 1 130f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_DEST_COL1 2 131f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_DEST_BFC0 3 132f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_DEST_BFC1 4 133f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_DEST_FOGC 5 134f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_DEST_PSZ 6 135f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_DEST_TC0 7 136f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_DEST_TC(n) (7+n) 137f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_INST_DEST_TEMP 0x1F 138f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST_INDEX_CONST (1 << 1) 139f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_INST3_KNOWN ( \ 140f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_SRC2L_MASK |\ 141f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_SCA_WRITEMASK_MASK |\ 142f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_VEC_WRITEMASK_MASK |\ 143f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_SCA_DEST_TEMP_MASK |\ 144f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_DEST_MASK |\ 145f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org NV40_VP_INST_INDEX_CONST) 146f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 147f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* Useful to split the source selection regs into their pieces */ 148f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC0_HIGH_SHIFT 9 149f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC0_HIGH_MASK 0x0001FE00 150f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC0_LOW_MASK 0x000001FF 151f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC2_HIGH_SHIFT 11 152f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC2_HIGH_MASK 0x0001F800 153f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC2_LOW_MASK 0x000007FF 154f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 155f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */ 156f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_NEGATE (1 << 16) 157f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_SWZ_X_SHIFT 14 158f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_SWZ_X_MASK (3 << 14) 159f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_SWZ_Y_SHIFT 12 160f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_SWZ_Y_MASK (3 << 12) 161f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_SWZ_Z_SHIFT 10 162f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_SWZ_Z_MASK (3 << 10) 163f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_SWZ_W_SHIFT 8 164f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_SWZ_W_MASK (3 << 8) 165f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_SWZ_ALL_SHIFT 8 166f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_SWZ_ALL_MASK (0xFF << 8) 167f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_TEMP_SRC_SHIFT 2 168f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_TEMP_SRC_MASK (0x1F << 2) 169f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_REG_TYPE_SHIFT 0 170f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define NV40_VP_SRC_REG_TYPE_MASK (3 << 0) 171f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_SRC_REG_TYPE_UNK0 0 172f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_SRC_REG_TYPE_TEMP 1 173f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_SRC_REG_TYPE_INPUT 2 174f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define NV40_VP_SRC_REG_TYPE_CONST 3 175f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 176f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "nvfx_shader.h" 177f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 178f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#endif 179