1// Copyright (c) 1994-2006 Sun Microsystems Inc. 2// All Rights Reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: 7// 8// - Redistributions of source code must retain the above copyright notice, 9// this list of conditions and the following disclaimer. 10// 11// - Redistribution in binary form must reproduce the above copyright 12// notice, this list of conditions and the following disclaimer in the 13// documentation and/or other materials provided with the distribution. 14// 15// - Neither the name of Sun Microsystems or the names of contributors may 16// be used to endorse or promote products derived from this software without 17// specific prior written permission. 18// 19// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31// The original source code covered by the above license above has been 32// modified significantly by Google Inc. 33// Copyright 2012 the V8 project authors. All rights reserved. 34 35 36#ifndef V8_MIPS_ASSEMBLER_MIPS_H_ 37#define V8_MIPS_ASSEMBLER_MIPS_H_ 38 39#include <stdio.h> 40#include "assembler.h" 41#include "constants-mips.h" 42#include "serialize.h" 43 44namespace v8 { 45namespace internal { 46 47// CPU Registers. 48// 49// 1) We would prefer to use an enum, but enum values are assignment- 50// compatible with int, which has caused code-generation bugs. 51// 52// 2) We would prefer to use a class instead of a struct but we don't like 53// the register initialization to depend on the particular initialization 54// order (which appears to be different on OS X, Linux, and Windows for the 55// installed versions of C++ we tried). Using a struct permits C-style 56// "initialization". Also, the Register objects cannot be const as this 57// forces initialization stubs in MSVC, making us dependent on initialization 58// order. 59// 60// 3) By not using an enum, we are possibly preventing the compiler from 61// doing certain constant folds, which may significantly reduce the 62// code generated for some assembly instructions (because they boil down 63// to a few constants). If this is a problem, we could change the code 64// such that we use an enum in optimized mode, and the struct in debug 65// mode. This way we get the compile-time error checking in debug mode 66// and best performance in optimized code. 67 68 69// ----------------------------------------------------------------------------- 70// Implementation of Register and FPURegister. 71 72// Core register. 73struct Register { 74 static const int kNumRegisters = v8::internal::kNumRegisters; 75 static const int kMaxNumAllocatableRegisters = 14; // v0 through t7. 76 static const int kSizeInBytes = 4; 77 78 inline static int NumAllocatableRegisters(); 79 80 static int ToAllocationIndex(Register reg) { 81 return reg.code() - 2; // zero_reg and 'at' are skipped. 82 } 83 84 static Register FromAllocationIndex(int index) { 85 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 86 return from_code(index + 2); // zero_reg and 'at' are skipped. 87 } 88 89 static const char* AllocationIndexToString(int index) { 90 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 91 const char* const names[] = { 92 "v0", 93 "v1", 94 "a0", 95 "a1", 96 "a2", 97 "a3", 98 "t0", 99 "t1", 100 "t2", 101 "t3", 102 "t4", 103 "t5", 104 "t6", 105 "t7", 106 }; 107 return names[index]; 108 } 109 110 static Register from_code(int code) { 111 Register r = { code }; 112 return r; 113 } 114 115 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; } 116 bool is(Register reg) const { return code_ == reg.code_; } 117 int code() const { 118 ASSERT(is_valid()); 119 return code_; 120 } 121 int bit() const { 122 ASSERT(is_valid()); 123 return 1 << code_; 124 } 125 126 // Unfortunately we can't make this private in a struct. 127 int code_; 128}; 129 130#define REGISTER(N, C) \ 131 const int kRegister_ ## N ## _Code = C; \ 132 const Register N = { C } 133 134REGISTER(no_reg, -1); 135// Always zero. 136REGISTER(zero_reg, 0); 137// at: Reserved for synthetic instructions. 138REGISTER(at, 1); 139// v0, v1: Used when returning multiple values from subroutines. 140REGISTER(v0, 2); 141REGISTER(v1, 3); 142// a0 - a4: Used to pass non-FP parameters. 143REGISTER(a0, 4); 144REGISTER(a1, 5); 145REGISTER(a2, 6); 146REGISTER(a3, 7); 147// t0 - t9: Can be used without reservation, act as temporary registers and are 148// allowed to be destroyed by subroutines. 149REGISTER(t0, 8); 150REGISTER(t1, 9); 151REGISTER(t2, 10); 152REGISTER(t3, 11); 153REGISTER(t4, 12); 154REGISTER(t5, 13); 155REGISTER(t6, 14); 156REGISTER(t7, 15); 157// s0 - s7: Subroutine register variables. Subroutines that write to these 158// registers must restore their values before exiting so that the caller can 159// expect the values to be preserved. 160REGISTER(s0, 16); 161REGISTER(s1, 17); 162REGISTER(s2, 18); 163REGISTER(s3, 19); 164REGISTER(s4, 20); 165REGISTER(s5, 21); 166REGISTER(s6, 22); 167REGISTER(s7, 23); 168REGISTER(t8, 24); 169REGISTER(t9, 25); 170// k0, k1: Reserved for system calls and interrupt handlers. 171REGISTER(k0, 26); 172REGISTER(k1, 27); 173// gp: Reserved. 174REGISTER(gp, 28); 175// sp: Stack pointer. 176REGISTER(sp, 29); 177// fp: Frame pointer. 178REGISTER(fp, 30); 179// ra: Return address pointer. 180REGISTER(ra, 31); 181 182#undef REGISTER 183 184 185int ToNumber(Register reg); 186 187Register ToRegister(int num); 188 189// Coprocessor register. 190struct FPURegister { 191 static const int kMaxNumRegisters = v8::internal::kNumFPURegisters; 192 193 // TODO(plind): Warning, inconsistent numbering here. kNumFPURegisters refers 194 // to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to 195 // number of Double regs (64-bit regs, or FPU-reg-pairs). 196 197 // A few double registers are reserved: one as a scratch register and one to 198 // hold 0.0. 199 // f28: 0.0 200 // f30: scratch register. 201 static const int kNumReservedRegisters = 2; 202 static const int kMaxNumAllocatableRegisters = kMaxNumRegisters / 2 - 203 kNumReservedRegisters; 204 205 inline static int NumRegisters(); 206 inline static int NumAllocatableRegisters(); 207 inline static int ToAllocationIndex(FPURegister reg); 208 static const char* AllocationIndexToString(int index); 209 210 static FPURegister FromAllocationIndex(int index) { 211 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); 212 return from_code(index * 2); 213 } 214 215 static FPURegister from_code(int code) { 216 FPURegister r = { code }; 217 return r; 218 } 219 220 bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters ; } 221 bool is(FPURegister creg) const { return code_ == creg.code_; } 222 FPURegister low() const { 223 // Find low reg of a Double-reg pair, which is the reg itself. 224 ASSERT(code_ % 2 == 0); // Specified Double reg must be even. 225 FPURegister reg; 226 reg.code_ = code_; 227 ASSERT(reg.is_valid()); 228 return reg; 229 } 230 FPURegister high() const { 231 // Find high reg of a Doubel-reg pair, which is reg + 1. 232 ASSERT(code_ % 2 == 0); // Specified Double reg must be even. 233 FPURegister reg; 234 reg.code_ = code_ + 1; 235 ASSERT(reg.is_valid()); 236 return reg; 237 } 238 239 int code() const { 240 ASSERT(is_valid()); 241 return code_; 242 } 243 int bit() const { 244 ASSERT(is_valid()); 245 return 1 << code_; 246 } 247 void setcode(int f) { 248 code_ = f; 249 ASSERT(is_valid()); 250 } 251 // Unfortunately we can't make this private in a struct. 252 int code_; 253}; 254 255// V8 now supports the O32 ABI, and the FPU Registers are organized as 32 256// 32-bit registers, f0 through f31. When used as 'double' they are used 257// in pairs, starting with the even numbered register. So a double operation 258// on f0 really uses f0 and f1. 259// (Modern mips hardware also supports 32 64-bit registers, via setting 260// (priviledged) Status Register FR bit to 1. This is used by the N32 ABI, 261// but it is not in common use. Someday we will want to support this in v8.) 262 263// For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers. 264typedef FPURegister DoubleRegister; 265typedef FPURegister FloatRegister; 266 267const FPURegister no_freg = { -1 }; 268 269const FPURegister f0 = { 0 }; // Return value in hard float mode. 270const FPURegister f1 = { 1 }; 271const FPURegister f2 = { 2 }; 272const FPURegister f3 = { 3 }; 273const FPURegister f4 = { 4 }; 274const FPURegister f5 = { 5 }; 275const FPURegister f6 = { 6 }; 276const FPURegister f7 = { 7 }; 277const FPURegister f8 = { 8 }; 278const FPURegister f9 = { 9 }; 279const FPURegister f10 = { 10 }; 280const FPURegister f11 = { 11 }; 281const FPURegister f12 = { 12 }; // Arg 0 in hard float mode. 282const FPURegister f13 = { 13 }; 283const FPURegister f14 = { 14 }; // Arg 1 in hard float mode. 284const FPURegister f15 = { 15 }; 285const FPURegister f16 = { 16 }; 286const FPURegister f17 = { 17 }; 287const FPURegister f18 = { 18 }; 288const FPURegister f19 = { 19 }; 289const FPURegister f20 = { 20 }; 290const FPURegister f21 = { 21 }; 291const FPURegister f22 = { 22 }; 292const FPURegister f23 = { 23 }; 293const FPURegister f24 = { 24 }; 294const FPURegister f25 = { 25 }; 295const FPURegister f26 = { 26 }; 296const FPURegister f27 = { 27 }; 297const FPURegister f28 = { 28 }; 298const FPURegister f29 = { 29 }; 299const FPURegister f30 = { 30 }; 300const FPURegister f31 = { 31 }; 301 302// Register aliases. 303// cp is assumed to be a callee saved register. 304// Defined using #define instead of "static const Register&" because Clang 305// complains otherwise when a compilation unit that includes this header 306// doesn't use the variables. 307#define kRootRegister s6 308#define cp s7 309#define kLithiumScratchReg s3 310#define kLithiumScratchReg2 s4 311#define kLithiumScratchDouble f30 312#define kDoubleRegZero f28 313 314// FPU (coprocessor 1) control registers. 315// Currently only FCSR (#31) is implemented. 316struct FPUControlRegister { 317 bool is_valid() const { return code_ == kFCSRRegister; } 318 bool is(FPUControlRegister creg) const { return code_ == creg.code_; } 319 int code() const { 320 ASSERT(is_valid()); 321 return code_; 322 } 323 int bit() const { 324 ASSERT(is_valid()); 325 return 1 << code_; 326 } 327 void setcode(int f) { 328 code_ = f; 329 ASSERT(is_valid()); 330 } 331 // Unfortunately we can't make this private in a struct. 332 int code_; 333}; 334 335const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister }; 336const FPUControlRegister FCSR = { kFCSRRegister }; 337 338 339// ----------------------------------------------------------------------------- 340// Machine instruction Operands. 341 342// Class Operand represents a shifter operand in data processing instructions. 343class Operand BASE_EMBEDDED { 344 public: 345 // Immediate. 346 INLINE(explicit Operand(int32_t immediate, 347 RelocInfo::Mode rmode = RelocInfo::NONE32)); 348 INLINE(explicit Operand(const ExternalReference& f)); 349 INLINE(explicit Operand(const char* s)); 350 INLINE(explicit Operand(Object** opp)); 351 INLINE(explicit Operand(Context** cpp)); 352 explicit Operand(Handle<Object> handle); 353 INLINE(explicit Operand(Smi* value)); 354 355 // Register. 356 INLINE(explicit Operand(Register rm)); 357 358 // Return true if this is a register operand. 359 INLINE(bool is_reg() const); 360 361 inline int32_t immediate() const { 362 ASSERT(!is_reg()); 363 return imm32_; 364 } 365 366 Register rm() const { return rm_; } 367 368 private: 369 Register rm_; 370 int32_t imm32_; // Valid if rm_ == no_reg. 371 RelocInfo::Mode rmode_; 372 373 friend class Assembler; 374 friend class MacroAssembler; 375}; 376 377 378// On MIPS we have only one adressing mode with base_reg + offset. 379// Class MemOperand represents a memory operand in load and store instructions. 380class MemOperand : public Operand { 381 public: 382 explicit MemOperand(Register rn, int32_t offset = 0); 383 int32_t offset() const { return offset_; } 384 385 bool OffsetIsInt16Encodable() const { 386 return is_int16(offset_); 387 } 388 389 private: 390 int32_t offset_; 391 392 friend class Assembler; 393}; 394 395 396// CpuFeatures keeps track of which features are supported by the target CPU. 397// Supported features must be enabled by a CpuFeatureScope before use. 398class CpuFeatures : public AllStatic { 399 public: 400 // Detect features of the target CPU. Set safe defaults if the serializer 401 // is enabled (snapshots must be portable). 402 static void Probe(); 403 404 // Check whether a feature is supported by the target CPU. 405 static bool IsSupported(CpuFeature f) { 406 ASSERT(initialized_); 407 return (supported_ & (1u << f)) != 0; 408 } 409 410 static bool IsFoundByRuntimeProbingOnly(CpuFeature f) { 411 ASSERT(initialized_); 412 return (found_by_runtime_probing_only_ & 413 (static_cast<uint64_t>(1) << f)) != 0; 414 } 415 416 static bool IsSafeForSnapshot(CpuFeature f) { 417 return (IsSupported(f) && 418 (!Serializer::enabled() || !IsFoundByRuntimeProbingOnly(f))); 419 } 420 421 private: 422#ifdef DEBUG 423 static bool initialized_; 424#endif 425 static unsigned supported_; 426 static unsigned found_by_runtime_probing_only_; 427 428 friend class ExternalReference; 429 DISALLOW_COPY_AND_ASSIGN(CpuFeatures); 430}; 431 432 433class Assembler : public AssemblerBase { 434 public: 435 // Create an assembler. Instructions and relocation information are emitted 436 // into a buffer, with the instructions starting from the beginning and the 437 // relocation information starting from the end of the buffer. See CodeDesc 438 // for a detailed comment on the layout (globals.h). 439 // 440 // If the provided buffer is NULL, the assembler allocates and grows its own 441 // buffer, and buffer_size determines the initial buffer size. The buffer is 442 // owned by the assembler and deallocated upon destruction of the assembler. 443 // 444 // If the provided buffer is not NULL, the assembler uses the provided buffer 445 // for code generation and assumes its size to be buffer_size. If the buffer 446 // is too small, a fatal error occurs. No deallocation of the buffer is done 447 // upon destruction of the assembler. 448 Assembler(Isolate* isolate, void* buffer, int buffer_size); 449 virtual ~Assembler() { } 450 451 // GetCode emits any pending (non-emitted) code and fills the descriptor 452 // desc. GetCode() is idempotent; it returns the same result if no other 453 // Assembler functions are invoked in between GetCode() calls. 454 void GetCode(CodeDesc* desc); 455 456 // Label operations & relative jumps (PPUM Appendix D). 457 // 458 // Takes a branch opcode (cc) and a label (L) and generates 459 // either a backward branch or a forward branch and links it 460 // to the label fixup chain. Usage: 461 // 462 // Label L; // unbound label 463 // j(cc, &L); // forward branch to unbound label 464 // bind(&L); // bind label to the current pc 465 // j(cc, &L); // backward branch to bound label 466 // bind(&L); // illegal: a label may be bound only once 467 // 468 // Note: The same Label can be used for forward and backward branches 469 // but it may be bound only once. 470 void bind(Label* L); // Binds an unbound label L to current code position. 471 // Determines if Label is bound and near enough so that branch instruction 472 // can be used to reach it, instead of jump instruction. 473 bool is_near(Label* L); 474 475 // Returns the branch offset to the given label from the current code 476 // position. Links the label to the current position if it is still unbound. 477 // Manages the jump elimination optimization if the second parameter is true. 478 int32_t branch_offset(Label* L, bool jump_elimination_allowed); 479 int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) { 480 int32_t o = branch_offset(L, jump_elimination_allowed); 481 ASSERT((o & 3) == 0); // Assert the offset is aligned. 482 return o >> 2; 483 } 484 uint32_t jump_address(Label* L); 485 486 // Puts a labels target address at the given position. 487 // The high 8 bits are set to zero. 488 void label_at_put(Label* L, int at_offset); 489 490 // Read/Modify the code target address in the branch/call instruction at pc. 491 static Address target_address_at(Address pc); 492 static void set_target_address_at(Address pc, Address target); 493 494 // Return the code target address at a call site from the return address 495 // of that call in the instruction stream. 496 inline static Address target_address_from_return_address(Address pc); 497 498 static void JumpLabelToJumpRegister(Address pc); 499 500 static void QuietNaN(HeapObject* nan); 501 502 // This sets the branch destination (which gets loaded at the call address). 503 // This is for calls and branches within generated code. The serializer 504 // has already deserialized the lui/ori instructions etc. 505 inline static void deserialization_set_special_target_at( 506 Address instruction_payload, Address target) { 507 set_target_address_at( 508 instruction_payload - kInstructionsFor32BitConstant * kInstrSize, 509 target); 510 } 511 512 // This sets the branch destination. 513 // This is for calls and branches to runtime code. 514 inline static void set_external_target_at(Address instruction_payload, 515 Address target) { 516 set_target_address_at(instruction_payload, target); 517 } 518 519 // Size of an instruction. 520 static const int kInstrSize = sizeof(Instr); 521 522 // Difference between address of current opcode and target address offset. 523 static const int kBranchPCOffset = 4; 524 525 // Here we are patching the address in the LUI/ORI instruction pair. 526 // These values are used in the serialization process and must be zero for 527 // MIPS platform, as Code, Embedded Object or External-reference pointers 528 // are split across two consecutive instructions and don't exist separately 529 // in the code, so the serializer should not step forwards in memory after 530 // a target is resolved and written. 531 static const int kSpecialTargetSize = 0; 532 533 // Number of consecutive instructions used to store 32bit constant. 534 // Before jump-optimizations, this constant was used in 535 // RelocInfo::target_address_address() function to tell serializer address of 536 // the instruction that follows LUI/ORI instruction pair. Now, with new jump 537 // optimization, where jump-through-register instruction that usually 538 // follows LUI/ORI pair is substituted with J/JAL, this constant equals 539 // to 3 instructions (LUI+ORI+J/JAL/JR/JALR). 540 static const int kInstructionsFor32BitConstant = 3; 541 542 // Distance between the instruction referring to the address of the call 543 // target and the return address. 544 static const int kCallTargetAddressOffset = 4 * kInstrSize; 545 546 // Distance between start of patched return sequence and the emitted address 547 // to jump to. 548 static const int kPatchReturnSequenceAddressOffset = 0; 549 550 // Distance between start of patched debug break slot and the emitted address 551 // to jump to. 552 static const int kPatchDebugBreakSlotAddressOffset = 0 * kInstrSize; 553 554 // Difference between address of current opcode and value read from pc 555 // register. 556 static const int kPcLoadDelta = 4; 557 558 static const int kPatchDebugBreakSlotReturnOffset = 4 * kInstrSize; 559 560 // Number of instructions used for the JS return sequence. The constant is 561 // used by the debugger to patch the JS return sequence. 562 static const int kJSReturnSequenceInstructions = 7; 563 static const int kDebugBreakSlotInstructions = 4; 564 static const int kDebugBreakSlotLength = 565 kDebugBreakSlotInstructions * kInstrSize; 566 567 568 // --------------------------------------------------------------------------- 569 // Code generation. 570 571 // Insert the smallest number of nop instructions 572 // possible to align the pc offset to a multiple 573 // of m. m must be a power of 2 (>= 4). 574 void Align(int m); 575 // Aligns code to something that's optimal for a jump target for the platform. 576 void CodeTargetAlign(); 577 578 // Different nop operations are used by the code generator to detect certain 579 // states of the generated code. 580 enum NopMarkerTypes { 581 NON_MARKING_NOP = 0, 582 DEBUG_BREAK_NOP, 583 // IC markers. 584 PROPERTY_ACCESS_INLINED, 585 PROPERTY_ACCESS_INLINED_CONTEXT, 586 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE, 587 // Helper values. 588 LAST_CODE_MARKER, 589 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED, 590 // Code aging 591 CODE_AGE_MARKER_NOP = 6, 592 CODE_AGE_SEQUENCE_NOP 593 }; 594 595 // Type == 0 is the default non-marking nop. For mips this is a 596 // sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero 597 // marking, to avoid conflict with ssnop and ehb instructions. 598 void nop(unsigned int type = 0) { 599 ASSERT(type < 32); 600 Register nop_rt_reg = (type == 0) ? zero_reg : at; 601 sll(zero_reg, nop_rt_reg, type, true); 602 } 603 604 605 // --------Branch-and-jump-instructions---------- 606 // We don't use likely variant of instructions. 607 void b(int16_t offset); 608 void b(Label* L) { b(branch_offset(L, false)>>2); } 609 void bal(int16_t offset); 610 void bal(Label* L) { bal(branch_offset(L, false)>>2); } 611 612 void beq(Register rs, Register rt, int16_t offset); 613 void beq(Register rs, Register rt, Label* L) { 614 beq(rs, rt, branch_offset(L, false) >> 2); 615 } 616 void bgez(Register rs, int16_t offset); 617 void bgezal(Register rs, int16_t offset); 618 void bgtz(Register rs, int16_t offset); 619 void blez(Register rs, int16_t offset); 620 void bltz(Register rs, int16_t offset); 621 void bltzal(Register rs, int16_t offset); 622 void bne(Register rs, Register rt, int16_t offset); 623 void bne(Register rs, Register rt, Label* L) { 624 bne(rs, rt, branch_offset(L, false)>>2); 625 } 626 627 // Never use the int16_t b(l)cond version with a branch offset 628 // instead of using the Label* version. 629 630 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits. 631 void j(int32_t target); 632 void jal(int32_t target); 633 void jalr(Register rs, Register rd = ra); 634 void jr(Register target); 635 void j_or_jr(int32_t target, Register rs); 636 void jal_or_jalr(int32_t target, Register rs); 637 638 639 //-------Data-processing-instructions--------- 640 641 // Arithmetic. 642 void addu(Register rd, Register rs, Register rt); 643 void subu(Register rd, Register rs, Register rt); 644 void mult(Register rs, Register rt); 645 void multu(Register rs, Register rt); 646 void div(Register rs, Register rt); 647 void divu(Register rs, Register rt); 648 void mul(Register rd, Register rs, Register rt); 649 650 void addiu(Register rd, Register rs, int32_t j); 651 652 // Logical. 653 void and_(Register rd, Register rs, Register rt); 654 void or_(Register rd, Register rs, Register rt); 655 void xor_(Register rd, Register rs, Register rt); 656 void nor(Register rd, Register rs, Register rt); 657 658 void andi(Register rd, Register rs, int32_t j); 659 void ori(Register rd, Register rs, int32_t j); 660 void xori(Register rd, Register rs, int32_t j); 661 void lui(Register rd, int32_t j); 662 663 // Shifts. 664 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop 665 // and may cause problems in normal code. coming_from_nop makes sure this 666 // doesn't happen. 667 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false); 668 void sllv(Register rd, Register rt, Register rs); 669 void srl(Register rd, Register rt, uint16_t sa); 670 void srlv(Register rd, Register rt, Register rs); 671 void sra(Register rt, Register rd, uint16_t sa); 672 void srav(Register rt, Register rd, Register rs); 673 void rotr(Register rd, Register rt, uint16_t sa); 674 void rotrv(Register rd, Register rt, Register rs); 675 676 677 //------------Memory-instructions------------- 678 679 void lb(Register rd, const MemOperand& rs); 680 void lbu(Register rd, const MemOperand& rs); 681 void lh(Register rd, const MemOperand& rs); 682 void lhu(Register rd, const MemOperand& rs); 683 void lw(Register rd, const MemOperand& rs); 684 void lwl(Register rd, const MemOperand& rs); 685 void lwr(Register rd, const MemOperand& rs); 686 void sb(Register rd, const MemOperand& rs); 687 void sh(Register rd, const MemOperand& rs); 688 void sw(Register rd, const MemOperand& rs); 689 void swl(Register rd, const MemOperand& rs); 690 void swr(Register rd, const MemOperand& rs); 691 692 693 //-------------Misc-instructions-------------- 694 695 // Break / Trap instructions. 696 void break_(uint32_t code, bool break_as_stop = false); 697 void stop(const char* msg, uint32_t code = kMaxStopCode); 698 void tge(Register rs, Register rt, uint16_t code); 699 void tgeu(Register rs, Register rt, uint16_t code); 700 void tlt(Register rs, Register rt, uint16_t code); 701 void tltu(Register rs, Register rt, uint16_t code); 702 void teq(Register rs, Register rt, uint16_t code); 703 void tne(Register rs, Register rt, uint16_t code); 704 705 // Move from HI/LO register. 706 void mfhi(Register rd); 707 void mflo(Register rd); 708 709 // Set on less than. 710 void slt(Register rd, Register rs, Register rt); 711 void sltu(Register rd, Register rs, Register rt); 712 void slti(Register rd, Register rs, int32_t j); 713 void sltiu(Register rd, Register rs, int32_t j); 714 715 // Conditional move. 716 void movz(Register rd, Register rs, Register rt); 717 void movn(Register rd, Register rs, Register rt); 718 void movt(Register rd, Register rs, uint16_t cc = 0); 719 void movf(Register rd, Register rs, uint16_t cc = 0); 720 721 // Bit twiddling. 722 void clz(Register rd, Register rs); 723 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); 724 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); 725 726 //--------Coprocessor-instructions---------------- 727 728 // Load, store, and move. 729 void lwc1(FPURegister fd, const MemOperand& src); 730 void ldc1(FPURegister fd, const MemOperand& src); 731 732 void swc1(FPURegister fs, const MemOperand& dst); 733 void sdc1(FPURegister fs, const MemOperand& dst); 734 735 void mtc1(Register rt, FPURegister fs); 736 void mfc1(Register rt, FPURegister fs); 737 738 void ctc1(Register rt, FPUControlRegister fs); 739 void cfc1(Register rt, FPUControlRegister fs); 740 741 // Arithmetic. 742 void add_d(FPURegister fd, FPURegister fs, FPURegister ft); 743 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft); 744 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft); 745 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 746 void div_d(FPURegister fd, FPURegister fs, FPURegister ft); 747 void abs_d(FPURegister fd, FPURegister fs); 748 void mov_d(FPURegister fd, FPURegister fs); 749 void neg_d(FPURegister fd, FPURegister fs); 750 void sqrt_d(FPURegister fd, FPURegister fs); 751 752 // Conversion. 753 void cvt_w_s(FPURegister fd, FPURegister fs); 754 void cvt_w_d(FPURegister fd, FPURegister fs); 755 void trunc_w_s(FPURegister fd, FPURegister fs); 756 void trunc_w_d(FPURegister fd, FPURegister fs); 757 void round_w_s(FPURegister fd, FPURegister fs); 758 void round_w_d(FPURegister fd, FPURegister fs); 759 void floor_w_s(FPURegister fd, FPURegister fs); 760 void floor_w_d(FPURegister fd, FPURegister fs); 761 void ceil_w_s(FPURegister fd, FPURegister fs); 762 void ceil_w_d(FPURegister fd, FPURegister fs); 763 764 void cvt_l_s(FPURegister fd, FPURegister fs); 765 void cvt_l_d(FPURegister fd, FPURegister fs); 766 void trunc_l_s(FPURegister fd, FPURegister fs); 767 void trunc_l_d(FPURegister fd, FPURegister fs); 768 void round_l_s(FPURegister fd, FPURegister fs); 769 void round_l_d(FPURegister fd, FPURegister fs); 770 void floor_l_s(FPURegister fd, FPURegister fs); 771 void floor_l_d(FPURegister fd, FPURegister fs); 772 void ceil_l_s(FPURegister fd, FPURegister fs); 773 void ceil_l_d(FPURegister fd, FPURegister fs); 774 775 void cvt_s_w(FPURegister fd, FPURegister fs); 776 void cvt_s_l(FPURegister fd, FPURegister fs); 777 void cvt_s_d(FPURegister fd, FPURegister fs); 778 779 void cvt_d_w(FPURegister fd, FPURegister fs); 780 void cvt_d_l(FPURegister fd, FPURegister fs); 781 void cvt_d_s(FPURegister fd, FPURegister fs); 782 783 // Conditions and branches. 784 void c(FPUCondition cond, SecondaryField fmt, 785 FPURegister ft, FPURegister fs, uint16_t cc = 0); 786 787 void bc1f(int16_t offset, uint16_t cc = 0); 788 void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); } 789 void bc1t(int16_t offset, uint16_t cc = 0); 790 void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); } 791 void fcmp(FPURegister src1, const double src2, FPUCondition cond); 792 793 // Check the code size generated from label to here. 794 int SizeOfCodeGeneratedSince(Label* label) { 795 return pc_offset() - label->pos(); 796 } 797 798 // Check the number of instructions generated from label to here. 799 int InstructionsGeneratedSince(Label* label) { 800 return SizeOfCodeGeneratedSince(label) / kInstrSize; 801 } 802 803 // Class for scoping postponing the trampoline pool generation. 804 class BlockTrampolinePoolScope { 805 public: 806 explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) { 807 assem_->StartBlockTrampolinePool(); 808 } 809 ~BlockTrampolinePoolScope() { 810 assem_->EndBlockTrampolinePool(); 811 } 812 813 private: 814 Assembler* assem_; 815 816 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope); 817 }; 818 819 // Class for postponing the assembly buffer growth. Typically used for 820 // sequences of instructions that must be emitted as a unit, before 821 // buffer growth (and relocation) can occur. 822 // This blocking scope is not nestable. 823 class BlockGrowBufferScope { 824 public: 825 explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) { 826 assem_->StartBlockGrowBuffer(); 827 } 828 ~BlockGrowBufferScope() { 829 assem_->EndBlockGrowBuffer(); 830 } 831 832 private: 833 Assembler* assem_; 834 835 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope); 836 }; 837 838 // Debugging. 839 840 // Mark address of the ExitJSFrame code. 841 void RecordJSReturn(); 842 843 // Mark address of a debug break slot. 844 void RecordDebugBreakSlot(); 845 846 // Record the AST id of the CallIC being compiled, so that it can be placed 847 // in the relocation information. 848 void SetRecordedAstId(TypeFeedbackId ast_id) { 849 ASSERT(recorded_ast_id_.IsNone()); 850 recorded_ast_id_ = ast_id; 851 } 852 853 TypeFeedbackId RecordedAstId() { 854 ASSERT(!recorded_ast_id_.IsNone()); 855 return recorded_ast_id_; 856 } 857 858 void ClearRecordedAstId() { recorded_ast_id_ = TypeFeedbackId::None(); } 859 860 // Record a comment relocation entry that can be used by a disassembler. 861 // Use --code-comments to enable. 862 void RecordComment(const char* msg); 863 864 static int RelocateInternalReference(byte* pc, intptr_t pc_delta); 865 866 // Writes a single byte or word of data in the code stream. Used for 867 // inline tables, e.g., jump-tables. 868 void db(uint8_t data); 869 void dd(uint32_t data); 870 871 PositionsRecorder* positions_recorder() { return &positions_recorder_; } 872 873 // Postpone the generation of the trampoline pool for the specified number of 874 // instructions. 875 void BlockTrampolinePoolFor(int instructions); 876 877 // Check if there is less than kGap bytes available in the buffer. 878 // If this is the case, we need to grow the buffer before emitting 879 // an instruction or relocation information. 880 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; } 881 882 // Get the number of bytes available in the buffer. 883 inline int available_space() const { return reloc_info_writer.pos() - pc_; } 884 885 // Read/patch instructions. 886 static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); } 887 static void instr_at_put(byte* pc, Instr instr) { 888 *reinterpret_cast<Instr*>(pc) = instr; 889 } 890 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); } 891 void instr_at_put(int pos, Instr instr) { 892 *reinterpret_cast<Instr*>(buffer_ + pos) = instr; 893 } 894 895 // Check if an instruction is a branch of some kind. 896 static bool IsBranch(Instr instr); 897 static bool IsBeq(Instr instr); 898 static bool IsBne(Instr instr); 899 900 static bool IsJump(Instr instr); 901 static bool IsJ(Instr instr); 902 static bool IsLui(Instr instr); 903 static bool IsOri(Instr instr); 904 905 static bool IsJal(Instr instr); 906 static bool IsJr(Instr instr); 907 static bool IsJalr(Instr instr); 908 909 static bool IsNop(Instr instr, unsigned int type); 910 static bool IsPop(Instr instr); 911 static bool IsPush(Instr instr); 912 static bool IsLwRegFpOffset(Instr instr); 913 static bool IsSwRegFpOffset(Instr instr); 914 static bool IsLwRegFpNegOffset(Instr instr); 915 static bool IsSwRegFpNegOffset(Instr instr); 916 917 static Register GetRtReg(Instr instr); 918 static Register GetRsReg(Instr instr); 919 static Register GetRdReg(Instr instr); 920 921 static uint32_t GetRt(Instr instr); 922 static uint32_t GetRtField(Instr instr); 923 static uint32_t GetRs(Instr instr); 924 static uint32_t GetRsField(Instr instr); 925 static uint32_t GetRd(Instr instr); 926 static uint32_t GetRdField(Instr instr); 927 static uint32_t GetSa(Instr instr); 928 static uint32_t GetSaField(Instr instr); 929 static uint32_t GetOpcodeField(Instr instr); 930 static uint32_t GetFunction(Instr instr); 931 static uint32_t GetFunctionField(Instr instr); 932 static uint32_t GetImmediate16(Instr instr); 933 static uint32_t GetLabelConst(Instr instr); 934 935 static int32_t GetBranchOffset(Instr instr); 936 static bool IsLw(Instr instr); 937 static int16_t GetLwOffset(Instr instr); 938 static Instr SetLwOffset(Instr instr, int16_t offset); 939 940 static bool IsSw(Instr instr); 941 static Instr SetSwOffset(Instr instr, int16_t offset); 942 static bool IsAddImmediate(Instr instr); 943 static Instr SetAddImmediateOffset(Instr instr, int16_t offset); 944 945 static bool IsAndImmediate(Instr instr); 946 static bool IsEmittedConstant(Instr instr); 947 948 void CheckTrampolinePool(); 949 950 protected: 951 // Relocation for a type-recording IC has the AST id added to it. This 952 // member variable is a way to pass the information from the call site to 953 // the relocation info. 954 TypeFeedbackId recorded_ast_id_; 955 956 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; } 957 958 // Decode branch instruction at pos and return branch target pos. 959 int target_at(int32_t pos); 960 961 // Patch branch instruction at pos to branch to given branch target pos. 962 void target_at_put(int32_t pos, int32_t target_pos); 963 964 // Say if we need to relocate with this mode. 965 bool MustUseReg(RelocInfo::Mode rmode); 966 967 // Record reloc info for current pc_. 968 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 969 970 // Block the emission of the trampoline pool before pc_offset. 971 void BlockTrampolinePoolBefore(int pc_offset) { 972 if (no_trampoline_pool_before_ < pc_offset) 973 no_trampoline_pool_before_ = pc_offset; 974 } 975 976 void StartBlockTrampolinePool() { 977 trampoline_pool_blocked_nesting_++; 978 } 979 980 void EndBlockTrampolinePool() { 981 trampoline_pool_blocked_nesting_--; 982 } 983 984 bool is_trampoline_pool_blocked() const { 985 return trampoline_pool_blocked_nesting_ > 0; 986 } 987 988 bool has_exception() const { 989 return internal_trampoline_exception_; 990 } 991 992 void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi); 993 994 bool is_trampoline_emitted() const { 995 return trampoline_emitted_; 996 } 997 998 // Temporarily block automatic assembly buffer growth. 999 void StartBlockGrowBuffer() { 1000 ASSERT(!block_buffer_growth_); 1001 block_buffer_growth_ = true; 1002 } 1003 1004 void EndBlockGrowBuffer() { 1005 ASSERT(block_buffer_growth_); 1006 block_buffer_growth_ = false; 1007 } 1008 1009 bool is_buffer_growth_blocked() const { 1010 return block_buffer_growth_; 1011 } 1012 1013 private: 1014 // Buffer size and constant pool distance are checked together at regular 1015 // intervals of kBufferCheckInterval emitted bytes. 1016 static const int kBufferCheckInterval = 1*KB/2; 1017 1018 // Code generation. 1019 // The relocation writer's position is at least kGap bytes below the end of 1020 // the generated instructions. This is so that multi-instruction sequences do 1021 // not have to check for overflow. The same is true for writes of large 1022 // relocation info entries. 1023 static const int kGap = 32; 1024 1025 1026 // Repeated checking whether the trampoline pool should be emitted is rather 1027 // expensive. By default we only check again once a number of instructions 1028 // has been generated. 1029 static const int kCheckConstIntervalInst = 32; 1030 static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize; 1031 1032 int next_buffer_check_; // pc offset of next buffer check. 1033 1034 // Emission of the trampoline pool may be blocked in some code sequences. 1035 int trampoline_pool_blocked_nesting_; // Block emission if this is not zero. 1036 int no_trampoline_pool_before_; // Block emission before this pc offset. 1037 1038 // Keep track of the last emitted pool to guarantee a maximal distance. 1039 int last_trampoline_pool_end_; // pc offset of the end of the last pool. 1040 1041 // Automatic growth of the assembly buffer may be blocked for some sequences. 1042 bool block_buffer_growth_; // Block growth when true. 1043 1044 // Relocation information generation. 1045 // Each relocation is encoded as a variable size value. 1046 static const int kMaxRelocSize = RelocInfoWriter::kMaxSize; 1047 RelocInfoWriter reloc_info_writer; 1048 1049 // The bound position, before this we cannot do instruction elimination. 1050 int last_bound_pos_; 1051 1052 // Code emission. 1053 inline void CheckBuffer(); 1054 void GrowBuffer(); 1055 inline void emit(Instr x); 1056 inline void CheckTrampolinePoolQuick(); 1057 1058 // Instruction generation. 1059 // We have 3 different kind of encoding layout on MIPS. 1060 // However due to many different types of objects encoded in the same fields 1061 // we have quite a few aliases for each mode. 1062 // Using the same structure to refer to Register and FPURegister would spare a 1063 // few aliases, but mixing both does not look clean to me. 1064 // Anyway we could surely implement this differently. 1065 1066 void GenInstrRegister(Opcode opcode, 1067 Register rs, 1068 Register rt, 1069 Register rd, 1070 uint16_t sa = 0, 1071 SecondaryField func = NULLSF); 1072 1073 void GenInstrRegister(Opcode opcode, 1074 Register rs, 1075 Register rt, 1076 uint16_t msb, 1077 uint16_t lsb, 1078 SecondaryField func); 1079 1080 void GenInstrRegister(Opcode opcode, 1081 SecondaryField fmt, 1082 FPURegister ft, 1083 FPURegister fs, 1084 FPURegister fd, 1085 SecondaryField func = NULLSF); 1086 1087 void GenInstrRegister(Opcode opcode, 1088 FPURegister fr, 1089 FPURegister ft, 1090 FPURegister fs, 1091 FPURegister fd, 1092 SecondaryField func = NULLSF); 1093 1094 void GenInstrRegister(Opcode opcode, 1095 SecondaryField fmt, 1096 Register rt, 1097 FPURegister fs, 1098 FPURegister fd, 1099 SecondaryField func = NULLSF); 1100 1101 void GenInstrRegister(Opcode opcode, 1102 SecondaryField fmt, 1103 Register rt, 1104 FPUControlRegister fs, 1105 SecondaryField func = NULLSF); 1106 1107 1108 void GenInstrImmediate(Opcode opcode, 1109 Register rs, 1110 Register rt, 1111 int32_t j); 1112 void GenInstrImmediate(Opcode opcode, 1113 Register rs, 1114 SecondaryField SF, 1115 int32_t j); 1116 void GenInstrImmediate(Opcode opcode, 1117 Register r1, 1118 FPURegister r2, 1119 int32_t j); 1120 1121 1122 void GenInstrJump(Opcode opcode, 1123 uint32_t address); 1124 1125 // Helpers. 1126 void LoadRegPlusOffsetToAt(const MemOperand& src); 1127 1128 // Labels. 1129 void print(Label* L); 1130 void bind_to(Label* L, int pos); 1131 void next(Label* L); 1132 1133 // One trampoline consists of: 1134 // - space for trampoline slots, 1135 // - space for labels. 1136 // 1137 // Space for trampoline slots is equal to slot_count * 2 * kInstrSize. 1138 // Space for trampoline slots preceeds space for labels. Each label is of one 1139 // instruction size, so total amount for labels is equal to 1140 // label_count * kInstrSize. 1141 class Trampoline { 1142 public: 1143 Trampoline() { 1144 start_ = 0; 1145 next_slot_ = 0; 1146 free_slot_count_ = 0; 1147 end_ = 0; 1148 } 1149 Trampoline(int start, int slot_count) { 1150 start_ = start; 1151 next_slot_ = start; 1152 free_slot_count_ = slot_count; 1153 end_ = start + slot_count * kTrampolineSlotsSize; 1154 } 1155 int start() { 1156 return start_; 1157 } 1158 int end() { 1159 return end_; 1160 } 1161 int take_slot() { 1162 int trampoline_slot = kInvalidSlotPos; 1163 if (free_slot_count_ <= 0) { 1164 // We have run out of space on trampolines. 1165 // Make sure we fail in debug mode, so we become aware of each case 1166 // when this happens. 1167 ASSERT(0); 1168 // Internal exception will be caught. 1169 } else { 1170 trampoline_slot = next_slot_; 1171 free_slot_count_--; 1172 next_slot_ += kTrampolineSlotsSize; 1173 } 1174 return trampoline_slot; 1175 } 1176 1177 private: 1178 int start_; 1179 int end_; 1180 int next_slot_; 1181 int free_slot_count_; 1182 }; 1183 1184 int32_t get_trampoline_entry(int32_t pos); 1185 int unbound_labels_count_; 1186 // If trampoline is emitted, generated code is becoming large. As this is 1187 // already a slow case which can possibly break our code generation for the 1188 // extreme case, we use this information to trigger different mode of 1189 // branch instruction generation, where we use jump instructions rather 1190 // than regular branch instructions. 1191 bool trampoline_emitted_; 1192 static const int kTrampolineSlotsSize = 4 * kInstrSize; 1193 static const int kMaxBranchOffset = (1 << (18 - 1)) - 1; 1194 static const int kInvalidSlotPos = -1; 1195 1196 Trampoline trampoline_; 1197 bool internal_trampoline_exception_; 1198 1199 friend class RegExpMacroAssemblerMIPS; 1200 friend class RelocInfo; 1201 friend class CodePatcher; 1202 friend class BlockTrampolinePoolScope; 1203 1204 PositionsRecorder positions_recorder_; 1205 friend class PositionsRecorder; 1206 friend class EnsureSpace; 1207}; 1208 1209 1210class EnsureSpace BASE_EMBEDDED { 1211 public: 1212 explicit EnsureSpace(Assembler* assembler) { 1213 assembler->CheckBuffer(); 1214 } 1215}; 1216 1217} } // namespace v8::internal 1218 1219#endif // V8_ARM_ASSEMBLER_MIPS_H_ 1220