1633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef _ASM_DMA_MAPPING_H 2633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define _ASM_DMA_MAPPING_H 3633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 4633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <asm/scatterlist.h> 5633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <asm/cache.h> 6633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 7633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamvoid *dma_alloc_noncoherent(struct device *dev, size_t size, 8633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham dma_addr_t *dma_handle, gfp_t flag); 9633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 10633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamvoid dma_free_noncoherent(struct device *dev, size_t size, 11633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham void *vaddr, dma_addr_t dma_handle); 12633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 13633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamvoid *dma_alloc_coherent(struct device *dev, size_t size, 14633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham dma_addr_t *dma_handle, gfp_t flag); 15633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 16633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamvoid dma_free_coherent(struct device *dev, size_t size, 17633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham void *vaddr, dma_addr_t dma_handle); 18633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 19633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, 20633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham enum dma_data_direction direction); 21633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, 22633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham size_t size, enum dma_data_direction direction); 23633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, 24633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham enum dma_data_direction direction); 25633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern dma_addr_t dma_map_page(struct device *dev, struct page *page, 26633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham unsigned long offset, size_t size, enum dma_data_direction direction); 27633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void dma_unmap_page(struct device *dev, dma_addr_t dma_address, 28633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham size_t size, enum dma_data_direction direction); 29633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, 30633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham int nhwentries, enum dma_data_direction direction); 31633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, 32633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham size_t size, enum dma_data_direction direction); 33633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void dma_sync_single_for_device(struct device *dev, 34633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham dma_addr_t dma_handle, size_t size, enum dma_data_direction direction); 35633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void dma_sync_single_range_for_cpu(struct device *dev, 36633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham dma_addr_t dma_handle, unsigned long offset, size_t size, 37633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham enum dma_data_direction direction); 38633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void dma_sync_single_range_for_device(struct device *dev, 39633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham dma_addr_t dma_handle, unsigned long offset, size_t size, 40633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham enum dma_data_direction direction); 41633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, 42633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham int nelems, enum dma_data_direction direction); 43633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, 44633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham int nelems, enum dma_data_direction direction); 45633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr); 46633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern int dma_supported(struct device *dev, u64 mask); 47633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 48633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstatic inline int 49633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamdma_set_mask(struct device *dev, u64 mask) 50633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham{ 51633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham if(!dev->dma_mask || !dma_supported(dev, mask)) 52633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham return -EIO; 53633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 54633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham *dev->dma_mask = mask; 55633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 56633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham return 0; 57633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} 58633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 59633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstatic inline int 60633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamdma_get_cache_alignment(void) 61633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham{ 62633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* XXX Largest on any MIPS */ 63633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham return 128; 64633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} 65633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 66633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr); 67633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 68633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, 69633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham enum dma_data_direction direction); 70633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 71633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if 0 72633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY 73633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 74633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, 75633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham dma_addr_t device_addr, size_t size, int flags); 76633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void dma_release_declared_memory(struct device *dev); 77633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void * dma_mark_declared_memory_occupied(struct device *dev, 78633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham dma_addr_t device_addr, size_t size); 79633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 80633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 81633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* _ASM_DMA_MAPPING_H */ 82