LiveIntervalAnalysis.h revision a62efd82ccb979df9e7b8f99913c83d698a6994e
1//===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass. Given some numbering of 11// each the machine instructions (in this implemention depth-first order) an 12// interval [i, j) is said to be a live interval for register v if there is no 13// instruction with number j' > j such that v is live at j' and there is no 14// instruction with number i' < i such that v is live at i'. In this 15// implementation intervals can have holes, i.e. an interval might look like 16// [1,20), [50,65), [1000,1001). 17// 18//===----------------------------------------------------------------------===// 19 20#ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H 21#define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H 22 23#include "llvm/CodeGen/MachineBasicBlock.h" 24#include "llvm/CodeGen/MachineFunctionPass.h" 25#include "llvm/CodeGen/LiveInterval.h" 26#include "llvm/CodeGen/SlotIndexes.h" 27#include "llvm/ADT/BitVector.h" 28#include "llvm/ADT/DenseMap.h" 29#include "llvm/ADT/SmallPtrSet.h" 30#include "llvm/ADT/SmallVector.h" 31#include "llvm/Support/Allocator.h" 32#include <cmath> 33#include <iterator> 34 35namespace llvm { 36 37 class AliasAnalysis; 38 class LiveVariables; 39 class MachineLoopInfo; 40 class TargetRegisterInfo; 41 class MachineRegisterInfo; 42 class TargetInstrInfo; 43 class TargetRegisterClass; 44 class VirtRegMap; 45 46 class LiveIntervals : public MachineFunctionPass { 47 MachineFunction* mf_; 48 MachineRegisterInfo* mri_; 49 const TargetMachine* tm_; 50 const TargetRegisterInfo* tri_; 51 const TargetInstrInfo* tii_; 52 AliasAnalysis *aa_; 53 LiveVariables* lv_; 54 SlotIndexes* indexes_; 55 56 /// Special pool allocator for VNInfo's (LiveInterval val#). 57 /// 58 VNInfo::Allocator VNInfoAllocator; 59 60 typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap; 61 Reg2IntervalMap r2iMap_; 62 63 /// allocatableRegs_ - A bit vector of allocatable registers. 64 BitVector allocatableRegs_; 65 66 /// reservedRegs_ - A bit vector of reserved registers. 67 BitVector reservedRegs_; 68 69 /// RegMaskSlots - Sorted list of instructions with register mask operands. 70 /// Always use the 'r' slot, RegMasks are normal clobbers, not early 71 /// clobbers. 72 SmallVector<SlotIndex, 8> RegMaskSlots; 73 74 /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a 75 /// pointer to the corresponding register mask. This pointer can be 76 /// recomputed as: 77 /// 78 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]); 79 /// unsigned OpNum = findRegMaskOperand(MI); 80 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask(); 81 /// 82 /// This is kept in a separate vector partly because some standard 83 /// libraries don't support lower_bound() with mixed objects, partly to 84 /// improve locality when searching in RegMaskSlots. 85 /// Also see the comment in LiveInterval::find(). 86 SmallVector<const uint32_t*, 8> RegMaskBits; 87 88 /// For each basic block number, keep (begin, size) pairs indexing into the 89 /// RegMaskSlots and RegMaskBits arrays. 90 /// Note that basic block numbers may not be layout contiguous, that's why 91 /// we can't just keep track of the first register mask in each basic 92 /// block. 93 SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks; 94 95 public: 96 static char ID; // Pass identification, replacement for typeid 97 LiveIntervals() : MachineFunctionPass(ID) { 98 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); 99 } 100 101 // Calculate the spill weight to assign to a single instruction. 102 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth); 103 104 typedef Reg2IntervalMap::iterator iterator; 105 typedef Reg2IntervalMap::const_iterator const_iterator; 106 const_iterator begin() const { return r2iMap_.begin(); } 107 const_iterator end() const { return r2iMap_.end(); } 108 iterator begin() { return r2iMap_.begin(); } 109 iterator end() { return r2iMap_.end(); } 110 unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); } 111 112 LiveInterval &getInterval(unsigned reg) { 113 Reg2IntervalMap::iterator I = r2iMap_.find(reg); 114 assert(I != r2iMap_.end() && "Interval does not exist for register"); 115 return *I->second; 116 } 117 118 const LiveInterval &getInterval(unsigned reg) const { 119 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg); 120 assert(I != r2iMap_.end() && "Interval does not exist for register"); 121 return *I->second; 122 } 123 124 bool hasInterval(unsigned reg) const { 125 return r2iMap_.count(reg); 126 } 127 128 /// isAllocatable - is the physical register reg allocatable in the current 129 /// function? 130 bool isAllocatable(unsigned reg) const { 131 return allocatableRegs_.test(reg); 132 } 133 134 /// isReserved - is the physical register reg reserved in the current 135 /// function 136 bool isReserved(unsigned reg) const { 137 return reservedRegs_.test(reg); 138 } 139 140 /// getScaledIntervalSize - get the size of an interval in "units," 141 /// where every function is composed of one thousand units. This 142 /// measure scales properly with empty index slots in the function. 143 double getScaledIntervalSize(LiveInterval& I) { 144 return (1000.0 * I.getSize()) / indexes_->getIndexesLength(); 145 } 146 147 /// getApproximateInstructionCount - computes an estimate of the number 148 /// of instructions in a given LiveInterval. 149 unsigned getApproximateInstructionCount(LiveInterval& I) { 150 double IntervalPercentage = getScaledIntervalSize(I) / 1000.0; 151 return (unsigned)(IntervalPercentage * indexes_->getFunctionSize()); 152 } 153 154 // Interval creation 155 LiveInterval &getOrCreateInterval(unsigned reg) { 156 Reg2IntervalMap::iterator I = r2iMap_.find(reg); 157 if (I == r2iMap_.end()) 158 I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first; 159 return *I->second; 160 } 161 162 /// dupInterval - Duplicate a live interval. The caller is responsible for 163 /// managing the allocated memory. 164 LiveInterval *dupInterval(LiveInterval *li); 165 166 /// addLiveRangeToEndOfBlock - Given a register and an instruction, 167 /// adds a live range from that instruction to the end of its MBB. 168 LiveRange addLiveRangeToEndOfBlock(unsigned reg, 169 MachineInstr* startInst); 170 171 /// shrinkToUses - After removing some uses of a register, shrink its live 172 /// range to just the remaining uses. This method does not compute reaching 173 /// defs for new uses, and it doesn't remove dead defs. 174 /// Dead PHIDef values are marked as unused. 175 /// New dead machine instructions are added to the dead vector. 176 /// Return true if the interval may have been separated into multiple 177 /// connected components. 178 bool shrinkToUses(LiveInterval *li, 179 SmallVectorImpl<MachineInstr*> *dead = 0); 180 181 // Interval removal 182 183 void removeInterval(unsigned Reg) { 184 DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg); 185 delete I->second; 186 r2iMap_.erase(I); 187 } 188 189 SlotIndexes *getSlotIndexes() const { 190 return indexes_; 191 } 192 193 /// isNotInMIMap - returns true if the specified machine instr has been 194 /// removed or was never entered in the map. 195 bool isNotInMIMap(const MachineInstr* Instr) const { 196 return !indexes_->hasIndex(Instr); 197 } 198 199 /// Returns the base index of the given instruction. 200 SlotIndex getInstructionIndex(const MachineInstr *instr) const { 201 return indexes_->getInstructionIndex(instr); 202 } 203 204 /// Returns the instruction associated with the given index. 205 MachineInstr* getInstructionFromIndex(SlotIndex index) const { 206 return indexes_->getInstructionFromIndex(index); 207 } 208 209 /// Return the first index in the given basic block. 210 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const { 211 return indexes_->getMBBStartIdx(mbb); 212 } 213 214 /// Return the last index in the given basic block. 215 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const { 216 return indexes_->getMBBEndIdx(mbb); 217 } 218 219 bool isLiveInToMBB(const LiveInterval &li, 220 const MachineBasicBlock *mbb) const { 221 return li.liveAt(getMBBStartIdx(mbb)); 222 } 223 224 bool isLiveOutOfMBB(const LiveInterval &li, 225 const MachineBasicBlock *mbb) const { 226 return li.liveAt(getMBBEndIdx(mbb).getPrevSlot()); 227 } 228 229 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const { 230 return indexes_->getMBBFromIndex(index); 231 } 232 233 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) { 234 return indexes_->insertMachineInstrInMaps(MI); 235 } 236 237 void RemoveMachineInstrFromMaps(MachineInstr *MI) { 238 indexes_->removeMachineInstrFromMaps(MI); 239 } 240 241 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) { 242 indexes_->replaceMachineInstrInMaps(MI, NewMI); 243 } 244 245 bool findLiveInMBBs(SlotIndex Start, SlotIndex End, 246 SmallVectorImpl<MachineBasicBlock*> &MBBs) const { 247 return indexes_->findLiveInMBBs(Start, End, MBBs); 248 } 249 250 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; } 251 252 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 253 virtual void releaseMemory(); 254 255 /// runOnMachineFunction - pass entry point 256 virtual bool runOnMachineFunction(MachineFunction&); 257 258 /// print - Implement the dump method. 259 virtual void print(raw_ostream &O, const Module* = 0) const; 260 261 /// isReMaterializable - Returns true if every definition of MI of every 262 /// val# of the specified interval is re-materializable. Also returns true 263 /// by reference if all of the defs are load instructions. 264 bool isReMaterializable(const LiveInterval &li, 265 const SmallVectorImpl<LiveInterval*> *SpillIs, 266 bool &isLoad); 267 268 /// intervalIsInOneMBB - If LI is confined to a single basic block, return 269 /// a pointer to that block. If LI is live in to or out of any block, 270 /// return NULL. 271 MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const; 272 273 /// addKillFlags - Add kill flags to any instruction that kills a virtual 274 /// register. 275 void addKillFlags(); 276 277 /// handleMove - call this method to notify LiveIntervals that 278 /// instruction 'mi' has been moved within a basic block. This will update 279 /// the live intervals for all operands of mi. Moves between basic blocks 280 /// are not supported. 281 void handleMove(MachineInstr* MI); 282 283 /// moveIntoBundle - Update intervals for operands of MI so that they 284 /// begin/end on the SlotIndex for BundleStart. 285 /// 286 /// Requires MI and BundleStart to have SlotIndexes, and assumes 287 /// existing liveness is accurate. BundleStart should be the first 288 /// instruction in the Bundle. 289 void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart); 290 291 // Register mask functions. 292 // 293 // Machine instructions may use a register mask operand to indicate that a 294 // large number of registers are clobbered by the instruction. This is 295 // typically used for calls. 296 // 297 // For compile time performance reasons, these clobbers are not recorded in 298 // the live intervals for individual physical registers. Instead, 299 // LiveIntervalAnalysis maintains a sorted list of instructions with 300 // register mask operands. 301 302 /// getRegMaskSlots - Returns a sorted array of slot indices of all 303 /// instructions with register mask operands. 304 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; } 305 306 /// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all 307 /// instructions with register mask operands in the basic block numbered 308 /// MBBNum. 309 ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const { 310 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum]; 311 return getRegMaskSlots().slice(P.first, P.second); 312 } 313 314 /// getRegMaskBits() - Returns an array of register mask pointers 315 /// corresponding to getRegMaskSlots(). 316 ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; } 317 318 /// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding 319 /// to getRegMaskSlotsInBlock(MBBNum). 320 ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const { 321 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum]; 322 return getRegMaskBits().slice(P.first, P.second); 323 } 324 325 /// checkRegMaskInterference - Test if LI is live across any register mask 326 /// instructions, and compute a bit mask of physical registers that are not 327 /// clobbered by any of them. 328 /// 329 /// Returns false if LI doesn't cross any register mask instructions. In 330 /// that case, the bit vector is not filled in. 331 bool checkRegMaskInterference(LiveInterval &LI, 332 BitVector &UsableRegs); 333 334 private: 335 /// computeIntervals - Compute live intervals. 336 void computeIntervals(); 337 338 /// handleRegisterDef - update intervals for a register def 339 /// (calls handlePhysicalRegisterDef and 340 /// handleVirtualRegisterDef) 341 void handleRegisterDef(MachineBasicBlock *MBB, 342 MachineBasicBlock::iterator MI, 343 SlotIndex MIIdx, 344 MachineOperand& MO, unsigned MOIdx); 345 346 /// isPartialRedef - Return true if the specified def at the specific index 347 /// is partially re-defining the specified live interval. A common case of 348 /// this is a definition of the sub-register. 349 bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO, 350 LiveInterval &interval); 351 352 /// handleVirtualRegisterDef - update intervals for a virtual 353 /// register def 354 void handleVirtualRegisterDef(MachineBasicBlock *MBB, 355 MachineBasicBlock::iterator MI, 356 SlotIndex MIIdx, MachineOperand& MO, 357 unsigned MOIdx, 358 LiveInterval& interval); 359 360 /// handlePhysicalRegisterDef - update intervals for a physical register 361 /// def. 362 void handlePhysicalRegisterDef(MachineBasicBlock* mbb, 363 MachineBasicBlock::iterator mi, 364 SlotIndex MIIdx, MachineOperand& MO, 365 LiveInterval &interval); 366 367 /// handleLiveInRegister - Create interval for a livein register. 368 void handleLiveInRegister(MachineBasicBlock* mbb, 369 SlotIndex MIIdx, 370 LiveInterval &interval); 371 372 /// getReMatImplicitUse - If the remat definition MI has one (for now, we 373 /// only allow one) virtual register operand, then its uses are implicitly 374 /// using the register. Returns the virtual register. 375 unsigned getReMatImplicitUse(const LiveInterval &li, 376 MachineInstr *MI) const; 377 378 /// isValNoAvailableAt - Return true if the val# of the specified interval 379 /// which reaches the given instruction also reaches the specified use 380 /// index. 381 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI, 382 SlotIndex UseIdx) const; 383 384 /// isReMaterializable - Returns true if the definition MI of the specified 385 /// val# of the specified interval is re-materializable. Also returns true 386 /// by reference if the def is a load. 387 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo, 388 MachineInstr *MI, 389 const SmallVectorImpl<LiveInterval*> *SpillIs, 390 bool &isLoad); 391 392 static LiveInterval* createInterval(unsigned Reg); 393 394 void printInstrs(raw_ostream &O) const; 395 void dumpInstrs() const; 396 397 class HMEditor; 398 }; 399} // End llvm namespace 400 401#endif 402