1//===- TargetItinerary.td - Target Itinierary Description --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent scheduling interfaces 11// which should be implemented by each target that uses instruction 12// itineraries for scheduling. Itineraries are details reservation 13// tables for each instruction class. They are most appropriate for 14// in-order machine with complicated scheduling or bundling constraints. 15// 16//===----------------------------------------------------------------------===// 17 18//===----------------------------------------------------------------------===// 19// Processor functional unit - These values represent the function units 20// available across all chip sets for the target. Eg., IntUnit, FPUnit, ... 21// These may be independent values for each chip set or may be shared across 22// all chip sets of the target. Each functional unit is treated as a resource 23// during scheduling and has an affect instruction order based on availability 24// during a time interval. 25// 26class FuncUnit; 27 28//===----------------------------------------------------------------------===// 29// Pipeline bypass / forwarding - These values specifies the symbolic names of 30// pipeline bypasses which can be used to forward results of instructions 31// that are forwarded to uses. 32class Bypass; 33def NoBypass : Bypass; 34 35class ReservationKind<bits<1> val> { 36 int Value = val; 37} 38 39def Required : ReservationKind<0>; 40def Reserved : ReservationKind<1>; 41 42//===----------------------------------------------------------------------===// 43// Instruction stage - These values represent a non-pipelined step in 44// the execution of an instruction. Cycles represents the number of 45// discrete time slots needed to complete the stage. Units represent 46// the choice of functional units that can be used to complete the 47// stage. Eg. IntUnit1, IntUnit2. NextCycles indicates how many 48// cycles should elapse from the start of this stage to the start of 49// the next stage in the itinerary. For example: 50// 51// A stage is specified in one of two ways: 52// 53// InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles 54// InstrStage<1, [FU_x, FU_y], 0> - TimeInc explicit 55// 56 57class InstrStage<int cycles, list<FuncUnit> units, 58 int timeinc = -1, 59 ReservationKind kind = Required> { 60 int Cycles = cycles; // length of stage in machine cycles 61 list<FuncUnit> Units = units; // choice of functional units 62 int TimeInc = timeinc; // cycles till start of next stage 63 int Kind = kind.Value; // kind of FU reservation 64} 65 66//===----------------------------------------------------------------------===// 67// Instruction itinerary - An itinerary represents a sequential series of steps 68// required to complete an instruction. Itineraries are represented as lists of 69// instruction stages. 70// 71 72//===----------------------------------------------------------------------===// 73// Instruction itinerary classes - These values represent 'named' instruction 74// itinerary. Using named itineraries simplifies managing groups of 75// instructions across chip sets. An instruction uses the same itinerary class 76// across all chip sets. Thus a new chip set can be added without modifying 77// instruction information. 78// 79class InstrItinClass; 80def NoItinerary : InstrItinClass; 81 82//===----------------------------------------------------------------------===// 83// Instruction itinerary data - These values provide a runtime map of an 84// instruction itinerary class (name) to its itinerary data. 85// 86// NumMicroOps represents the number of micro-operations that each instruction 87// in the class are decoded to. If the number is zero, then it means the 88// instruction can decode into variable number of micro-ops and it must be 89// determined dynamically. This directly relates to the itineraries 90// global IssueWidth property, which constrains the number of microops 91// that can issue per cycle. 92// 93// OperandCycles are optional "cycle counts". They specify the cycle after 94// instruction issue the values which correspond to specific operand indices 95// are defined or read. Bypasses are optional "pipeline forwarding pathes", if 96// a def by an instruction is available on a specific bypass and the use can 97// read from the same bypass, then the operand use latency is reduced by one. 98// 99// InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>, 100// InstrStage<1, [A9_AGU]>], 101// [3, 1], [A9_LdBypass]>, 102// InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], 103// [1, 1], [NoBypass, A9_LdBypass]>, 104// 105// In this example, the instruction of IIC_iLoadi reads its input on cycle 1 106// (after issue) and the result of the load is available on cycle 3. The result 107// is available via forwarding path A9_LdBypass. If it's used by the first 108// source operand of instructions of IIC_iMVNr class, then the operand latency 109// is reduced by 1. 110class InstrItinData<InstrItinClass Class, list<InstrStage> stages, 111 list<int> operandcycles = [], 112 list<Bypass> bypasses = [], int uops = 1> { 113 InstrItinClass TheClass = Class; 114 int NumMicroOps = uops; 115 list<InstrStage> Stages = stages; 116 list<int> OperandCycles = operandcycles; 117 list<Bypass> Bypasses = bypasses; 118} 119 120//===----------------------------------------------------------------------===// 121// Processor itineraries - These values represent the set of all itinerary 122// classes for a given chip set. 123// 124// Set property values to -1 to use the default. 125// See InstrItineraryProps for comments and defaults. 126class ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp, 127 list<InstrItinData> iid> { 128 list<FuncUnit> FU = fu; 129 list<Bypass> BP = bp; 130 list<InstrItinData> IID = iid; 131} 132 133// NoItineraries - A marker that can be used by processors without schedule 134// info. Subtargets using NoItineraries can bypass the scheduler's 135// expensive HazardRecognizer because no reservation table is needed. 136def NoItineraries : ProcessorItineraries<[], [], []>; 137