InstrEmitter.cpp revision 9d7019f586719a03f3519142ca2166166962e433
1bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// The LLVM Compiler Infrastructure 494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// This file is distributed under the University of Illinois Open Source 694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// License. See LICENSE.TXT for details. 794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman//===----------------------------------------------------------------------===// 994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 10bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// This implements the Emit routines for the SelectionDAG class, which creates 11bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// MachineInstrs based on the decisions of the SelectionDAG instruction 12bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman// selection. 1394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman// 1494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman//===----------------------------------------------------------------------===// 1594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman#define DEBUG_TYPE "instr-emitter" 17bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman#include "InstrEmitter.h" 18a8efe28a44996978faa42a387f1a6087a7b942c7Evan Cheng#include "SDNodeDbgValue.h" 1994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineConstantPool.h" 2094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineFunction.h" 2194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineInstrBuilder.h" 2294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/CodeGen/MachineRegisterInfo.h" 2394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetData.h" 2494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetMachine.h" 2594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetInstrInfo.h" 2694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Target/TargetLowering.h" 2794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/ADT/Statistic.h" 2894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Support/Debug.h" 29c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 3094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#include "llvm/Support/MathExtras.h" 3194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohmanusing namespace llvm; 3294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 33bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// CountResults - The results of target nodes have register or immediate 34bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// operands first, then an optional chain, and optional flag operands (which do 35bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// not go into the resulting MachineInstr). 36bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::CountResults(SDNode *Node) { 37bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned N = Node->getNumValues(); 38bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman while (N && Node->getValueType(N - 1) == MVT::Flag) 39bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; 40bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (N && Node->getValueType(N - 1) == MVT::Other) 41bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; // Skip over chain result. 42bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman return N; 43bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman} 44bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman 45bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// CountOperands - The inputs to target nodes have any actual inputs first, 46bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// followed by an optional chain operand, then an optional flag operand. 47bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// Compute the number of actual operands that will go into the resulting 48bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// MachineInstr. 49bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::CountOperands(SDNode *Node) { 50bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned N = Node->getNumOperands(); 51bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 52bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; 53bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman --N; // Ignore chain if it exists. 55bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman return N; 56bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman} 57bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman 5894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 5994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// implicit physical register output. 60bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter:: 615202312d2ed5078b0451838ee2661f4eb5ff2ef9Chris LattnerEmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 625202312d2ed5078b0451838ee2661f4eb5ff2ef9Chris Lattner unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 6394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 6494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 6594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Just use the input register directly! 6694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, ResNo); 6794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (IsClone) 6894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBaseMap.erase(Op); 6994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 7094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman isNew = isNew; // Silence compiler warning. 7194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 7294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return; 7394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 7494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 7594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the node is only used by a CopyToReg and the dest reg is a vreg, use 7694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the CopyToReg'd destination register instead of creating a new vreg. 7794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool MatchReg = true; 781cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng const TargetRegisterClass *UseRC = NULL; 79e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (!IsClone && !IsCloned) 80e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 81e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UI != E; ++UI) { 82e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDNode *User = *UI; 83e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng bool Match = true; 84e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (User->getOpcode() == ISD::CopyToReg && 85e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getNode() == Node && 86e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getResNo() == ResNo) { 87e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 88e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 89e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng VRBase = DestReg; 90e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 91e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } else if (DestReg != SrcReg) 92e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 93e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } else { 94e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 95e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDValue Op = User->getOperand(i); 96e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (Op.getNode() != Node || Op.getResNo() != ResNo) 97e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng continue; 98e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson EVT VT = Node->getValueType(Op.getResNo()); 99825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson if (VT == MVT::Other || VT == MVT::Flag) 100e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng continue; 101e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng Match = false; 102e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (User->isMachineOpcode()) { 103e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); 1042a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *RC = 0; 1052a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner if (i+II.getNumDefs() < II.getNumOperands()) 1062a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); 107e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (!UseRC) 108e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UseRC = RC; 109f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman else if (RC) { 110f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 111f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen // If multiple uses expect disjoint register classes, we emit 112f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen // copies in AddRegisterOperand. 113f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen if (ComRC) 114f7e8af925cee687b94ed4b84235cf0efed75a68bJakob Stoklund Olesen UseRC = ComRC; 115f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 116e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } 1171cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng } 11894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 119e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng MatchReg &= Match; 120e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (VRBase) 121e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng break; 12294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 12394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 124e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson EVT VT = Node->getValueType(ResNo); 12594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 1261cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT); 12794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 12894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Figure out the register class to create for the destreg. 12994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (VRBase) { 130bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DstRC = MRI->getRegClass(VRBase); 1311cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng } else if (UseRC) { 1321cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 1331cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng DstRC = UseRC; 13494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 1351cd332725f7e5fc93f08a8d3ed9806827e9b5509Evan Cheng DstRC = TLI->getRegClassFor(VT); 13694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 13794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 13894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If all uses are reading from the src physical register and copying the 13994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // register is either impossible or very expensive, then don't create a copy. 14094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (MatchReg && SrcRC->getCopyCost() < 0) { 14194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBase = SrcReg; 14294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 14394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the reg, emit the copy. 144bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(DstRC); 145bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg, 14634dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman DstRC, SrcRC, Node->getDebugLoc()); 147f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 148f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(Emitted && "Unable to issue a copy instruction!\n"); 1498c562e2d25d319f8bde7a1a60142203f316a2883Daniel Dunbar (void) Emitted; 15094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 15194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 15294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, ResNo); 15394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (IsClone) 15494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBaseMap.erase(Op); 15594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 15694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman isNew = isNew; // Silence compiler warning. 15794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 15894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 15994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// getDstOfCopyToRegUse - If the only use of the specified result number of 16194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// node is a CopyToReg, return its destination register. Return 0 otherwise. 162bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 163bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned ResNo) const { 16494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (!Node->hasOneUse()) 16594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return 0; 16694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 16794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDNode *User = *Node->use_begin(); 16894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (User->getOpcode() == ISD::CopyToReg && 16994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getNode() == Node && 17094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getResNo() == ResNo) { 17194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 17294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(Reg)) 17394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return Reg; 17494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 17594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return 0; 17694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 17794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 178bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 179e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng const TargetInstrDesc &II, 180e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng bool IsClone, bool IsCloned, 1815c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng DenseMap<SDValue, unsigned> &VRBaseMap) { 182518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 18394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 18494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 18594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (unsigned i = 0; i < II.getNumDefs(); ++i) { 18694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the specific node value is only used by a CopyToReg and the dest reg 187f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // is a vreg in the same register class, use the CopyToReg'd destination 188f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // register instead of creating a new vreg. 18994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 1902a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); 1918955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng if (II.OpInfo[i].isOptionalDef()) { 1928955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng // Optional def must be a physical register. 1938955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng unsigned NumResults = CountResults(Node); 1948955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 1958955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 1968955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 1978955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng } 198e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng 1998955e93b1ffa7645beea0b51e4b091b96063f613Evan Cheng if (!VRBase && !IsClone && !IsCloned) 200e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 201e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng UI != E; ++UI) { 202e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng SDNode *User = *UI; 203e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (User->getOpcode() == ISD::CopyToReg && 204e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getNode() == Node && 205e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng User->getOperand(2).getResNo() == i) { 206e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 207e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng if (TargetRegisterInfo::isVirtualRegister(Reg)) { 208bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 209f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (RegRC == RC) { 210f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman VRBase = Reg; 211f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman MI->addOperand(MachineOperand::CreateReg(Reg, true)); 212f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman break; 213f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 214e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng } 21594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 21694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 21794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 21894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the result registers for this node and add the result regs to 21994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the machine instruction. 22094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (VRBase == 0) { 22194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(RC && "Isn't a register operand!"); 222bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(RC); 22394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 22494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 22594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 22694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, i); 2275c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng if (IsClone) 2285c3c5a4d9c21e73f7a0e11d77a85997c9f34f2baEvan Cheng VRBaseMap.erase(Op); 22994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 23094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman isNew = isNew; // Silence compiler warning. 23194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 23294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 23394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 23494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 23594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// getVR - Return the virtual register corresponding to the specified result 23694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// of the specified node. 237bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanunsigned InstrEmitter::getVR(SDValue Op, 238bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 23994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Op.isMachineOpcode() && 240518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 24194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add an IMPLICIT_DEF instruction before every use. 24294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 24394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc 24494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // does not include operand register class info. 24594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (!VReg) { 24694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 247bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VReg = MRI->createVirtualRegister(RC); 24894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 249bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman BuildMI(MBB, Op.getDebugLoc(), 250518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 25194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return VReg; 25294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 25394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 25494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 25594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 25694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman return I->second; 25794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 25894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 25994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 260f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// AddRegisterOperand - Add the specified register as an operand to the 261f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// specified machine instr. Insert register copies if the register is 262f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// not in the required register class. 263f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanvoid 264bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 265bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned IIOpNum, 266bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetInstrDesc *II, 267bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DenseMap<SDValue, unsigned> &VRBaseMap, 268bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng bool IsDebug) { 269825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson assert(Op.getValueType() != MVT::Other && 270825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson Op.getValueType() != MVT::Flag && 271f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman "Chain and flag operands should occur at end of operand list!"); 272f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // Get/emit the operand. 273f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Op, VRBaseMap); 274f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 275f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 276f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const TargetInstrDesc &TID = MI->getDesc(); 277f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman bool isOptDef = IIOpNum < TID.getNumOperands() && 278f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman TID.OpInfo[IIOpNum].isOptionalDef(); 279f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 280f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // If the instruction requires a register in a different class, create 281f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // a new virtual register and copy the value into it. 282f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (II) { 283bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 2842a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner const TargetRegisterClass *DstRC = 0; 2852a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner if (IIOpNum < II->getNumOperands()) 2862a3868849438a0a0ad4f9a50f2b94eb1639b554eChris Lattner DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); 287f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && 288f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman "Don't have operand info for this instruction!"); 289f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { 290bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned NewVReg = MRI->createVirtualRegister(DstRC); 291bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 29234dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman DstRC, SrcRC, Op.getNode()->getDebugLoc()); 293f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(Emitted && "Unable to issue a copy instruction!\n"); 2948c562e2d25d319f8bde7a1a60142203f316a2883Daniel Dunbar (void) Emitted; 295f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman VReg = NewVReg; 296f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 297f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 298f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 29947bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman // If this value has only one use, that use is a kill. This is a 3009d7019f586719a03f3519142ca2166166962e433Dan Gohman // conservative approximation. InstrEmitter does trivial coalescing 3019d7019f586719a03f3519142ca2166166962e433Dan Gohman // with CopyFromReg nodes, so don't emit kill flags for them. 3029d7019f586719a03f3519142ca2166166962e433Dan Gohman // Tied operands are never killed, so we need to check that. And that 3039d7019f586719a03f3519142ca2166166962e433Dan Gohman // means we need to determine the index of the operand. 3049d7019f586719a03f3519142ca2166166962e433Dan Gohman bool isKill = Op.hasOneUse() && 3059d7019f586719a03f3519142ca2166166962e433Dan Gohman Op.getNode()->getOpcode() != ISD::CopyFromReg && 3069d7019f586719a03f3519142ca2166166962e433Dan Gohman !IsDebug; 3079d7019f586719a03f3519142ca2166166962e433Dan Gohman if (isKill) { 3089d7019f586719a03f3519142ca2166166962e433Dan Gohman unsigned Idx = MI->getNumOperands(); 3099d7019f586719a03f3519142ca2166166962e433Dan Gohman while (Idx > 0 && 3109d7019f586719a03f3519142ca2166166962e433Dan Gohman MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) 3119d7019f586719a03f3519142ca2166166962e433Dan Gohman --Idx; 3129d7019f586719a03f3519142ca2166166962e433Dan Gohman bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1; 3139d7019f586719a03f3519142ca2166166962e433Dan Gohman if (isTied) 3149d7019f586719a03f3519142ca2166166962e433Dan Gohman isKill = false; 3159d7019f586719a03f3519142ca2166166962e433Dan Gohman } 31647bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman 317bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 31847bd03b2779bc500fb0472518d0e278f080ee79aDan Gohman false/*isImp*/, isKill, 319bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng false/*isDead*/, false/*isUndef*/, 320bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng false/*isEarlyClobber*/, 321bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 0/*SubReg*/, IsDebug)); 322f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 323f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 32494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// AddOperand - Add the specified operand to the specified machine instr. II 32594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// specifies the instruction information for the node, and IIOpNum is the 32694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// operand number (in the II) that we are adding. IIOpNum and II are used for 32794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// assertions only. 328bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 329bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned IIOpNum, 330bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetInstrDesc *II, 331bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DenseMap<SDValue, unsigned> &VRBaseMap, 332bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng bool IsDebug) { 33394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Op.isMachineOpcode()) { 334bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); 33594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 336d842962e27b10b6831c2421fa257e3fd58a85b18Chris Lattner MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 33794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 3384fbd796a1251a27e6590765a0a34876f436a0af9Dan Gohman const ConstantFP *CFP = F->getConstantFPValue(); 33994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateFPImm(CFP)); 34094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 34186b49f8e2de796cb46c7c8b6a4c4900533fd53f4Dale Johannesen MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 34294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 3436ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 3446ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner TGA->getTargetFlags())); 345f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 346f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 34794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 34894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 34994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 3506ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 3516ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner JT->getTargetFlags())); 35294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 35394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman int Offset = CP->getOffset(); 35494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Align = CP->getAlignment(); 35594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const Type *Type = CP->getType(); 35694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // MachineConstantPool wants an explicit alignment. 35794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Align == 0) { 358bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Align = TM->getTargetData()->getPrefTypeAlignment(Type); 35994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (Align == 0) { 36094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Alignment of vector types. FIXME! 361bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Align = TM->getTargetData()->getTypeAllocSize(Type); 36294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 36394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 36494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 36594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Idx; 366bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineConstantPool *MCP = MF->getConstantPool(); 36794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (CP->isMachineConstantPoolEntry()) 368bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 36994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 370bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 3716ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 3726ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner CP->getTargetFlags())); 373056292fd738924f3f7703725d8f630983794b5a5Bill Wendling } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 37431e2c7b4c13c2f31774614b1124533628958d0cdDaniel Dunbar MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 3756ec66dba123a46a4006e0169d9edb8f5d9e1fbdcChris Lattner ES->getTargetFlags())); 3768c2b52552c90f39e4b2fed43e309e599e742b6acDan Gohman } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 37729cbade25aa094ca9a149a96a8614cf6f3247480Dan Gohman MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 37829cbade25aa094ca9a149a96a8614cf6f3247480Dan Gohman BA->getTargetFlags())); 37994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else { 380825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson assert(Op.getValueType() != MVT::Other && 381825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson Op.getValueType() != MVT::Flag && 38294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman "Chain and flag operands should occur at end of operand list!"); 383bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); 384f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 385f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 386f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 387f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 388f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// "SubIdx"'th sub-register class is the specified register class and whose 389f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// type matches the specified type. 390f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanstatic const TargetRegisterClass* 391f8c7394781f7cf27ac52ca087e289436d36844daDan GohmangetSuperRegisterRegClass(const TargetRegisterClass *TRC, 392e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson unsigned SubIdx, EVT VT) { 393f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // Pick the register class of the superegister for this type 394f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 395f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman E = TRC->superregclasses_end(); I != E; ++I) 396fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 397f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return *I; 398f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(false && "Couldn't find the register class"); 399f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return 0; 40094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 40194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 40294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// EmitSubregNode - Generate machine code for subreg nodes. 40394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// 404bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohmanvoid InstrEmitter::EmitSubregNode(SDNode *Node, 405bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap){ 40694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned VRBase = 0; 40794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Opc = Node->getMachineOpcode(); 40894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 40994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If the node is only used by a CopyToReg and the dest reg is a vreg, use 41094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // the CopyToReg'd destination register instead of creating a new vreg. 41194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 41294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman UI != E; ++UI) { 41394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDNode *User = *UI; 41494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (User->getOpcode() == ISD::CopyToReg && 41594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman User->getOperand(2).getNode() == Node) { 41694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 41794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 41894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman VRBase = DestReg; 41994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 42094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 42194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 42294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 42394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 424518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (Opc == TargetOpcode::EXTRACT_SUBREG) { 425f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 42694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 42794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the extract_subreg machine instruction. 428bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 429518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner TII->get(TargetOpcode::EXTRACT_SUBREG)); 43094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 43194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Figure out the register class to create for the destreg. 432f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 433bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 434fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 435fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 43694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 4375ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // Figure out the register class to create for the destreg. 4385ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // Note that if we're going to directly use an existing register, 4395ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // it must be precisely the required class, and not a subclass 4405ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // thereof. 441bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 44294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the reg 44394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(SRC && "Couldn't find source register class"); 444bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(SRC); 44594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 4465ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 44794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add def, source, and subreg index 44894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 44994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); 45094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateImm(SubIdx)); 451bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 452518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner } else if (Opc == TargetOpcode::INSERT_SUBREG || 453518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner Opc == TargetOpcode::SUBREG_TO_REG) { 45494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N0 = Node->getOperand(0); 45594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N1 = Node->getOperand(1); 45694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue N2 = Node->getOperand(2); 457f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned SubReg = getVR(N1, VRBaseMap); 458f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 459bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 4605ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman const TargetRegisterClass *SRC = 461ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0)); 4625ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 46394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Figure out the register class to create for the destreg. 4645ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // Note that if we're going to directly use an existing register, 4655ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // it must be precisely the required class, and not a subclass 4665ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // thereof. 467bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 4685ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman // Create the reg 4695ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman assert(SRC && "Couldn't find source register class"); 470bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman VRBase = MRI->createVirtualRegister(SRC); 47194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 4725ec3b427c850d8c61aaa29e3421019bdff9b77f1Dan Gohman 47394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the insert_subreg or subreg_to_reg machine instruction. 474bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 47594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 47694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 47794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // If creating a subreg_to_reg, then the first input operand 47894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // is an implicit value immediate, otherwise it's a register 479518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (Opc == TargetOpcode::SUBREG_TO_REG) { 48094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 481f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 48294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else 48394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman AddOperand(MI, N0, 0, 0, VRBaseMap); 48494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add the subregster being inserted 48594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman AddOperand(MI, N1, 0, 0, VRBaseMap); 48694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateImm(SubIdx)); 487bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 48894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } else 489c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 49094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 49194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue Op(Node, 0); 49294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 49394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman isNew = isNew; // Silence compiler warning. 49494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman assert(isNew && "Node emitted out of order - early"); 49594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 49694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 49788c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 49888c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman/// COPY_TO_REGCLASS is just a normal copy, except that the destination 499f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// register is constrained to be in a particular register class. 500f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman/// 501f8c7394781f7cf27ac52ca087e289436d36844daDan Gohmanvoid 502bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 503bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 504f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 505bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 506f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 507f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 508f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 509f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 510f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman // Create the new VReg in the destination class and emit a copy. 511bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman unsigned NewVReg = MRI->createVirtualRegister(DstRC); 512bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 51334dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman DstRC, SrcRC, Node->getDebugLoc()); 514f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(Emitted && 51588c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n"); 5168c562e2d25d319f8bde7a1a60142203f316a2883Daniel Dunbar (void) Emitted; 517f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 518f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman SDValue Op(Node, 0); 519f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 520f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman isNew = isNew; // Silence compiler warning. 521f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(isNew && "Node emitted out of order - early"); 522f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman} 523f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 524ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 525ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng/// 526ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Chengvoid InstrEmitter::EmitRegSequence(SDNode *Node, 527ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng DenseMap<SDValue, unsigned> &VRBaseMap) { 528ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0)); 529ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned NewVReg = MRI->createVirtualRegister(RC); 530ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 531ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng TII->get(TargetOpcode::REG_SEQUENCE), NewVReg); 532ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned NumOps = Node->getNumOperands(); 533ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng assert((NumOps & 1) == 0 && 534ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng "REG_SEQUENCE must have an even number of operands!"); 535ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 536ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng for (unsigned i = 0; i != NumOps; ++i) { 537ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng SDValue Op = Node->getOperand(i); 538ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng#ifndef NDEBUG 539ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng if (i & 1) { 540ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 541ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 54260ffa9467b0c7df2f76e2b2de7af17b776805e28Evan Cheng const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 54360ffa9467b0c7df2f76e2b2de7af17b776805e28Evan Cheng const TargetRegisterClass *SRC = 54460ffa9467b0c7df2f76e2b2de7af17b776805e28Evan Cheng getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0)); 54560ffa9467b0c7df2f76e2b2de7af17b776805e28Evan Cheng assert(SRC == RC && "Invalid subregister index in REG_SEQUENCE"); 546ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 547ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng#endif 548ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng AddOperand(MI, Op, i+1, &II, VRBaseMap); 549ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 550ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 551ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng MBB->insert(InsertPos, MI); 552ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng SDValue Op(Node, 0); 553ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 554ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng isNew = isNew; // Silence compiler warning. 555ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng assert(isNew && "Node emitted out of order - early"); 556ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng} 557ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 558bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng/// EmitDbgValue - Generate machine instruction for a dbg_value node. 559bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng/// 560891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan GohmanMachineInstr * 561891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan GohmanInstrEmitter::EmitDbgValue(SDDbgValue *SD, 562891ff8fbd61a06ef8ea57461fa377ebbb663ed09Dan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 563bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng uint64_t Offset = SD->getOffset(); 564bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MDNode* MDPtr = SD->getMDPtr(); 565bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng DebugLoc DL = SD->getDebugLoc(); 566bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 567f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen if (SD->getKind() == SDDbgValue::FRAMEIX) { 568f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // Stack address; this needs to be lowered in target-dependent fashion. 569f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // EmitTargetCodeForFrameDebugValue is responsible for allocation. 570f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen unsigned FrameIx = SD->getFrameIx(); 571962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 572f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen } 573f822e733aff93b34e6cd85b2f92d86e71fe67f87Dale Johannesen // Otherwise, we're going to create an instruction here. 57406a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 575bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 576bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng if (SD->getKind() == SDDbgValue::SDNODE) { 577c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen SDNode *Node = SD->getSDNode(); 578c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen SDValue Op = SDValue(Node, SD->getResNo()); 579c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // It's possible we replaced this SDNode with other(s) and therefore 580c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // didn't generate code for it. It's better to catch these cases where 581c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // they happen and transfer the debug info, but trying to guarantee that 582c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // in all cases would be very fragile; this is a safeguard for any 583c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen // that were missed. 584c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 585c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen if (I==VRBaseMap.end()) 586c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen MIB.addReg(0U); // undef 587c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen else 588c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 589c4d7b14a92a9b34449eccdccce1263c4b68ad474Dale Johannesen true /*IsDebug*/); 590bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng } else if (SD->getKind() == SDDbgValue::CONST) { 59146510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Value *V = SD->getConst(); 59246510a73e977273ec67747eb34cbdb43f815e451Dan Gohman if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 5934ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman // FIXME: SDDbgValues aren't updated with legalization, so it's possible 5944ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman // to have i128 values in them at this point. As a crude workaround, just 5954ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman // drop the debug info if this happens. 5964ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman if (!CI->getValue().isSignedIntN(64)) 5974ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman MIB.addReg(0U); 5984ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman else 5994ce86f459c92258f887fd8fd884fa55066b3a0cdDan Gohman MIB.addImm(CI->getSExtValue()); 60046510a73e977273ec67747eb34cbdb43f815e451Dan Gohman } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 601bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addFPImm(CF); 602bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen } else { 603bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen // Could be an Undef. In any case insert an Undef so we can see what we 604bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen // dropped. 605bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addReg(0U); 606bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33Dale Johannesen } 60706a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen } else { 60806a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen // Insert an Undef so we can see what we dropped. 609bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addReg(0U); 61006a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen } 611bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng 612bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng MIB.addImm(Offset).addMetadata(MDPtr); 613bfcb3051899b7141a946d769fcf6e8a8453bc530Evan Cheng return &*MIB; 61406a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen} 61506a26637daff1bb785ef0945d1ba05f6ccdfab86Dale Johannesen 6163d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// EmitMachineNode - Generate machine code for a target-specific node and 6173d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// needed dependencies. 61894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman/// 6193d7d07ef038696cefcaf3ce5335072964199a78dChris Lattnervoid InstrEmitter:: 6203d7d07ef038696cefcaf3ce5335072964199a78dChris LattnerEmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 621af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman DenseMap<SDValue, unsigned> &VRBaseMap) { 6223d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned Opc = Node->getMachineOpcode(); 6233d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 6243d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Handle subreg insert/extract specially 6253d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::EXTRACT_SUBREG || 6263d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner Opc == TargetOpcode::INSERT_SUBREG || 6273d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner Opc == TargetOpcode::SUBREG_TO_REG) { 6283d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner EmitSubregNode(Node, VRBaseMap); 6293d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6303d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 63194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 6323d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Handle COPY_TO_REGCLASS specially. 6333d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 6343d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner EmitCopyToRegClassNode(Node, VRBaseMap); 6353d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6363d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 637f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 638ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng // Handle REG_SEQUENCE specially. 639ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng if (Opc == TargetOpcode::REG_SEQUENCE) { 640ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng EmitRegSequence(Node, VRBaseMap); 641ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng return; 642ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng } 643ba609c88a5a0eb717772c89bda89157c85fdf95eEvan Cheng 6443d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Opc == TargetOpcode::IMPLICIT_DEF) 6453d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // We want a unique VR for each IMPLICIT_DEF use. 6463d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner return; 6473d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 6483d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner const TargetInstrDesc &II = TII->get(Opc); 6493d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumResults = CountResults(Node); 6503d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NodeOperands = CountOperands(Node); 65147cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 65294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#ifndef NDEBUG 6533d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumMIOperands = NodeOperands + NumResults; 65447cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner if (II.isVariadic()) 65547cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner assert(NumMIOperands >= II.getNumOperands() && 65647cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner "Too few operands for a variadic node!"); 65747cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner else 65847cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner assert(NumMIOperands >= II.getNumOperands() && 65947cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && 66047cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner "#operands for dag node doesn't match .td file!"); 66194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#endif 66294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 6633d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Create the new machine instruction. 6643d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 6653d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 6663d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Add result register values for things that are defined by this 6673d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // instruction. 6683d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (NumResults) 6693d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 6703d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 6713d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Emit all of the actual operands of this instruction, adding them to the 6723d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // instruction as appropriate. 6733d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner bool HasOptPRefs = II.getNumDefs() > NumResults; 6743d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner assert((!HasOptPRefs || !HasPhysRegOuts) && 6753d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner "Unable to cope with optional defs and phys regs defs!"); 6763d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 6773d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner for (unsigned i = NumSkip; i != NodeOperands; ++i) 6783d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 6793d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner VRBaseMap); 6803d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 6813d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Transfer all of the memory reference descriptions of this instruction. 6823d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 6833d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner cast<MachineSDNode>(Node)->memoperands_end()); 6843d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner 6853d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (II.usesCustomInsertionHook()) { 6863d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Insert this instruction into the basic block using a target 6873d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // specific inserter which may returns a new basic block. 688af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman MBB = TLI->EmitInstrWithCustomInserter(MI, MBB); 6893d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner InsertPos = MBB->end(); 6907bf198fd607b356e767e0577cac81c3491c4bc90Chris Lattner return; 6913d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner } 6927bf198fd607b356e767e0577cac81c3491c4bc90Chris Lattner 6937bf198fd607b356e767e0577cac81c3491c4bc90Chris Lattner MBB->insert(InsertPos, MI); 69494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 6953d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Additional results must be an physical register def. 6963d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (HasPhysRegOuts) { 6973d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 6983d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 6993d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner if (Node->hasAnyUseOfValue(i)) 7003d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 7013d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // If there are no uses, mark the register as dead now, so that 7023d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // MachineLICM/Sink can see that it's dead. Don't do this if the 7033d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // node has a Flag value, for the benefit of targets still using 7043d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner // Flag for values in physregs. 7053d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 7063d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner MI->addRegisterDead(Reg, TRI); 70794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 70894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 70947cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner 71047cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner // If the instruction has implicit defs and the node doesn't, mark the 71147cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner // implicit def as dead. If the node has any flag outputs, we don't do this 71247cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner // because we don't know what implicit defs are being used by flagged nodes. 713d05e8055362be52fc33dcc685ba2ae5c722506b5Evan Cheng if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 71447cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner if (const unsigned *IDList = II.getImplicitDefs()) { 71547cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); 71647cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner i != e; ++i) 71747cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); 71847cdf4abff20eb9d7d05406cc1a9be2890ed39bbChris Lattner } 7193d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner} 72094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 7213d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// EmitSpecialNode - Generate machine code for a target-independent node and 7223d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner/// needed dependencies. 7233d7d07ef038696cefcaf3ce5335072964199a78dChris Lattnervoid InstrEmitter:: 7243d7d07ef038696cefcaf3ce5335072964199a78dChris LattnerEmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 7253d7d07ef038696cefcaf3ce5335072964199a78dChris Lattner DenseMap<SDValue, unsigned> &VRBaseMap) { 72694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman switch (Node->getOpcode()) { 72794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman default: 72894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#ifndef NDEBUG 729bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman Node->dump(); 73094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman#endif 731c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("This target-independent node should have been selected!"); 73294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 73394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::EntryToken: 734c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("EntryToken should have been excluded from the schedule!"); 73594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 73637b7387da90ffd42d28ad0f08fca00b684294b2cEvan Cheng case ISD::MERGE_VALUES: 73794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::TokenFactor: // fall thru 73894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 73994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::CopyToReg: { 74094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned SrcReg; 74194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SDValue SrcVal = Node->getOperand(2); 74294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 74394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SrcReg = R->getReg(); 74494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 74594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SrcReg = getVR(SrcVal, VRBaseMap); 74694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 74794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 74894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 74994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 75094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 75194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0; 75294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Get the register classes of the src/dst. 75394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(SrcReg)) 754bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman SrcTRC = MRI->getRegClass(SrcReg); 75594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 75694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType()); 75794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 75894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman if (TargetRegisterInfo::isVirtualRegister(DestReg)) 759bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman DstTRC = MRI->getRegClass(DestReg); 76094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman else 76194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, 76294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman Node->getOperand(1).getValueType()); 763f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 764bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg, 76534dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman DstTRC, SrcTRC, Node->getDebugLoc()); 766f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman assert(Emitted && "Unable to issue a copy instruction!\n"); 7678c562e2d25d319f8bde7a1a60142203f316a2883Daniel Dunbar (void) Emitted; 76894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 76994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 77094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::CopyFromReg: { 77194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 772e57187cbe321a286f6a7f409a7badd1ae4e4642cEvan Cheng EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 77394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 77494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 7757561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner case ISD::EH_LABEL: { 7767561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 7777561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 7787561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner TII->get(TargetOpcode::EH_LABEL)).addSym(S); 7797561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner break; 7807561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner } 7817561d480953e0a2faa4af9be0a00b1180097c4bdChris Lattner 78294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman case ISD::INLINEASM: { 78394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned NumOps = Node->getNumOperands(); 784825b72b0571821bf2d378749f69d6c4cfb52d2f9Owen Anderson if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) 78594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman --NumOps; // Ignore the flag operand. 78694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 78794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Create the inline asm machine instruction. 788bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 789518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner TII->get(TargetOpcode::INLINEASM)); 79094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 79194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add the asm string as an external symbol operand. 792decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 793decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 79494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateES(AsmStr)); 79594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 79694b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // Add all of the operand registers to the instruction. 797decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 798f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman unsigned Flags = 799f5aeb1a8e4cf272c7348376d185ef8d8267653e0Dan Gohman cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 800697cbbfb00c318f98d6eb51945f077e2bfe8781eEvan Cheng unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 80194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 80294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateImm(Flags)); 80394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman ++i; // Skip the ID value. 80494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 805decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner switch (InlineAsm::getKind(Flags)) { 806c23197a26f34f559ea9797de51e187087c039c42Torok Edwin default: llvm_unreachable("Bad flags!"); 807decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegDef: 80894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (; NumVals; --NumVals, ++i) { 80994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 81094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman MI->addOperand(MachineOperand::CreateReg(Reg, true)); 81194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 81294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 813decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegDefEarlyClobber: 814913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen for (; NumVals; --NumVals, ++i) { 815913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 816913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false, 8174784f1fc73abf6005b7b7262d395af71b57b1255Evan Cheng false, false, true)); 818913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen } 819913d3dfac43f29921467f33aa743f28ee1bfc5d1Dale Johannesen break; 820decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_RegUse: // Use of register. 821decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_Imm: // Immediate. 822decc2671516e6c52ee2f29f7746f8d02753845eaChris Lattner case InlineAsm::Kind_Mem: // Addressing mode. 82394b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // The addressing mode has been selected, just add all of the 82494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman // operands to the machine instruction. 82594b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman for (; NumVals; --NumVals, ++i) 82686b49f8e2de796cb46c7c8b6a4c4900533fd53f4Dale Johannesen AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap); 82794b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 82894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 82994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 830cf9a415182aca6a432105a2a12168e1049de180aChris Lattner 831cf9a415182aca6a432105a2a12168e1049de180aChris Lattner // Get the mdnode from the asm if it exists and add it to the instruction. 832cf9a415182aca6a432105a2a12168e1049de180aChris Lattner SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 833cf9a415182aca6a432105a2a12168e1049de180aChris Lattner const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 834cc7354e9936595fd2654e1690310fcdc5ef10971Bob Wilson if (MD) 835cc7354e9936595fd2654e1690310fcdc5ef10971Bob Wilson MI->addOperand(MachineOperand::CreateMetadata(MD)); 836cf9a415182aca6a432105a2a12168e1049de180aChris Lattner 837bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB->insert(InsertPos, MI); 83894b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman break; 83994b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 84094b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman } 84194b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 84294b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman 843bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 844bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman/// at the given position in the given block. 845bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan GohmanInstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 846bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MachineBasicBlock::iterator insertpos) 847bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman : MF(mbb->getParent()), 848bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MRI(&MF->getRegInfo()), 849bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TM(&MF->getTarget()), 850bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TII(TM->getInstrInfo()), 851bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TRI(TM->getRegisterInfo()), 852bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman TLI(TM->getTargetLowering()), 853bcea859fc1dd1af9ac66ec93ea04ce9a19c8451cDan Gohman MBB(mbb), InsertPos(insertpos) { 85494b8d7ea63c5b533c299226677a0973a39f98e91Dan Gohman} 855