ARMBaseInstrInfo.h revision 57148c166ab232191098492633c924fad9c44ef3
131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#ifndef ARMBASEINSTRUCTIONINFO_H 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#define ARMBASEINSTRUCTIONINFO_H 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 17334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 1848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "llvm/ADT/DenseMap.h" 1948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "llvm/ADT/SmallSet.h" 20a1514e24cc24b050f53a12650e047799358833a1Chandler Carruth#include "llvm/CodeGen/MachineInstrBuilder.h" 21a1514e24cc24b050f53a12650e047799358833a1Chandler Carruth#include "llvm/Target/TargetInstrInfo.h" 22334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 234db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#define GET_INSTRINFO_HEADER 244db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#include "ARMGenInstrInfo.inc" 254db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng 26334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinnamespace llvm { 274dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner class ARMSubtarget; 284dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner class ARMBaseRegisterInfo; 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 304db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Chengclass ARMBaseInstrInfo : public ARMGenInstrInfo { 314dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner const ARMSubtarget &Subtarget; 3248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 33334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinprotected: 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can be only subclassed. 35f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov explicit ARMBaseInstrInfo(const ARMSubtarget &STI); 3648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinpublic: 38c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach // Return whether the target has an explicit NOP encoding. 39c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach bool hasNOP() const; 40c01810eeb7227010f73cb39e3c4fa0197a3c4ef0Jim Grosbach 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Return the non-pre/post incrementing version of 'Opc'. Return 0 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // if there is not such an opcode. 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; 44334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const; 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 4957148c166ab232191098492633c924fad9c44ef3Bill Wendling virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0; 50f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov const ARMSubtarget &getSubtarget() const { return Subtarget; } 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 5248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng ScheduleHazardRecognizer * 532da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick CreateTargetHazardRecognizer(const TargetMachine *TM, 542da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const; 552da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 562da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick ScheduleHazardRecognizer * 572da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 582da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const; 5948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Branch analysis. 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 642062875a7d8f7dd94a20d9e3a298e9e216efb4b5Chris Lattner bool AllowModify = false) const; 65334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *FBB, 683bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 693bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const; 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Predication support. 75ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng bool isPredicated(const MachineInstr *MI) const; 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin : ARMCC::AL; 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool PredicateInstruction(MachineInstr *MI, 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const; 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const; 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual bool DefinesPredicate(MachineInstr *MI, 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const; 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 94ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng virtual bool isPredicable(MachineInstr *MI) const; 95ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin /// GetInstSize - Returns the size of the specified MachineInstr. 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin /// 98334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const; 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 101334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const; 102334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 103334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const; 10436ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 10536ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const; 10636ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 10736ee0e640554b8cc6ad1658fc3049e05d9967160Jakob Stoklund Olesen int &FrameIndex) const; 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 109ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen virtual void copyPhysReg(MachineBasicBlock &MBB, 110ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 111ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 112ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const; 1135732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng 114334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 115334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator MBBI, 116334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FrameIndex, 117746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 118746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const; 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator MBBI, 122334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FrameIndex, 123746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 124746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const; 125334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 126142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 127142bd1a54e93f3f66d420717ecba53539a556035Jakob Stoklund Olesen 12862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 1298601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, 13062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng uint64_t Offset, 13162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 13262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const; 13362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 134fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 135fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator MI, 136fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 137d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 1389edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const; 139fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 14030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const; 14130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 142c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen MachineInstr *commuteInstruction(MachineInstr*, bool=false) const; 143c5041cac7d3aeaa7350abadf2a7ada92e8da27dcJakob Stoklund Olesen 1444cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 1454cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover unsigned SubIdx, unsigned State, 1464cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover const TargetRegisterInfo *TRI) const; 1474cc1407b84dc6dbbc0d62b1d1b8db7c0ddec86ccTim Northover 148506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng virtual bool produceSameValue(const MachineInstr *MI0, 1499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 1509fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const; 15186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 1524b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 1534b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// determine if two loads are loading from the same base address. It should 1544b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// only return true if the base pointers are the same and the only 1554b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// differences between the two addresses is the offset. It also returns the 1564b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// offsets by reference. 1574b722108e2cf8e77157e0879a23789cd44829933Bill Wendling virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 1584b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, int64_t &Offset2)const; 1594b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 1604b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 161f921c0fe3418f96bd1e37beb582a368d3ac24295Jim Grosbach /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 162f921c0fe3418f96bd1e37beb582a368d3ac24295Jim Grosbach /// should be scheduled togther. On some targets if two loads are loading from 1634b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// addresses in the same cache line, it's better if they are scheduled 1644b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// together. This function takes two integers that represent the load offsets 1654b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// from the common base address. It returns true if it decides it's desirable 1664b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// to schedule the two loads together. "NumLoads" is the number of loads that 1674b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// have already been scheduled after Load1. 1684b722108e2cf8e77157e0879a23789cd44829933Bill Wendling virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 1694b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 1704b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const; 1714b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 17286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual bool isSchedulingBoundary(const MachineInstr *MI, 17386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 17486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const; 17513151432edace19ee867a93b5c14573df4f75d24Evan Cheng 17613151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, 1775876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich unsigned NumCycles, unsigned ExtraPredCycles, 178f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const; 17913151432edace19ee867a93b5c14573df4f75d24Evan Cheng 1808239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 1818239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumT, unsigned ExtraT, 1828239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 1838239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumF, unsigned ExtraF, 184f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const; 18513151432edace19ee867a93b5c14573df4f75d24Evan Cheng 18613151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 1875876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich unsigned NumCycles, 188f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability 189154418cdd82b3d8dcf23efd65f5647833e43bc45Bob Wilson &Probability) const { 1905876db7a66fcc4ec4444a9f3e387c1cdc8baf9e5Cameron Zwarich return NumCycles == 1; 19113151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 192e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 193eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 194eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson MachineBasicBlock &FMBB) const; 195eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson 196de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// analyzeCompare - For a comparison instruction, return the source registers 197de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// in SrcReg and SrcReg2 if having two register operands, and the value it 198de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// compares against in CmpValue. Return true if the comparison instruction 199de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// can be analyzed. 200de7266c611b37ec050efb53b73166081a98cea13Manman Ren virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, 201de7266c611b37ec050efb53b73166081a98cea13Manman Ren unsigned &SrcReg2, int &CmpMask, 202de7266c611b37ec050efb53b73166081a98cea13Manman Ren int &CmpValue) const; 203de7266c611b37ec050efb53b73166081a98cea13Manman Ren 204de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// optimizeCompareInstr - Convert the instruction to set the zero flag so 205de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// that we can remove a "comparison with zero"; Remove a redundant CMP 206de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// instruction if the flags can be updated in the same way by an earlier 207de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// instruction such as SUB. 208de7266c611b37ec050efb53b73166081a98cea13Manman Ren virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, 209de7266c611b37ec050efb53b73166081a98cea13Manman Ren unsigned SrcReg2, int CmpMask, int CmpValue, 210eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng const MachineRegisterInfo *MRI) const; 2115f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 212053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen virtual bool analyzeSelect(const MachineInstr *MI, 213053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen SmallVectorImpl<MachineOperand> &Cond, 214053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen unsigned &TrueOp, unsigned &FalseOp, 215053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen bool &Optimizable) const; 216053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 217053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen virtual MachineInstr *optimizeSelect(MachineInstr *MI, bool) const; 218053b5b0b3c34d4763511b6dcd8e0150f8e9dd083Jakob Stoklund Olesen 219c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// FoldImmediate - 'Reg' is known to be defined by a move immediate 220c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// instruction, try to fold the immediate into the use instruction. 221c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 222c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg, MachineRegisterInfo *MRI) const; 223c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 2248239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 2258239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const; 226a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 227a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng virtual 228a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int getOperandLatency(const InstrItineraryData *ItinData, 229a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 230a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const; 231a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng virtual 232a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int getOperandLatency(const InstrItineraryData *ItinData, 233a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 234a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const; 23513fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 23613fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen /// VFP/NEON execution domains. 23713fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen std::pair<uint16_t, uint16_t> 23813fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen getExecutionDomain(const MachineInstr *MI) const; 23913fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen void setExecutionDomain(MachineInstr *MI, unsigned Domain) const; 24013fd601e0f1c6d8558c4c2b027dacd148f19e6afJakob Stoklund Olesen 241eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned, 242eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const TargetRegisterInfo*) const; 243eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned, 244eb1641d54a7eda7717304bc4d55d059208d8ebedBob Wilson const TargetRegisterInfo *TRI) const; 2459eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick /// Get the number of addresses by LDM or VLDM or zero for unknown. 2469eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick unsigned getNumLDMAddresses(const MachineInstr *MI) const; 2479eed53379f19f836769a0c4a14042eeb1b587769Andrew Trick 248a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengprivate: 249ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng unsigned getInstBundleLength(const MachineInstr *MI) const; 250ddfd1377d2e4154d44dc3ad217735adc15af2e3fEvan Cheng 251344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getVLDMDefCycle(const InstrItineraryData *ItinData, 252e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 253344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 254344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const; 255344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getLDMDefCycle(const InstrItineraryData *ItinData, 256e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 257344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 258344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const; 259344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getVSTMUseCycle(const InstrItineraryData *ItinData, 260e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 261344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 262344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const; 263344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getSTMUseCycle(const InstrItineraryData *ItinData, 264e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 265344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 266344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const; 267a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int getOperandLatency(const InstrItineraryData *ItinData, 268e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &DefMCID, 269a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 270e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &UseMCID, 271a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const; 2722312842de0c641107dd04d7e056d02491cc781caEvan Cheng 273b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick unsigned getInstrLatency(const InstrItineraryData *ItinData, 274b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick const MachineInstr *MI, 275b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick unsigned *PredCost = 0) const; 2768239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 2778239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng int getInstrLatency(const InstrItineraryData *ItinData, 2788239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const; 2798239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 2802312842de0c641107dd04d7e056d02491cc781caEvan Cheng bool hasHighOperandLatency(const InstrItineraryData *ItinData, 2812312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 2822312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 2832312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const; 284c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng bool hasLowDefLatency(const InstrItineraryData *ItinData, 285c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const; 28648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 2873be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick /// verifyInstruction - Perform target specific instruction verification. 2883be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const; 2893be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 29048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengprivate: 29148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// Modeling special VFP / NEON fp MLA / MLS hazards. 29248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 29348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal 29448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// MLx table. 29548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned> MLxEntryMap; 29648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 29748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause 29848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// stalls when scheduled together with fp MLA / MLS opcodes. 29948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng SmallSet<unsigned, 16> MLxHazardOpcodes; 30048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 30148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengpublic: 30248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS 30348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// instruction. 30448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool isFpMLxInstruction(unsigned Opcode) const { 30548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return MLxEntryMap.count(Opcode); 30648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 30748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 30848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// isFpMLxInstruction - This version also returns the multiply opcode and the 30948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// addition / subtraction opcode to expand to. Return true for 'HasLane' for 31048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// the MLX instructions with an extra lane operand. 31148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 31248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, bool &NegAcc, 31348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &HasLane) const; 31448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 31548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// canCauseFpMLxStall - Return true if an instruction of the specified opcode 31648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// will cause stalls when scheduled after (within 4-cycle window) a fp 31748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// MLA / MLS instruction. 31848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool canCauseFpMLxStall(unsigned Opcode) const { 31948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return MLxHazardOpcodes.count(Opcode); 32048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 32108da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer 32208da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer /// Returns true if the instruction has a shift by immediate that can be 32308da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer /// executed in one cycle less. 32408da4865576056f997a9c8013240d716018f7edfArnold Schwaighofer bool isSwiftFastImmShift(const MachineInstr *MI) const; 3256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng}; 3265ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 3276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 3286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengconst MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 3296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 3306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 3315ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 3326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 3336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengconst MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 3346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return MIB.addReg(0); 3356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 33683e0e36be8390fee1235783731f6c64aa604b7eeEvan Cheng 3376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 338e8af1f9afe5e70e1d4ec4d00a6870428dba88692Evan Chengconst MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, 339e8af1f9afe5e70e1d4ec4d00a6870428dba88692Evan Cheng bool isDead = false) { 340e8af1f9afe5e70e1d4ec4d00a6870428dba88692Evan Cheng return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 3416495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 3426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 3436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 344bc9b754091ea281e769e487f396b40f6675b9edbEvan Chengconst MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { 345bc9b754091ea281e769e487f396b40f6675b9edbEvan Cheng return MIB.addReg(0); 346bc9b754091ea281e769e487f396b40f6675b9edbEvan Cheng} 347bc9b754091ea281e769e487f396b40f6675b9edbEvan Cheng 348bc9b754091ea281e769e487f396b40f6675b9edbEvan Chengstatic inline 3496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengbool isUncondBranchOpcode(int Opc) { 3506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 351334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 352334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 3536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 3546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengbool isCondBranchOpcode(int Opc) { 3556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; 3566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 3576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 3586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 3596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengbool isJumpTableBranchOpcode(int Opc) { 3606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || 3616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; 3626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 3636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 3648d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilsonstatic inline 3658d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilsonbool isIndirectBranchOpcode(int Opc) { 3666e46d84eea97792a66c0bb64f26aad3976a23365Bill Wendling return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; 3678d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson} 3688d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson 3698fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 3708fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 3718fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 3725adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 3738fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 3746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint getMatchingCondBranchOpcode(int Opc); 3756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 3762860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen/// Determine if MI can be folded into an ARM MOVCC instruction, and return the 3772860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen/// opcode of the SSA instruction representing the conditional MI. 3782860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesenunsigned canFoldARMInstrIntoMOVCC(unsigned Reg, 3792860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen MachineInstr *&MI, 3802860b7ea3a1d60213ee7228bd274bc4f8b170772Jakob Stoklund Olesen const MachineRegisterInfo &MRI); 3813be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 3823be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether 3833be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// the instruction is encoded with an 'S' bit is determined by the optional 3843be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick/// CPSR def operand. 3853be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trickunsigned convertAddSubFlagsOpcode(unsigned OldOpc); 3863be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 3876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of 3886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 3896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng/// code. 3906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 3916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 3926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 3936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 39457caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 3956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 3966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid emitT2RegPlusImmediate(MachineBasicBlock &MBB, 3976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 3986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 3996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 40057caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 401e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbachvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 40257caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov MachineBasicBlock::iterator &MBBI, DebugLoc dl, 403e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach unsigned DestReg, unsigned BaseReg, 404e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach int NumBytes, const TargetInstrInfo &TII, 405e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseRegisterInfo& MRI, 40657caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov unsigned MIFlags = 0); 4076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 409764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach/// rewriteARMFrameIndex / rewriteT2FrameIndex - 410cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the 411cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng/// offset could not be handled directly in MI, and return the left-over 412cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng/// portion by reference. 413cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 414cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 415cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII); 416cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng 417cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 418cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 419cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII); 4206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} // End llvm namespace 4226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 423334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#endif 424