ARMBaseInstrInfo.h revision 9fe2009956fc40f3aea46fb3c38dcfb61c4aca46
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#ifndef ARMBASEINSTRUCTIONINFO_H 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#define ARMBASEINSTRUCTIONINFO_H 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 17334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 18b8e9ac834a9c253e3f8f5caa8f229bafba0b4fcfAnton Korobeynikov#include "llvm/CodeGen/MachineInstrBuilder.h" 19b8e9ac834a9c253e3f8f5caa8f229bafba0b4fcfAnton Korobeynikov#include "llvm/Target/TargetInstrInfo.h" 2048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "llvm/ADT/DenseMap.h" 2148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng#include "llvm/ADT/SmallSet.h" 22334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 23334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinnamespace llvm { 244dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner class ARMSubtarget; 254dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner class ARMBaseRegisterInfo; 26334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// ARMII - This namespace holds all of the target specific flags that 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// instruction info tracks. 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 30334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinnamespace ARMII { 31334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin enum { 32334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin //===------------------------------------------------------------------===// 33334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Instruction Flags. 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 35334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin //===------------------------------------------------------------------===// 36334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // This four-bit field describes the addressing mode used. 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 38d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach AddrModeMask = 0x1f, 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeNone = 0, 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode1 = 1, 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode2 = 2, 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode3 = 3, 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode4 = 4, 44334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode5 = 5, 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode6 = 6, 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT1_1 = 7, 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT1_2 = 8, 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT1_4 = 9, 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT2_i12 = 11, 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT2_i8 = 12, 52334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT2_so = 13, 53334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT2_pc = 14, // +/- i12 for pc relative data 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT2_i8s4 = 15, // i8 * 4 553e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach AddrMode_i12 = 16, 56334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Size* - Flags to keep track of the size of an instruction. 58d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach SizeShift = 5, 59334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SizeMask = 7 << SizeShift, 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SizeSpecial = 1, // 0 byte pseudo or special case. 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Size8Bytes = 2, 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Size4Bytes = 3, 63334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Size2Bytes = 4, 64334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 65bffb5b39bea3288bc557b10f3ed1864e6c7857e0Bob Wilson // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load 66bffb5b39bea3288bc557b10f3ed1864e6c7857e0Bob Wilson // and store ops only. Generic "updating" flag is used for ld/st multiple. 67d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach IndexModeShift = 8, 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin IndexModeMask = 3 << IndexModeShift, 69334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin IndexModePre = 1, 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin IndexModePost = 2, 71bffb5b39bea3288bc557b10f3ed1864e6c7857e0Bob Wilson IndexModeUpd = 3, 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin //===------------------------------------------------------------------===// 74334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Instruction encoding formats. 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 76d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach FormShift = 10, 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FormMask = 0x3f << FormShift, 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Pseudo instructions 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pseudo = 0 << FormShift, 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Multiply instructions 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MulFrm = 1 << FormShift, 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Branch instructions 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BrFrm = 2 << FormShift, 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BrMiscFrm = 3 << FormShift, 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Data Processing instructions 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DPFrm = 4 << FormShift, 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DPSoRegFrm = 5 << FormShift, 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Load and Store 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LdFrm = 6 << FormShift, 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin StFrm = 7 << FormShift, 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LdMiscFrm = 8 << FormShift, 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin StMiscFrm = 9 << FormShift, 98334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LdStMulFrm = 10 << FormShift, 99334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 10081f04d59f6216d0e105daa9bde2250ca6af35fa5Johnny Chen LdStExFrm = 11 << FormShift, 1015278eb802fae2ee1a7b2a428596bc364d8bcd9dbJim Grosbach 102334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Miscellaneous arithmetic instructions 10381f04d59f6216d0e105daa9bde2250ca6af35fa5Johnny Chen ArithMiscFrm = 12 << FormShift, 1049a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson SatFrm = 13 << FormShift, 105334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Extend instructions 1079a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson ExtFrm = 14 << FormShift, 108334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 109334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // VFP formats 1109a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPUnaryFrm = 15 << FormShift, 1119a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPBinaryFrm = 16 << FormShift, 1129a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPConv1Frm = 17 << FormShift, 1139a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPConv2Frm = 18 << FormShift, 1149a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPConv3Frm = 19 << FormShift, 1159a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPConv4Frm = 20 << FormShift, 1169a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPConv5Frm = 21 << FormShift, 1179a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPLdStFrm = 22 << FormShift, 1189a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPLdStMulFrm = 23 << FormShift, 1199a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPMiscFrm = 24 << FormShift, 120334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb format 1229a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson ThumbFrm = 25 << FormShift, 123334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 12426532631653be91f9ccc99fca3bfb8027da7c70bBob Wilson // Miscelleaneous format 1259a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson MiscFrm = 26 << FormShift, 12626532631653be91f9ccc99fca3bfb8027da7c70bBob Wilson 1271a913ed17875d1a0fb490e1266b74c057c76a94bBob Wilson // NEON formats 1289a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NGetLnFrm = 27 << FormShift, 1299a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NSetLnFrm = 28 << FormShift, 1309a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NDupFrm = 29 << FormShift, 1319a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NLdStFrm = 30 << FormShift, 1329a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N1RegModImmFrm= 31 << FormShift, 1339a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N2RegFrm = 32 << FormShift, 1349a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NVCVTFrm = 33 << FormShift, 1359a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NVDupLnFrm = 34 << FormShift, 1369a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N2RegVShLFrm = 35 << FormShift, 1379a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N2RegVShRFrm = 36 << FormShift, 1389a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N3RegFrm = 37 << FormShift, 1399a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N3RegVShFrm = 38 << FormShift, 1409a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NVExtFrm = 39 << FormShift, 1419a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NVMulSLFrm = 40 << FormShift, 1429a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NVTBLFrm = 41 << FormShift, 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin //===------------------------------------------------------------------===// 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Misc flags. 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 147334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // UnaryDP - Indicates this is a unary data processing instruction, i.e. 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // it doesn't have a Rn operand. 149d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach UnaryDP = 1 << 16, 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 151334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Xform16Bit - Indicates this Thumb2 instruction may be transformed into 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // a 16-bit Thumb instruction if certain conditions are met. 153d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach Xform16Bit = 1 << 17, 154334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 155334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin //===------------------------------------------------------------------===// 156f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov // Code domain. 157d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach DomainShift = 18, 158f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov DomainMask = 3 << DomainShift, 159f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov DomainGeneral = 0 << DomainShift, 160f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov DomainVFP = 1 << DomainShift, 161f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov DomainNEON = 2 << DomainShift, 162f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov 163f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov //===------------------------------------------------------------------===// 164334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Field shifts - such shifts are used to set field while generating 165334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // machine instructions. 16642fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach // 16742fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach // FIXME: This list will need adjusting/fixing as the MC code emitter 16842fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach // takes shape and the ARMCodeEmitter.cpp bits go away. 16942fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach ShiftTypeShift = 4, 17042fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin M_BitShift = 5, 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ShiftImmShift = 5, 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ShiftShift = 7, 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin N_BitShift = 7, 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ImmHiShift = 8, 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SoRotImmShift = 8, 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegRsShift = 8, 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ExtRotImmShift = 10, 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegRdLoShift = 12, 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegRdShift = 12, 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegRdHiShift = 16, 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegRnShift = 16, 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin S_BitShift = 20, 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin W_BitShift = 21, 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AM3_I_BitShift = 22, 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin D_BitShift = 22, 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin U_BitShift = 23, 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin P_BitShift = 24, 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I_BitShift = 25, 190334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin CondShift = 28 191334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin }; 192b46aaa3874d2753632c48400c66be1a10ac18d42Evan Cheng} 193b46aaa3874d2753632c48400c66be1a10ac18d42Evan Cheng 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinclass ARMBaseInstrInfo : public TargetInstrInfoImpl { 1954dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner const ARMSubtarget &Subtarget; 19648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinprotected: 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can be only subclassed. 199f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov explicit ARMBaseInstrInfo(const ARMSubtarget &STI); 20048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinpublic: 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Return the non-pre/post incrementing version of 'Opc'. Return 0 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // if there is not such an opcode. 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 207334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const; 209334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 210334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0; 211f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov const ARMSubtarget &getSubtarget() const { return Subtarget; } 212334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 21348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng ScheduleHazardRecognizer * 2142da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick CreateTargetHazardRecognizer(const TargetMachine *TM, 2152da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const; 2162da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 2172da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick ScheduleHazardRecognizer * 2182da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 2192da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const; 22048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Branch analysis. 222334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 223334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 2252062875a7d8f7dd94a20d9e3a298e9e216efb4b5Chris Lattner bool AllowModify = false) const; 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *FBB, 2293bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 2303bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const; 231334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 232334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Predication support. 236ab331504452a833f27a030f13525b964545d768aEvan Cheng bool isPredicated(const MachineInstr *MI) const { 237ab331504452a833f27a030f13525b964545d768aEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 238ab331504452a833f27a030f13525b964545d768aEvan Cheng return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 239ab331504452a833f27a030f13525b964545d768aEvan Cheng } 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin : ARMCC::AL; 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool PredicateInstruction(MachineInstr *MI, 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const; 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 251334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual 252334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const; 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual bool DefinesPredicate(MachineInstr *MI, 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const; 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 258ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng virtual bool isPredicable(MachineInstr *MI) const; 259ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin /// GetInstSize - Returns the size of the specified MachineInstr. 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin /// 262334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const; 263334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 264334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 265334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const; 266334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const; 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 269ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen virtual void copyPhysReg(MachineBasicBlock &MBB, 270ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 271ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 272ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const; 2735732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator MBBI, 276334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FrameIndex, 277746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 278746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const; 279334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 280334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 281334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator MBBI, 282334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FrameIndex, 283746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 284746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const; 285334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 28662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 2878601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, 28862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng uint64_t Offset, 28962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 29062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const; 29162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 292fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 293fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator MI, 294fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 295d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 2969edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const; 297fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 29830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const; 29930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 300506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng virtual bool produceSameValue(const MachineInstr *MI0, 3019fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 3029fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const; 30386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 3044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 3054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// determine if two loads are loading from the same base address. It should 3064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// only return true if the base pointers are the same and the only 3074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// differences between the two addresses is the offset. It also returns the 3084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// offsets by reference. 3094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 3104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, int64_t &Offset2)const; 3114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 3124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 3134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 3144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// be scheduled togther. On some targets if two loads are loading from 3154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// addresses in the same cache line, it's better if they are scheduled 3164b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// together. This function takes two integers that represent the load offsets 3174b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// from the common base address. It returns true if it decides it's desirable 3184b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// to schedule the two loads together. "NumLoads" is the number of loads that 3194b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// have already been scheduled after Load1. 3204b722108e2cf8e77157e0879a23789cd44829933Bill Wendling virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 3214b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 3224b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const; 3234b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 32486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual bool isSchedulingBoundary(const MachineInstr *MI, 32586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 32686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const; 32713151432edace19ee867a93b5c14573df4f75d24Evan Cheng 32813151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, 3298239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumCyles, unsigned ExtraPredCycles, 330e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Prob, float Confidence) const; 33113151432edace19ee867a93b5c14573df4f75d24Evan Cheng 3328239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 3338239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumT, unsigned ExtraT, 3348239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 3358239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumF, unsigned ExtraF, 336e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, float Confidence) const; 33713151432edace19ee867a93b5c14573df4f75d24Evan Cheng 33813151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 3398239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumCyles, 340e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, 341e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Confidence) const { 3428239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return NumCyles == 1; 34313151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 344e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 345c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling /// AnalyzeCompare - For a comparison instruction, return the source register 346c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling /// in SrcReg and the value it compares against in CmpValue. Return true if 347c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling /// the comparison instruction can be analyzed. 348c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, 34904ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif int &CmpMask, int &CmpValue) const; 350e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 351a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling /// OptimizeCompareInstr - Convert the instruction to set the zero flag so 352e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling /// that we can remove a "comparison with zero". 353a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, 35404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif int CmpMask, int CmpValue, 355eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng const MachineRegisterInfo *MRI) const; 3565f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 357c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// FoldImmediate - 'Reg' is known to be defined by a move immediate 358c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// instruction, try to fold the immediate into the use instruction. 359c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 360c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg, MachineRegisterInfo *MRI) const; 361c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 3628239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 3638239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const; 364a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 365a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng virtual 366a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int getOperandLatency(const InstrItineraryData *ItinData, 367a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 368a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const; 369a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng virtual 370a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int getOperandLatency(const InstrItineraryData *ItinData, 371a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 372a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const; 373a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengprivate: 374344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getVLDMDefCycle(const InstrItineraryData *ItinData, 375344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 376344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 377344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const; 378344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getLDMDefCycle(const InstrItineraryData *ItinData, 379344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 380344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 381344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const; 382344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getVSTMUseCycle(const InstrItineraryData *ItinData, 383344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 384344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 385344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const; 386344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getSTMUseCycle(const InstrItineraryData *ItinData, 387344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 388344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 389344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const; 390a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int getOperandLatency(const InstrItineraryData *ItinData, 391a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID, 392a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 393a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID, 394a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const; 3952312842de0c641107dd04d7e056d02491cc781caEvan Cheng 3968239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng int getInstrLatency(const InstrItineraryData *ItinData, 3978239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI, unsigned *PredCost = 0) const; 3988239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 3998239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng int getInstrLatency(const InstrItineraryData *ItinData, 4008239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const; 4018239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 4022312842de0c641107dd04d7e056d02491cc781caEvan Cheng bool hasHighOperandLatency(const InstrItineraryData *ItinData, 4032312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 4042312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 4052312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const; 406c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng bool hasLowDefLatency(const InstrItineraryData *ItinData, 407c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const; 40848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 40948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengprivate: 41048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// Modeling special VFP / NEON fp MLA / MLS hazards. 41148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 41248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal 41348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// MLx table. 41448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng DenseMap<unsigned, unsigned> MLxEntryMap; 41548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 41648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause 41748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// stalls when scheduled together with fp MLA / MLS opcodes. 41848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng SmallSet<unsigned, 16> MLxHazardOpcodes; 41948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 42048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Chengpublic: 42148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS 42248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// instruction. 42348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool isFpMLxInstruction(unsigned Opcode) const { 42448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return MLxEntryMap.count(Opcode); 42548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 42648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 42748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// isFpMLxInstruction - This version also returns the multiply opcode and the 42848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// addition / subtraction opcode to expand to. Return true for 'HasLane' for 42948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// the MLX instructions with an extra lane operand. 43048575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 43148575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng unsigned &AddSubOpc, bool &NegAcc, 43248575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool &HasLane) const; 43348575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng 43448575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// canCauseFpMLxStall - Return true if an instruction of the specified opcode 43548575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// will cause stalls when scheduled after (within 4-cycle window) a fp 43648575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng /// MLA / MLS instruction. 43748575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng bool canCauseFpMLxStall(unsigned Opcode) const { 43848575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng return MLxHazardOpcodes.count(Opcode); 43948575f6ea7d5cd21ab29ca370f58fcf9ca31400bEvan Cheng } 4406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng}; 4415ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 4426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 4436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengconst MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 4446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 4456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 4465ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 4476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 4486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengconst MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 4496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return MIB.addReg(0); 4506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 45183e0e36be8390fee1235783731f6c64aa604b7eeEvan Cheng 4526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 453e8af1f9afe5e70e1d4ec4d00a6870428dba88692Evan Chengconst MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, 454e8af1f9afe5e70e1d4ec4d00a6870428dba88692Evan Cheng bool isDead = false) { 455e8af1f9afe5e70e1d4ec4d00a6870428dba88692Evan Cheng return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 4566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 4576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 459bc9b754091ea281e769e487f396b40f6675b9edbEvan Chengconst MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { 460bc9b754091ea281e769e487f396b40f6675b9edbEvan Cheng return MIB.addReg(0); 461bc9b754091ea281e769e487f396b40f6675b9edbEvan Cheng} 462bc9b754091ea281e769e487f396b40f6675b9edbEvan Cheng 463bc9b754091ea281e769e487f396b40f6675b9edbEvan Chengstatic inline 4646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengbool isUncondBranchOpcode(int Opc) { 4656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 466334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 467334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 4686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 4696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengbool isCondBranchOpcode(int Opc) { 4706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; 4716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 4726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 4746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengbool isJumpTableBranchOpcode(int Opc) { 4756495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || 4766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; 4776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 4786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4798d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilsonstatic inline 4808d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilsonbool isIndirectBranchOpcode(int Opc) { 4816e46d84eea97792a66c0bb64f26aad3976a23365Bill Wendling return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; 4828d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson} 4838d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson 4848fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 4858fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 4868fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 4875adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 4888fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 4896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint getMatchingCondBranchOpcode(int Opc); 4906495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of 4926495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 4936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng/// code. 4946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 4956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 4966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 4976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 4986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII); 4996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 5006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid emitT2RegPlusImmediate(MachineBasicBlock &MBB, 5016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 5026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 5036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 5046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII); 505e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbachvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 506e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MachineBasicBlock::iterator &MBBI, 507e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach unsigned DestReg, unsigned BaseReg, 508e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach int NumBytes, const TargetInstrInfo &TII, 509e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseRegisterInfo& MRI, 510e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach DebugLoc dl); 5116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 5126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 513764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach/// rewriteARMFrameIndex / rewriteT2FrameIndex - 514cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the 515cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng/// offset could not be handled directly in MI, and return the left-over 516cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng/// portion by reference. 517cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 518cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 519cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII); 520cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng 521cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 522cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 523cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII); 5246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 5256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} // End llvm namespace 5266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 527334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#endif 528