ARMBaseInstrInfo.h revision c4af4638dfdab0dc3b6257276cfad2ee45053060
131c24bf5b39cc8391d4cfdbf8cf5163975fdb81eJim Grosbach//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===// 2334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 3334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// The LLVM Compiler Infrastructure 4334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 5334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file is distributed under the University of Illinois Open Source 6334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// License. See LICENSE.TXT for details. 7334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 8334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 9334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 10334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// This file contains the Base ARM implementation of the TargetInstrInfo class. 11334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin// 12334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin//===----------------------------------------------------------------------===// 13334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 14334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#ifndef ARMBASEINSTRUCTIONINFO_H 15334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#define ARMBASEINSTRUCTIONINFO_H 16334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 17334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#include "ARM.h" 18b8e9ac834a9c253e3f8f5caa8f229bafba0b4fcfAnton Korobeynikov#include "llvm/CodeGen/MachineInstrBuilder.h" 19b8e9ac834a9c253e3f8f5caa8f229bafba0b4fcfAnton Korobeynikov#include "llvm/Target/TargetInstrInfo.h" 20334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 21334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinnamespace llvm { 224dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner class ARMSubtarget; 234dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner class ARMBaseRegisterInfo; 24334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 25334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// ARMII - This namespace holds all of the target specific flags that 26334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// instruction info tracks. 27334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin/// 28334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinnamespace ARMII { 29334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin enum { 30334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin //===------------------------------------------------------------------===// 31334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Instruction Flags. 32334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 33334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin //===------------------------------------------------------------------===// 34334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // This four-bit field describes the addressing mode used. 35334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 36d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach AddrModeMask = 0x1f, 37334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeNone = 0, 38334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode1 = 1, 39334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode2 = 2, 40334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode3 = 3, 41334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode4 = 4, 42334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode5 = 5, 43334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrMode6 = 6, 44334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT1_1 = 7, 45334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT1_2 = 8, 46334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT1_4 = 9, 47334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data 48334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT2_i12 = 11, 49334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT2_i8 = 12, 50334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT2_so = 13, 51334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT2_pc = 14, // +/- i12 for pc relative data 52334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AddrModeT2_i8s4 = 15, // i8 * 4 533e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach AddrMode_i12 = 16, 54334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 55334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Size* - Flags to keep track of the size of an instruction. 56d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach SizeShift = 5, 57334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SizeMask = 7 << SizeShift, 58334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SizeSpecial = 1, // 0 byte pseudo or special case. 59334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Size8Bytes = 2, 60334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Size4Bytes = 3, 61334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Size2Bytes = 4, 62334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 63bffb5b39bea3288bc557b10f3ed1864e6c7857e0Bob Wilson // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load 64bffb5b39bea3288bc557b10f3ed1864e6c7857e0Bob Wilson // and store ops only. Generic "updating" flag is used for ld/st multiple. 65d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach IndexModeShift = 8, 66334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin IndexModeMask = 3 << IndexModeShift, 67334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin IndexModePre = 1, 68334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin IndexModePost = 2, 69bffb5b39bea3288bc557b10f3ed1864e6c7857e0Bob Wilson IndexModeUpd = 3, 70334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 71334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin //===------------------------------------------------------------------===// 72334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Instruction encoding formats. 73334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // 74d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach FormShift = 10, 75334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin FormMask = 0x3f << FormShift, 76334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 77334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Pseudo instructions 78334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin Pseudo = 0 << FormShift, 79334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 80334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Multiply instructions 81334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MulFrm = 1 << FormShift, 82334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 83334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Branch instructions 84334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BrFrm = 2 << FormShift, 85334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin BrMiscFrm = 3 << FormShift, 86334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 87334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Data Processing instructions 88334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DPFrm = 4 << FormShift, 89334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin DPSoRegFrm = 5 << FormShift, 90334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 91334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Load and Store 92334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LdFrm = 6 << FormShift, 93334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin StFrm = 7 << FormShift, 94334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LdMiscFrm = 8 << FormShift, 95334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin StMiscFrm = 9 << FormShift, 96334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LdStMulFrm = 10 << FormShift, 97334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 9881f04d59f6216d0e105daa9bde2250ca6af35fa5Johnny Chen LdStExFrm = 11 << FormShift, 995278eb802fae2ee1a7b2a428596bc364d8bcd9dbJim Grosbach 100334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Miscellaneous arithmetic instructions 10181f04d59f6216d0e105daa9bde2250ca6af35fa5Johnny Chen ArithMiscFrm = 12 << FormShift, 1029a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson SatFrm = 13 << FormShift, 103334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 104334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Extend instructions 1059a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson ExtFrm = 14 << FormShift, 106334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 107334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // VFP formats 1089a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPUnaryFrm = 15 << FormShift, 1099a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPBinaryFrm = 16 << FormShift, 1109a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPConv1Frm = 17 << FormShift, 1119a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPConv2Frm = 18 << FormShift, 1129a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPConv3Frm = 19 << FormShift, 1139a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPConv4Frm = 20 << FormShift, 1149a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPConv5Frm = 21 << FormShift, 1159a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPLdStFrm = 22 << FormShift, 1169a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPLdStMulFrm = 23 << FormShift, 1179a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson VFPMiscFrm = 24 << FormShift, 118334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 119334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Thumb format 1209a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson ThumbFrm = 25 << FormShift, 121334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 12226532631653be91f9ccc99fca3bfb8027da7c70bBob Wilson // Miscelleaneous format 1239a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson MiscFrm = 26 << FormShift, 12426532631653be91f9ccc99fca3bfb8027da7c70bBob Wilson 1251a913ed17875d1a0fb490e1266b74c057c76a94bBob Wilson // NEON formats 1269a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NGetLnFrm = 27 << FormShift, 1279a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NSetLnFrm = 28 << FormShift, 1289a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NDupFrm = 29 << FormShift, 1299a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NLdStFrm = 30 << FormShift, 1309a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N1RegModImmFrm= 31 << FormShift, 1319a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N2RegFrm = 32 << FormShift, 1329a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NVCVTFrm = 33 << FormShift, 1339a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NVDupLnFrm = 34 << FormShift, 1349a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N2RegVShLFrm = 35 << FormShift, 1359a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N2RegVShRFrm = 36 << FormShift, 1369a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N3RegFrm = 37 << FormShift, 1379a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson N3RegVShFrm = 38 << FormShift, 1389a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NVExtFrm = 39 << FormShift, 1399a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NVMulSLFrm = 40 << FormShift, 1409a1c189d9e7472f336f3c6d61be76bc46b25749eBob Wilson NVTBLFrm = 41 << FormShift, 141334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 142334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin //===------------------------------------------------------------------===// 143334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Misc flags. 144334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 145334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // UnaryDP - Indicates this is a unary data processing instruction, i.e. 146334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // it doesn't have a Rn operand. 147d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach UnaryDP = 1 << 16, 148334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 149334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Xform16Bit - Indicates this Thumb2 instruction may be transformed into 150334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // a 16-bit Thumb instruction if certain conditions are met. 151d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach Xform16Bit = 1 << 17, 152334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 153334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin //===------------------------------------------------------------------===// 154f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov // Code domain. 155d86609fca46ac9e186557d2d7b12f029febecf0eJim Grosbach DomainShift = 18, 156f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov DomainMask = 3 << DomainShift, 157f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov DomainGeneral = 0 << DomainShift, 158f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov DomainVFP = 1 << DomainShift, 159f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov DomainNEON = 2 << DomainShift, 160f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov 161f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov //===------------------------------------------------------------------===// 162334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Field shifts - such shifts are used to set field while generating 163334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // machine instructions. 16442fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach // 16542fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach // FIXME: This list will need adjusting/fixing as the MC code emitter 16642fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach // takes shape and the ARMCodeEmitter.cpp bits go away. 16742fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach ShiftTypeShift = 4, 16842fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach 169334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin M_BitShift = 5, 170334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ShiftImmShift = 5, 171334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ShiftShift = 7, 172334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin N_BitShift = 7, 173334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ImmHiShift = 8, 174334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SoRotImmShift = 8, 175334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegRsShift = 8, 176334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ExtRotImmShift = 10, 177334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegRdLoShift = 12, 178334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegRdShift = 12, 179334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegRdHiShift = 16, 180334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin RegRnShift = 16, 181334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin S_BitShift = 20, 182334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin W_BitShift = 21, 183334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin AM3_I_BitShift = 22, 184334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin D_BitShift = 22, 185334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin U_BitShift = 23, 186334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin P_BitShift = 24, 187334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin I_BitShift = 25, 188334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin CondShift = 28 189334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin }; 190b46aaa3874d2753632c48400c66be1a10ac18d42Evan Cheng} 191b46aaa3874d2753632c48400c66be1a10ac18d42Evan Cheng 192334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinclass ARMBaseInstrInfo : public TargetInstrInfoImpl { 1934dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner const ARMSubtarget &Subtarget; 194334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinprotected: 195334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Can be only subclassed. 196f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov explicit ARMBaseInstrInfo(const ARMSubtarget &STI); 197334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwinpublic: 198334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Return the non-pre/post incrementing version of 'Opc'. Return 0 199334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // if there is not such an opcode. 200334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; 201334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 202334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 203334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator &MBBI, 204334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin LiveVariables *LV) const; 205334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 206334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0; 207f95215f551949d5e5adfbf4753aa833b9009b77aAnton Korobeynikov const ARMSubtarget &getSubtarget() const { return Subtarget; } 208334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 2092457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 2102457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng MachineBasicBlock::iterator MI, 2112457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng const std::vector<CalleeSavedInfo> &CSI, 2122457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng const TargetRegisterInfo *TRI) const; 2132457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng 214334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Branch analysis. 215334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 216334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *&FBB, 217334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin SmallVectorImpl<MachineOperand> &Cond, 2182062875a7d8f7dd94a20d9e3a298e9e216efb4b5Chris Lattner bool AllowModify = false) const; 219334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 220334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 221334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock *FBB, 2223bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 2233bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const; 224334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 225334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual 226334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 227334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 228334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin // Predication support. 229ab331504452a833f27a030f13525b964545d768aEvan Cheng bool isPredicated(const MachineInstr *MI) const { 230ab331504452a833f27a030f13525b964545d768aEvan Cheng int PIdx = MI->findFirstPredOperandIdx(); 231ab331504452a833f27a030f13525b964545d768aEvan Cheng return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 232ab331504452a833f27a030f13525b964545d768aEvan Cheng } 233334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 234334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { 235334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int PIdx = MI->findFirstPredOperandIdx(); 236334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() 237334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin : ARMCC::AL; 238334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin } 239334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 240334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual 241334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool PredicateInstruction(MachineInstr *MI, 242334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred) const; 243334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 244334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual 245334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 246334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin const SmallVectorImpl<MachineOperand> &Pred2) const; 247334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 248334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual bool DefinesPredicate(MachineInstr *MI, 249334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin std::vector<MachineOperand> &Pred) const; 250334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 251ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng virtual bool isPredicable(MachineInstr *MI) const; 252ac0869dc8a7986855c5557cc67d4709600158ef5Evan Cheng 253334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin /// GetInstSize - Returns the size of the specified MachineInstr. 254334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin /// 255334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const; 256334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 257334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 258334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const; 259334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 260334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin int &FrameIndex) const; 261334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 262ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen virtual void copyPhysReg(MachineBasicBlock &MBB, 263ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 264ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 265ac2736670034e8942939b9fccf8e4618a0bda908Jakob Stoklund Olesen bool KillSrc) const; 2665732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng 267334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 268334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator MBBI, 269334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned SrcReg, bool isKill, int FrameIndex, 270746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 271746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const; 272334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 273334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 274334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin MachineBasicBlock::iterator MBBI, 275334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin unsigned DestReg, int FrameIndex, 276746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 277746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const; 278334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 27962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 2808601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, 28162b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng uint64_t Offset, 28262b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng const MDNode *MDPtr, 28362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng DebugLoc DL) const; 28462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 285fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 286fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng MachineBasicBlock::iterator MI, 287fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng unsigned DestReg, unsigned SubIdx, 288d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 2899edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const; 290fdc834046efd427d474e3b899ec69354c05071e0Evan Cheng 29130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const; 29230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 293506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng virtual bool produceSameValue(const MachineInstr *MI0, 294506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const; 29586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 2964b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 2974b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// determine if two loads are loading from the same base address. It should 2984b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// only return true if the base pointers are the same and the only 2994b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// differences between the two addresses is the offset. It also returns the 3004b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// offsets by reference. 3014b722108e2cf8e77157e0879a23789cd44829933Bill Wendling virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 3024b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t &Offset1, int64_t &Offset2)const; 3034b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 3044b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 3054b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 3064b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// be scheduled togther. On some targets if two loads are loading from 3074b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// addresses in the same cache line, it's better if they are scheduled 3084b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// together. This function takes two integers that represent the load offsets 3094b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// from the common base address. It returns true if it decides it's desirable 3104b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// to schedule the two loads together. "NumLoads" is the number of loads that 3114b722108e2cf8e77157e0879a23789cd44829933Bill Wendling /// have already been scheduled after Load1. 3124b722108e2cf8e77157e0879a23789cd44829933Bill Wendling virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 3134b722108e2cf8e77157e0879a23789cd44829933Bill Wendling int64_t Offset1, int64_t Offset2, 3144b722108e2cf8e77157e0879a23789cd44829933Bill Wendling unsigned NumLoads) const; 3154b722108e2cf8e77157e0879a23789cd44829933Bill Wendling 31686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual bool isSchedulingBoundary(const MachineInstr *MI, 31786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 31886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const; 31913151432edace19ee867a93b5c14573df4f75d24Evan Cheng 32013151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, 3218239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumCyles, unsigned ExtraPredCycles, 322e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Prob, float Confidence) const; 32313151432edace19ee867a93b5c14573df4f75d24Evan Cheng 3248239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 3258239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumT, unsigned ExtraT, 3268239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 3278239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumF, unsigned ExtraF, 328e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, float Confidence) const; 32913151432edace19ee867a93b5c14573df4f75d24Evan Cheng 33013151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 3318239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumCyles, 332e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, 333e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Confidence) const { 3348239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng return NumCyles == 1; 33513151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 336e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 337c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling /// AnalyzeCompare - For a comparison instruction, return the source register 338c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling /// in SrcReg and the value it compares against in CmpValue. Return true if 339c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling /// the comparison instruction can be analyzed. 340c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, 34104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif int &CmpMask, int &CmpValue) const; 342e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 343a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling /// OptimizeCompareInstr - Convert the instruction to set the zero flag so 344e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling /// that we can remove a "comparison with zero". 345a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, 34604ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif int CmpMask, int CmpValue, 347eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng const MachineRegisterInfo *MRI) const; 3485f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 349c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// FoldImmediate - 'Reg' is known to be defined by a move immediate 350c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// instruction, try to fold the immediate into the use instruction. 351c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 352c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg, MachineRegisterInfo *MRI) const; 353c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 3548239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 3558239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const; 356a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 357a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng virtual 358a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int getOperandLatency(const InstrItineraryData *ItinData, 359a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 360a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const; 361a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng virtual 362a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int getOperandLatency(const InstrItineraryData *ItinData, 363a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *DefNode, unsigned DefIdx, 364a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng SDNode *UseNode, unsigned UseIdx) const; 365a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Chengprivate: 366344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getVLDMDefCycle(const InstrItineraryData *ItinData, 367344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 368344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 369344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const; 370344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getLDMDefCycle(const InstrItineraryData *ItinData, 371344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &DefTID, 372344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefClass, 373344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned DefIdx, unsigned DefAlign) const; 374344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getVSTMUseCycle(const InstrItineraryData *ItinData, 375344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 376344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 377344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const; 378344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng int getSTMUseCycle(const InstrItineraryData *ItinData, 379344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng const TargetInstrDesc &UseTID, 380344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseClass, 381344d9db97062736cd66da6c07baa9108b6cfa419Evan Cheng unsigned UseIdx, unsigned UseAlign) const; 382a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng int getOperandLatency(const InstrItineraryData *ItinData, 383a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &DefTID, 384a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned DefIdx, unsigned DefAlign, 385a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng const TargetInstrDesc &UseTID, 386a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng unsigned UseIdx, unsigned UseAlign) const; 3872312842de0c641107dd04d7e056d02491cc781caEvan Cheng 3888239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng int getInstrLatency(const InstrItineraryData *ItinData, 3898239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI, unsigned *PredCost = 0) const; 3908239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 3918239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng int getInstrLatency(const InstrItineraryData *ItinData, 3928239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const; 3938239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 3942312842de0c641107dd04d7e056d02491cc781caEvan Cheng bool hasHighOperandLatency(const InstrItineraryData *ItinData, 3952312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 3962312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 3972312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const; 398c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng bool hasLowDefLatency(const InstrItineraryData *ItinData, 399c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const; 4006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng}; 4015ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 4026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 4036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengconst MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 4046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 4056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 4065ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng 4076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 4086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengconst MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 4096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return MIB.addReg(0); 4106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 41183e0e36be8390fee1235783731f6c64aa604b7eeEvan Cheng 4126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 413e8af1f9afe5e70e1d4ec4d00a6870428dba88692Evan Chengconst MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, 414e8af1f9afe5e70e1d4ec4d00a6870428dba88692Evan Cheng bool isDead = false) { 415e8af1f9afe5e70e1d4ec4d00a6870428dba88692Evan Cheng return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 4166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 4176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 419bc9b754091ea281e769e487f396b40f6675b9edbEvan Chengconst MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { 420bc9b754091ea281e769e487f396b40f6675b9edbEvan Cheng return MIB.addReg(0); 421bc9b754091ea281e769e487f396b40f6675b9edbEvan Cheng} 422bc9b754091ea281e769e487f396b40f6675b9edbEvan Cheng 423bc9b754091ea281e769e487f396b40f6675b9edbEvan Chengstatic inline 4246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengbool isUncondBranchOpcode(int Opc) { 4256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 426334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin} 427334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin 4286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 4296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengbool isCondBranchOpcode(int Opc) { 4306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; 4316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 4326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengstatic inline 4346495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengbool isJumpTableBranchOpcode(int Opc) { 4356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || 4366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; 4376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} 4386495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4398d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilsonstatic inline 4408d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilsonbool isIndirectBranchOpcode(int Opc) { 441ce7bf1c55f5238870bae2909cd368151f1d813d1Anton Korobeynikov return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; 4428d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson} 4438d4de5abfa1bcd974554ea14904ebf7af289e84dBob Wilson 4448fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// getInstrPredicate - If instruction is predicated, returns its predicate 4458fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// condition, otherwise returns AL. It also returns the condition code 4468fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng/// register by reference. 4475adb66a646e2ec32265263739f5b01c3f50c176aEvan ChengARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 4488fb903604e83dfd63659c919042bf2bfed3c940fEvan Cheng 4496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengint getMatchingCondBranchOpcode(int Opc); 4506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of 4526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 4536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng/// code. 4546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid emitARMRegPlusImmediate(MachineBasicBlock &MBB, 4556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 4566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 4576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 4586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII); 4596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid emitT2RegPlusImmediate(MachineBasicBlock &MBB, 4616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock::iterator &MBBI, DebugLoc dl, 4626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned DestReg, unsigned BaseReg, int NumBytes, 4636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMCC::CondCodes Pred, unsigned PredReg, 4646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng const ARMBaseInstrInfo &TII); 465e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbachvoid emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 466e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MachineBasicBlock::iterator &MBBI, 467e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach unsigned DestReg, unsigned BaseReg, 468e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach int NumBytes, const TargetInstrInfo &TII, 469e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseRegisterInfo& MRI, 470e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach DebugLoc dl); 4716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 473764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach/// rewriteARMFrameIndex / rewriteT2FrameIndex - 474cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the 475cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng/// offset could not be handled directly in MI, and return the left-over 476cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng/// portion by reference. 477cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 478cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 479cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII); 480cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng 481cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Chengbool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 482cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng unsigned FrameReg, int &Offset, 483cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng const ARMBaseInstrInfo &TII); 4846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 4856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng} // End llvm namespace 4866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 487334c26473bba3ad8b88341bb0d25d0ac2008bb8dDavid Goodwin#endif 488