1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "llvm/MC/MCDisassembler.h" 13#include "MCTargetDesc/ARMAddressingModes.h" 14#include "MCTargetDesc/ARMBaseInfo.h" 15#include "MCTargetDesc/ARMMCExpr.h" 16#include "llvm/MC/MCContext.h" 17#include "llvm/MC/MCExpr.h" 18#include "llvm/MC/MCFixedLenDisassembler.h" 19#include "llvm/MC/MCInst.h" 20#include "llvm/MC/MCInstrDesc.h" 21#include "llvm/MC/MCSubtargetInfo.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/LEB128.h" 25#include "llvm/Support/MemoryObject.h" 26#include "llvm/Support/TargetRegistry.h" 27#include "llvm/Support/raw_ostream.h" 28#include <vector> 29 30using namespace llvm; 31 32typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85} 86 87namespace { 88/// ARMDisassembler - ARM disassembler for all ARM platforms. 89class ARMDisassembler : public MCDisassembler { 90public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107}; 108 109/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110class ThumbDisassembler : public MCDisassembler { 111public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133}; 134} 135 136static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149} 150 151 152// Forward declare these because the autogenerated code will reference them. 153// Definitions are further down. 154static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 185 unsigned RegNo, uint64_t Address, 186 const void *Decoder); 187 188static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 201static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 212 uint64_t Address, const void *Decoder); 213static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 218static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 219 unsigned Insn, 220 uint64_t Adddress, 221 const void *Decoder); 222static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 265 uint64_t Address, const void *Decoder); 266static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 327 const void *Decoder); 328 329 330static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 331 uint64_t Address, const void *Decoder); 332static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void* Decoder); 354static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void* Decoder); 356static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void* Decoder); 358static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 363 uint64_t Address, const void *Decoder); 364static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 365 uint64_t Address, const void *Decoder); 366static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 369 uint64_t Address, const void *Decoder); 370static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 371 uint64_t Address, const void *Decoder); 372static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 373 uint64_t Address, const void *Decoder); 374static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 387 uint64_t Address, const void *Decoder); 388static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 393 uint64_t Address, const void *Decoder); 394static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 395 uint64_t Address, const void *Decoder); 396static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 401 uint64_t Address, const void *Decoder); 402 403static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 406 uint64_t Address, const void *Decoder); 407#include "ARMGenDisassemblerTables.inc" 408 409static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 410 return new ARMDisassembler(STI); 411} 412 413static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 414 return new ThumbDisassembler(STI); 415} 416 417DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 418 const MemoryObject &Region, 419 uint64_t Address, 420 raw_ostream &os, 421 raw_ostream &cs) const { 422 CommentStream = &cs; 423 424 uint8_t bytes[4]; 425 426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 428 429 // We want to read exactly 4 bytes of data. 430 if (Region.readBytes(Address, 4, bytes) == -1) { 431 Size = 0; 432 return MCDisassembler::Fail; 433 } 434 435 // Encoded as a small-endian 32-bit word in the stream. 436 uint32_t insn = (bytes[3] << 24) | 437 (bytes[2] << 16) | 438 (bytes[1] << 8) | 439 (bytes[0] << 0); 440 441 // Calling the auto-generated decoder function. 442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 443 Address, this, STI); 444 if (result != MCDisassembler::Fail) { 445 Size = 4; 446 return result; 447 } 448 449 // VFP and NEON instructions, similarly, are shared between ARM 450 // and Thumb modes. 451 MI.clear(); 452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 453 if (result != MCDisassembler::Fail) { 454 Size = 4; 455 return result; 456 } 457 458 MI.clear(); 459 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI); 460 if (result != MCDisassembler::Fail) { 461 Size = 4; 462 return result; 463 } 464 465 MI.clear(); 466 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 467 this, STI); 468 if (result != MCDisassembler::Fail) { 469 Size = 4; 470 // Add a fake predicate operand, because we share these instruction 471 // definitions with Thumb2 where these instructions are predicable. 472 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 473 return MCDisassembler::Fail; 474 return result; 475 } 476 477 MI.clear(); 478 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 479 this, STI); 480 if (result != MCDisassembler::Fail) { 481 Size = 4; 482 // Add a fake predicate operand, because we share these instruction 483 // definitions with Thumb2 where these instructions are predicable. 484 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 485 return MCDisassembler::Fail; 486 return result; 487 } 488 489 MI.clear(); 490 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 491 this, STI); 492 if (result != MCDisassembler::Fail) { 493 Size = 4; 494 // Add a fake predicate operand, because we share these instruction 495 // definitions with Thumb2 where these instructions are predicable. 496 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 497 return MCDisassembler::Fail; 498 return result; 499 } 500 501 MI.clear(); 502 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address, 503 this, STI); 504 if (result != MCDisassembler::Fail) { 505 Size = 4; 506 return result; 507 } 508 509 MI.clear(); 510 Size = 0; 511 return MCDisassembler::Fail; 512} 513 514namespace llvm { 515extern const MCInstrDesc ARMInsts[]; 516} 517 518/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 519/// immediate Value in the MCInst. The immediate Value has had any PC 520/// adjustment made by the caller. If the instruction is a branch instruction 521/// then isBranch is true, else false. If the getOpInfo() function was set as 522/// part of the setupForSymbolicDisassembly() call then that function is called 523/// to get any symbolic information at the Address for this instruction. If 524/// that returns non-zero then the symbolic information it returns is used to 525/// create an MCExpr and that is added as an operand to the MCInst. If 526/// getOpInfo() returns zero and isBranch is true then a symbol look up for 527/// Value is done and if a symbol is found an MCExpr is created with that, else 528/// an MCExpr with Value is created. This function returns true if it adds an 529/// operand to the MCInst and false otherwise. 530static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 531 bool isBranch, uint64_t InstSize, 532 MCInst &MI, const void *Decoder) { 533 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 534 // FIXME: Does it make sense for value to be negative? 535 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 536 /* Offset */ 0, InstSize); 537} 538 539/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 540/// referenced by a load instruction with the base register that is the Pc. 541/// These can often be values in a literal pool near the Address of the 542/// instruction. The Address of the instruction and its immediate Value are 543/// used as a possible literal pool entry. The SymbolLookUp call back will 544/// return the name of a symbol referenced by the literal pool's entry if 545/// the referenced address is that of a symbol. Or it will return a pointer to 546/// a literal 'C' string if the referenced address of the literal pool's entry 547/// is an address into a section with 'C' string literals. 548static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 549 const void *Decoder) { 550 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 551 Dis->tryAddingPcLoadReferenceComment(Value, Address); 552} 553 554// Thumb1 instructions don't have explicit S bits. Rather, they 555// implicitly set CPSR. Since it's not represented in the encoding, the 556// auto-generated decoder won't inject the CPSR operand. We need to fix 557// that as a post-pass. 558static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 559 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 560 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 561 MCInst::iterator I = MI.begin(); 562 for (unsigned i = 0; i < NumOps; ++i, ++I) { 563 if (I == MI.end()) break; 564 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 565 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 566 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 567 return; 568 } 569 } 570 571 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 572} 573 574// Most Thumb instructions don't have explicit predicates in the 575// encoding, but rather get their predicates from IT context. We need 576// to fix up the predicate operands using this context information as a 577// post-pass. 578MCDisassembler::DecodeStatus 579ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 580 MCDisassembler::DecodeStatus S = Success; 581 582 // A few instructions actually have predicates encoded in them. Don't 583 // try to overwrite it if we're seeing one of those. 584 switch (MI.getOpcode()) { 585 case ARM::tBcc: 586 case ARM::t2Bcc: 587 case ARM::tCBZ: 588 case ARM::tCBNZ: 589 case ARM::tCPS: 590 case ARM::t2CPS3p: 591 case ARM::t2CPS2p: 592 case ARM::t2CPS1p: 593 case ARM::tMOVSr: 594 case ARM::tSETEND: 595 // Some instructions (mostly conditional branches) are not 596 // allowed in IT blocks. 597 if (ITBlock.instrInITBlock()) 598 S = SoftFail; 599 else 600 return Success; 601 break; 602 case ARM::tB: 603 case ARM::t2B: 604 case ARM::t2TBB: 605 case ARM::t2TBH: 606 // Some instructions (mostly unconditional branches) can 607 // only appears at the end of, or outside of, an IT. 608 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 609 S = SoftFail; 610 break; 611 default: 612 break; 613 } 614 615 // If we're in an IT block, base the predicate on that. Otherwise, 616 // assume a predicate of AL. 617 unsigned CC; 618 CC = ITBlock.getITCC(); 619 if (CC == 0xF) 620 CC = ARMCC::AL; 621 if (ITBlock.instrInITBlock()) 622 ITBlock.advanceITState(); 623 624 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 625 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 626 MCInst::iterator I = MI.begin(); 627 for (unsigned i = 0; i < NumOps; ++i, ++I) { 628 if (I == MI.end()) break; 629 if (OpInfo[i].isPredicate()) { 630 I = MI.insert(I, MCOperand::CreateImm(CC)); 631 ++I; 632 if (CC == ARMCC::AL) 633 MI.insert(I, MCOperand::CreateReg(0)); 634 else 635 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 636 return S; 637 } 638 } 639 640 I = MI.insert(I, MCOperand::CreateImm(CC)); 641 ++I; 642 if (CC == ARMCC::AL) 643 MI.insert(I, MCOperand::CreateReg(0)); 644 else 645 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 646 647 return S; 648} 649 650// Thumb VFP instructions are a special case. Because we share their 651// encodings between ARM and Thumb modes, and they are predicable in ARM 652// mode, the auto-generated decoder will give them an (incorrect) 653// predicate operand. We need to rewrite these operands based on the IT 654// context as a post-pass. 655void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 656 unsigned CC; 657 CC = ITBlock.getITCC(); 658 if (ITBlock.instrInITBlock()) 659 ITBlock.advanceITState(); 660 661 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 662 MCInst::iterator I = MI.begin(); 663 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 664 for (unsigned i = 0; i < NumOps; ++i, ++I) { 665 if (OpInfo[i].isPredicate() ) { 666 I->setImm(CC); 667 ++I; 668 if (CC == ARMCC::AL) 669 I->setReg(0); 670 else 671 I->setReg(ARM::CPSR); 672 return; 673 } 674 } 675} 676 677DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 678 const MemoryObject &Region, 679 uint64_t Address, 680 raw_ostream &os, 681 raw_ostream &cs) const { 682 CommentStream = &cs; 683 684 uint8_t bytes[4]; 685 686 assert((STI.getFeatureBits() & ARM::ModeThumb) && 687 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 688 689 // We want to read exactly 2 bytes of data. 690 if (Region.readBytes(Address, 2, bytes) == -1) { 691 Size = 0; 692 return MCDisassembler::Fail; 693 } 694 695 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 696 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 697 Address, this, STI); 698 if (result != MCDisassembler::Fail) { 699 Size = 2; 700 Check(result, AddThumbPredicate(MI)); 701 return result; 702 } 703 704 MI.clear(); 705 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 706 Address, this, STI); 707 if (result) { 708 Size = 2; 709 bool InITBlock = ITBlock.instrInITBlock(); 710 Check(result, AddThumbPredicate(MI)); 711 AddThumb1SBit(MI, InITBlock); 712 return result; 713 } 714 715 MI.clear(); 716 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 717 Address, this, STI); 718 if (result != MCDisassembler::Fail) { 719 Size = 2; 720 721 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 722 // the Thumb predicate. 723 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 724 result = MCDisassembler::SoftFail; 725 726 Check(result, AddThumbPredicate(MI)); 727 728 // If we find an IT instruction, we need to parse its condition 729 // code and mask operands so that we can apply them correctly 730 // to the subsequent instructions. 731 if (MI.getOpcode() == ARM::t2IT) { 732 733 unsigned Firstcond = MI.getOperand(0).getImm(); 734 unsigned Mask = MI.getOperand(1).getImm(); 735 ITBlock.setITState(Firstcond, Mask); 736 } 737 738 return result; 739 } 740 741 // We want to read exactly 4 bytes of data. 742 if (Region.readBytes(Address, 4, bytes) == -1) { 743 Size = 0; 744 return MCDisassembler::Fail; 745 } 746 747 uint32_t insn32 = (bytes[3] << 8) | 748 (bytes[2] << 0) | 749 (bytes[1] << 24) | 750 (bytes[0] << 16); 751 MI.clear(); 752 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 753 this, STI); 754 if (result != MCDisassembler::Fail) { 755 Size = 4; 756 bool InITBlock = ITBlock.instrInITBlock(); 757 Check(result, AddThumbPredicate(MI)); 758 AddThumb1SBit(MI, InITBlock); 759 return result; 760 } 761 762 MI.clear(); 763 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 764 this, STI); 765 if (result != MCDisassembler::Fail) { 766 Size = 4; 767 Check(result, AddThumbPredicate(MI)); 768 return result; 769 } 770 771 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 772 MI.clear(); 773 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 774 if (result != MCDisassembler::Fail) { 775 Size = 4; 776 UpdateThumbVFPPredicate(MI); 777 return result; 778 } 779 } 780 781 MI.clear(); 782 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI); 783 if (result != MCDisassembler::Fail) { 784 Size = 4; 785 return result; 786 } 787 788 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 789 MI.clear(); 790 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 791 this, STI); 792 if (result != MCDisassembler::Fail) { 793 Size = 4; 794 Check(result, AddThumbPredicate(MI)); 795 return result; 796 } 797 } 798 799 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 800 MI.clear(); 801 uint32_t NEONLdStInsn = insn32; 802 NEONLdStInsn &= 0xF0FFFFFF; 803 NEONLdStInsn |= 0x04000000; 804 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 805 Address, this, STI); 806 if (result != MCDisassembler::Fail) { 807 Size = 4; 808 Check(result, AddThumbPredicate(MI)); 809 return result; 810 } 811 } 812 813 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 814 MI.clear(); 815 uint32_t NEONDataInsn = insn32; 816 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 817 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 818 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 819 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 820 Address, this, STI); 821 if (result != MCDisassembler::Fail) { 822 Size = 4; 823 Check(result, AddThumbPredicate(MI)); 824 return result; 825 } 826 } 827 828 MI.clear(); 829 uint32_t NEONv8Insn = insn32; 830 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 831 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 832 this, STI); 833 if (result != MCDisassembler::Fail) { 834 Size = 4; 835 return result; 836 } 837 838 MI.clear(); 839 Size = 0; 840 return MCDisassembler::Fail; 841} 842 843 844extern "C" void LLVMInitializeARMDisassembler() { 845 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 846 createARMDisassembler); 847 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 848 createThumbDisassembler); 849} 850 851static const uint16_t GPRDecoderTable[] = { 852 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 853 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 854 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 855 ARM::R12, ARM::SP, ARM::LR, ARM::PC 856}; 857 858static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 859 uint64_t Address, const void *Decoder) { 860 if (RegNo > 15) 861 return MCDisassembler::Fail; 862 863 unsigned Register = GPRDecoderTable[RegNo]; 864 Inst.addOperand(MCOperand::CreateReg(Register)); 865 return MCDisassembler::Success; 866} 867 868static DecodeStatus 869DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 870 uint64_t Address, const void *Decoder) { 871 DecodeStatus S = MCDisassembler::Success; 872 873 if (RegNo == 15) 874 S = MCDisassembler::SoftFail; 875 876 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 877 878 return S; 879} 880 881static DecodeStatus 882DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 883 uint64_t Address, const void *Decoder) { 884 DecodeStatus S = MCDisassembler::Success; 885 886 if (RegNo == 15) 887 { 888 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 889 return MCDisassembler::Success; 890 } 891 892 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 893 return S; 894} 895 896static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 897 uint64_t Address, const void *Decoder) { 898 if (RegNo > 7) 899 return MCDisassembler::Fail; 900 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 901} 902 903static const uint16_t GPRPairDecoderTable[] = { 904 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 905 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 906}; 907 908static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 909 uint64_t Address, const void *Decoder) { 910 DecodeStatus S = MCDisassembler::Success; 911 912 if (RegNo > 13) 913 return MCDisassembler::Fail; 914 915 if ((RegNo & 1) || RegNo == 0xe) 916 S = MCDisassembler::SoftFail; 917 918 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 919 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 920 return S; 921} 922 923static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 924 uint64_t Address, const void *Decoder) { 925 unsigned Register = 0; 926 switch (RegNo) { 927 case 0: 928 Register = ARM::R0; 929 break; 930 case 1: 931 Register = ARM::R1; 932 break; 933 case 2: 934 Register = ARM::R2; 935 break; 936 case 3: 937 Register = ARM::R3; 938 break; 939 case 9: 940 Register = ARM::R9; 941 break; 942 case 12: 943 Register = ARM::R12; 944 break; 945 default: 946 return MCDisassembler::Fail; 947 } 948 949 Inst.addOperand(MCOperand::CreateReg(Register)); 950 return MCDisassembler::Success; 951} 952 953static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 954 uint64_t Address, const void *Decoder) { 955 DecodeStatus S = MCDisassembler::Success; 956 if (RegNo == 13 || RegNo == 15) 957 S = MCDisassembler::SoftFail; 958 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 959 return S; 960} 961 962static const uint16_t SPRDecoderTable[] = { 963 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 964 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 965 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 966 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 967 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 968 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 969 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 970 ARM::S28, ARM::S29, ARM::S30, ARM::S31 971}; 972 973static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 974 uint64_t Address, const void *Decoder) { 975 if (RegNo > 31) 976 return MCDisassembler::Fail; 977 978 unsigned Register = SPRDecoderTable[RegNo]; 979 Inst.addOperand(MCOperand::CreateReg(Register)); 980 return MCDisassembler::Success; 981} 982 983static const uint16_t DPRDecoderTable[] = { 984 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 985 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 986 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 987 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 988 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 989 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 990 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 991 ARM::D28, ARM::D29, ARM::D30, ARM::D31 992}; 993 994static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 995 uint64_t Address, const void *Decoder) { 996 if (RegNo > 31) 997 return MCDisassembler::Fail; 998 999 unsigned Register = DPRDecoderTable[RegNo]; 1000 Inst.addOperand(MCOperand::CreateReg(Register)); 1001 return MCDisassembler::Success; 1002} 1003 1004static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1005 uint64_t Address, const void *Decoder) { 1006 if (RegNo > 7) 1007 return MCDisassembler::Fail; 1008 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1009} 1010 1011static DecodeStatus 1012DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1013 uint64_t Address, const void *Decoder) { 1014 if (RegNo > 15) 1015 return MCDisassembler::Fail; 1016 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1017} 1018 1019static const uint16_t QPRDecoderTable[] = { 1020 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1021 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1022 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1023 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1024}; 1025 1026 1027static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1028 uint64_t Address, const void *Decoder) { 1029 if (RegNo > 31 || (RegNo & 1) != 0) 1030 return MCDisassembler::Fail; 1031 RegNo >>= 1; 1032 1033 unsigned Register = QPRDecoderTable[RegNo]; 1034 Inst.addOperand(MCOperand::CreateReg(Register)); 1035 return MCDisassembler::Success; 1036} 1037 1038static const uint16_t DPairDecoderTable[] = { 1039 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1040 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1041 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1042 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1043 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1044 ARM::Q15 1045}; 1046 1047static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1048 uint64_t Address, const void *Decoder) { 1049 if (RegNo > 30) 1050 return MCDisassembler::Fail; 1051 1052 unsigned Register = DPairDecoderTable[RegNo]; 1053 Inst.addOperand(MCOperand::CreateReg(Register)); 1054 return MCDisassembler::Success; 1055} 1056 1057static const uint16_t DPairSpacedDecoderTable[] = { 1058 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1059 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1060 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1061 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1062 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1063 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1064 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1065 ARM::D28_D30, ARM::D29_D31 1066}; 1067 1068static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1069 unsigned RegNo, 1070 uint64_t Address, 1071 const void *Decoder) { 1072 if (RegNo > 29) 1073 return MCDisassembler::Fail; 1074 1075 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1076 Inst.addOperand(MCOperand::CreateReg(Register)); 1077 return MCDisassembler::Success; 1078} 1079 1080static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1081 uint64_t Address, const void *Decoder) { 1082 if (Val == 0xF) return MCDisassembler::Fail; 1083 // AL predicate is not allowed on Thumb1 branches. 1084 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1085 return MCDisassembler::Fail; 1086 Inst.addOperand(MCOperand::CreateImm(Val)); 1087 if (Val == ARMCC::AL) { 1088 Inst.addOperand(MCOperand::CreateReg(0)); 1089 } else 1090 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1091 return MCDisassembler::Success; 1092} 1093 1094static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1095 uint64_t Address, const void *Decoder) { 1096 if (Val) 1097 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1098 else 1099 Inst.addOperand(MCOperand::CreateReg(0)); 1100 return MCDisassembler::Success; 1101} 1102 1103static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1104 uint64_t Address, const void *Decoder) { 1105 uint32_t imm = Val & 0xFF; 1106 uint32_t rot = (Val & 0xF00) >> 7; 1107 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1108 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1109 return MCDisassembler::Success; 1110} 1111 1112static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1113 uint64_t Address, const void *Decoder) { 1114 DecodeStatus S = MCDisassembler::Success; 1115 1116 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1117 unsigned type = fieldFromInstruction(Val, 5, 2); 1118 unsigned imm = fieldFromInstruction(Val, 7, 5); 1119 1120 // Register-immediate 1121 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1122 return MCDisassembler::Fail; 1123 1124 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1125 switch (type) { 1126 case 0: 1127 Shift = ARM_AM::lsl; 1128 break; 1129 case 1: 1130 Shift = ARM_AM::lsr; 1131 break; 1132 case 2: 1133 Shift = ARM_AM::asr; 1134 break; 1135 case 3: 1136 Shift = ARM_AM::ror; 1137 break; 1138 } 1139 1140 if (Shift == ARM_AM::ror && imm == 0) 1141 Shift = ARM_AM::rrx; 1142 1143 unsigned Op = Shift | (imm << 3); 1144 Inst.addOperand(MCOperand::CreateImm(Op)); 1145 1146 return S; 1147} 1148 1149static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1150 uint64_t Address, const void *Decoder) { 1151 DecodeStatus S = MCDisassembler::Success; 1152 1153 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1154 unsigned type = fieldFromInstruction(Val, 5, 2); 1155 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1156 1157 // Register-register 1158 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1159 return MCDisassembler::Fail; 1160 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1161 return MCDisassembler::Fail; 1162 1163 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1164 switch (type) { 1165 case 0: 1166 Shift = ARM_AM::lsl; 1167 break; 1168 case 1: 1169 Shift = ARM_AM::lsr; 1170 break; 1171 case 2: 1172 Shift = ARM_AM::asr; 1173 break; 1174 case 3: 1175 Shift = ARM_AM::ror; 1176 break; 1177 } 1178 1179 Inst.addOperand(MCOperand::CreateImm(Shift)); 1180 1181 return S; 1182} 1183 1184static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1185 uint64_t Address, const void *Decoder) { 1186 DecodeStatus S = MCDisassembler::Success; 1187 1188 bool writebackLoad = false; 1189 unsigned writebackReg = 0; 1190 switch (Inst.getOpcode()) { 1191 default: 1192 break; 1193 case ARM::LDMIA_UPD: 1194 case ARM::LDMDB_UPD: 1195 case ARM::LDMIB_UPD: 1196 case ARM::LDMDA_UPD: 1197 case ARM::t2LDMIA_UPD: 1198 case ARM::t2LDMDB_UPD: 1199 writebackLoad = true; 1200 writebackReg = Inst.getOperand(0).getReg(); 1201 break; 1202 } 1203 1204 // Empty register lists are not allowed. 1205 if (Val == 0) return MCDisassembler::Fail; 1206 for (unsigned i = 0; i < 16; ++i) { 1207 if (Val & (1 << i)) { 1208 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1209 return MCDisassembler::Fail; 1210 // Writeback not allowed if Rn is in the target list. 1211 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1212 Check(S, MCDisassembler::SoftFail); 1213 } 1214 } 1215 1216 return S; 1217} 1218 1219static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1220 uint64_t Address, const void *Decoder) { 1221 DecodeStatus S = MCDisassembler::Success; 1222 1223 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1224 unsigned regs = fieldFromInstruction(Val, 0, 8); 1225 1226 // In case of unpredictable encoding, tweak the operands. 1227 if (regs == 0 || (Vd + regs) > 32) { 1228 regs = Vd + regs > 32 ? 32 - Vd : regs; 1229 regs = std::max( 1u, regs); 1230 S = MCDisassembler::SoftFail; 1231 } 1232 1233 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1234 return MCDisassembler::Fail; 1235 for (unsigned i = 0; i < (regs - 1); ++i) { 1236 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1237 return MCDisassembler::Fail; 1238 } 1239 1240 return S; 1241} 1242 1243static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1244 uint64_t Address, const void *Decoder) { 1245 DecodeStatus S = MCDisassembler::Success; 1246 1247 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1248 unsigned regs = fieldFromInstruction(Val, 1, 7); 1249 1250 // In case of unpredictable encoding, tweak the operands. 1251 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1252 regs = Vd + regs > 32 ? 32 - Vd : regs; 1253 regs = std::max( 1u, regs); 1254 regs = std::min(16u, regs); 1255 S = MCDisassembler::SoftFail; 1256 } 1257 1258 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1259 return MCDisassembler::Fail; 1260 for (unsigned i = 0; i < (regs - 1); ++i) { 1261 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1262 return MCDisassembler::Fail; 1263 } 1264 1265 return S; 1266} 1267 1268static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1269 uint64_t Address, const void *Decoder) { 1270 // This operand encodes a mask of contiguous zeros between a specified MSB 1271 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1272 // the mask of all bits LSB-and-lower, and then xor them to create 1273 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1274 // create the final mask. 1275 unsigned msb = fieldFromInstruction(Val, 5, 5); 1276 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1277 1278 DecodeStatus S = MCDisassembler::Success; 1279 if (lsb > msb) { 1280 Check(S, MCDisassembler::SoftFail); 1281 // The check above will cause the warning for the "potentially undefined 1282 // instruction encoding" but we can't build a bad MCOperand value here 1283 // with a lsb > msb or else printing the MCInst will cause a crash. 1284 lsb = msb; 1285 } 1286 1287 uint32_t msb_mask = 0xFFFFFFFF; 1288 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1289 uint32_t lsb_mask = (1U << lsb) - 1; 1290 1291 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1292 return S; 1293} 1294 1295static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1296 uint64_t Address, const void *Decoder) { 1297 DecodeStatus S = MCDisassembler::Success; 1298 1299 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1300 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1301 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1302 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1303 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1304 unsigned U = fieldFromInstruction(Insn, 23, 1); 1305 1306 switch (Inst.getOpcode()) { 1307 case ARM::LDC_OFFSET: 1308 case ARM::LDC_PRE: 1309 case ARM::LDC_POST: 1310 case ARM::LDC_OPTION: 1311 case ARM::LDCL_OFFSET: 1312 case ARM::LDCL_PRE: 1313 case ARM::LDCL_POST: 1314 case ARM::LDCL_OPTION: 1315 case ARM::STC_OFFSET: 1316 case ARM::STC_PRE: 1317 case ARM::STC_POST: 1318 case ARM::STC_OPTION: 1319 case ARM::STCL_OFFSET: 1320 case ARM::STCL_PRE: 1321 case ARM::STCL_POST: 1322 case ARM::STCL_OPTION: 1323 case ARM::t2LDC_OFFSET: 1324 case ARM::t2LDC_PRE: 1325 case ARM::t2LDC_POST: 1326 case ARM::t2LDC_OPTION: 1327 case ARM::t2LDCL_OFFSET: 1328 case ARM::t2LDCL_PRE: 1329 case ARM::t2LDCL_POST: 1330 case ARM::t2LDCL_OPTION: 1331 case ARM::t2STC_OFFSET: 1332 case ARM::t2STC_PRE: 1333 case ARM::t2STC_POST: 1334 case ARM::t2STC_OPTION: 1335 case ARM::t2STCL_OFFSET: 1336 case ARM::t2STCL_PRE: 1337 case ARM::t2STCL_POST: 1338 case ARM::t2STCL_OPTION: 1339 if (coproc == 0xA || coproc == 0xB) 1340 return MCDisassembler::Fail; 1341 break; 1342 default: 1343 break; 1344 } 1345 1346 Inst.addOperand(MCOperand::CreateImm(coproc)); 1347 Inst.addOperand(MCOperand::CreateImm(CRd)); 1348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1349 return MCDisassembler::Fail; 1350 1351 switch (Inst.getOpcode()) { 1352 case ARM::t2LDC2_OFFSET: 1353 case ARM::t2LDC2L_OFFSET: 1354 case ARM::t2LDC2_PRE: 1355 case ARM::t2LDC2L_PRE: 1356 case ARM::t2STC2_OFFSET: 1357 case ARM::t2STC2L_OFFSET: 1358 case ARM::t2STC2_PRE: 1359 case ARM::t2STC2L_PRE: 1360 case ARM::LDC2_OFFSET: 1361 case ARM::LDC2L_OFFSET: 1362 case ARM::LDC2_PRE: 1363 case ARM::LDC2L_PRE: 1364 case ARM::STC2_OFFSET: 1365 case ARM::STC2L_OFFSET: 1366 case ARM::STC2_PRE: 1367 case ARM::STC2L_PRE: 1368 case ARM::t2LDC_OFFSET: 1369 case ARM::t2LDCL_OFFSET: 1370 case ARM::t2LDC_PRE: 1371 case ARM::t2LDCL_PRE: 1372 case ARM::t2STC_OFFSET: 1373 case ARM::t2STCL_OFFSET: 1374 case ARM::t2STC_PRE: 1375 case ARM::t2STCL_PRE: 1376 case ARM::LDC_OFFSET: 1377 case ARM::LDCL_OFFSET: 1378 case ARM::LDC_PRE: 1379 case ARM::LDCL_PRE: 1380 case ARM::STC_OFFSET: 1381 case ARM::STCL_OFFSET: 1382 case ARM::STC_PRE: 1383 case ARM::STCL_PRE: 1384 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1385 Inst.addOperand(MCOperand::CreateImm(imm)); 1386 break; 1387 case ARM::t2LDC2_POST: 1388 case ARM::t2LDC2L_POST: 1389 case ARM::t2STC2_POST: 1390 case ARM::t2STC2L_POST: 1391 case ARM::LDC2_POST: 1392 case ARM::LDC2L_POST: 1393 case ARM::STC2_POST: 1394 case ARM::STC2L_POST: 1395 case ARM::t2LDC_POST: 1396 case ARM::t2LDCL_POST: 1397 case ARM::t2STC_POST: 1398 case ARM::t2STCL_POST: 1399 case ARM::LDC_POST: 1400 case ARM::LDCL_POST: 1401 case ARM::STC_POST: 1402 case ARM::STCL_POST: 1403 imm |= U << 8; 1404 // fall through. 1405 default: 1406 // The 'option' variant doesn't encode 'U' in the immediate since 1407 // the immediate is unsigned [0,255]. 1408 Inst.addOperand(MCOperand::CreateImm(imm)); 1409 break; 1410 } 1411 1412 switch (Inst.getOpcode()) { 1413 case ARM::LDC_OFFSET: 1414 case ARM::LDC_PRE: 1415 case ARM::LDC_POST: 1416 case ARM::LDC_OPTION: 1417 case ARM::LDCL_OFFSET: 1418 case ARM::LDCL_PRE: 1419 case ARM::LDCL_POST: 1420 case ARM::LDCL_OPTION: 1421 case ARM::STC_OFFSET: 1422 case ARM::STC_PRE: 1423 case ARM::STC_POST: 1424 case ARM::STC_OPTION: 1425 case ARM::STCL_OFFSET: 1426 case ARM::STCL_PRE: 1427 case ARM::STCL_POST: 1428 case ARM::STCL_OPTION: 1429 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1430 return MCDisassembler::Fail; 1431 break; 1432 default: 1433 break; 1434 } 1435 1436 return S; 1437} 1438 1439static DecodeStatus 1440DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1441 uint64_t Address, const void *Decoder) { 1442 DecodeStatus S = MCDisassembler::Success; 1443 1444 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1445 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1446 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1447 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1448 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1449 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1450 unsigned P = fieldFromInstruction(Insn, 24, 1); 1451 unsigned W = fieldFromInstruction(Insn, 21, 1); 1452 1453 // On stores, the writeback operand precedes Rt. 1454 switch (Inst.getOpcode()) { 1455 case ARM::STR_POST_IMM: 1456 case ARM::STR_POST_REG: 1457 case ARM::STRB_POST_IMM: 1458 case ARM::STRB_POST_REG: 1459 case ARM::STRT_POST_REG: 1460 case ARM::STRT_POST_IMM: 1461 case ARM::STRBT_POST_REG: 1462 case ARM::STRBT_POST_IMM: 1463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1464 return MCDisassembler::Fail; 1465 break; 1466 default: 1467 break; 1468 } 1469 1470 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1471 return MCDisassembler::Fail; 1472 1473 // On loads, the writeback operand comes after Rt. 1474 switch (Inst.getOpcode()) { 1475 case ARM::LDR_POST_IMM: 1476 case ARM::LDR_POST_REG: 1477 case ARM::LDRB_POST_IMM: 1478 case ARM::LDRB_POST_REG: 1479 case ARM::LDRBT_POST_REG: 1480 case ARM::LDRBT_POST_IMM: 1481 case ARM::LDRT_POST_REG: 1482 case ARM::LDRT_POST_IMM: 1483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1484 return MCDisassembler::Fail; 1485 break; 1486 default: 1487 break; 1488 } 1489 1490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1491 return MCDisassembler::Fail; 1492 1493 ARM_AM::AddrOpc Op = ARM_AM::add; 1494 if (!fieldFromInstruction(Insn, 23, 1)) 1495 Op = ARM_AM::sub; 1496 1497 bool writeback = (P == 0) || (W == 1); 1498 unsigned idx_mode = 0; 1499 if (P && writeback) 1500 idx_mode = ARMII::IndexModePre; 1501 else if (!P && writeback) 1502 idx_mode = ARMII::IndexModePost; 1503 1504 if (writeback && (Rn == 15 || Rn == Rt)) 1505 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1506 1507 if (reg) { 1508 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1509 return MCDisassembler::Fail; 1510 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1511 switch( fieldFromInstruction(Insn, 5, 2)) { 1512 case 0: 1513 Opc = ARM_AM::lsl; 1514 break; 1515 case 1: 1516 Opc = ARM_AM::lsr; 1517 break; 1518 case 2: 1519 Opc = ARM_AM::asr; 1520 break; 1521 case 3: 1522 Opc = ARM_AM::ror; 1523 break; 1524 default: 1525 return MCDisassembler::Fail; 1526 } 1527 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1528 if (Opc == ARM_AM::ror && amt == 0) 1529 Opc = ARM_AM::rrx; 1530 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1531 1532 Inst.addOperand(MCOperand::CreateImm(imm)); 1533 } else { 1534 Inst.addOperand(MCOperand::CreateReg(0)); 1535 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1536 Inst.addOperand(MCOperand::CreateImm(tmp)); 1537 } 1538 1539 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1540 return MCDisassembler::Fail; 1541 1542 return S; 1543} 1544 1545static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1546 uint64_t Address, const void *Decoder) { 1547 DecodeStatus S = MCDisassembler::Success; 1548 1549 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1550 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1551 unsigned type = fieldFromInstruction(Val, 5, 2); 1552 unsigned imm = fieldFromInstruction(Val, 7, 5); 1553 unsigned U = fieldFromInstruction(Val, 12, 1); 1554 1555 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1556 switch (type) { 1557 case 0: 1558 ShOp = ARM_AM::lsl; 1559 break; 1560 case 1: 1561 ShOp = ARM_AM::lsr; 1562 break; 1563 case 2: 1564 ShOp = ARM_AM::asr; 1565 break; 1566 case 3: 1567 ShOp = ARM_AM::ror; 1568 break; 1569 } 1570 1571 if (ShOp == ARM_AM::ror && imm == 0) 1572 ShOp = ARM_AM::rrx; 1573 1574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1575 return MCDisassembler::Fail; 1576 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1577 return MCDisassembler::Fail; 1578 unsigned shift; 1579 if (U) 1580 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1581 else 1582 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1583 Inst.addOperand(MCOperand::CreateImm(shift)); 1584 1585 return S; 1586} 1587 1588static DecodeStatus 1589DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1590 uint64_t Address, const void *Decoder) { 1591 DecodeStatus S = MCDisassembler::Success; 1592 1593 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1594 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1595 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1596 unsigned type = fieldFromInstruction(Insn, 22, 1); 1597 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1598 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1599 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1600 unsigned W = fieldFromInstruction(Insn, 21, 1); 1601 unsigned P = fieldFromInstruction(Insn, 24, 1); 1602 unsigned Rt2 = Rt + 1; 1603 1604 bool writeback = (W == 1) | (P == 0); 1605 1606 // For {LD,ST}RD, Rt must be even, else undefined. 1607 switch (Inst.getOpcode()) { 1608 case ARM::STRD: 1609 case ARM::STRD_PRE: 1610 case ARM::STRD_POST: 1611 case ARM::LDRD: 1612 case ARM::LDRD_PRE: 1613 case ARM::LDRD_POST: 1614 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1615 break; 1616 default: 1617 break; 1618 } 1619 switch (Inst.getOpcode()) { 1620 case ARM::STRD: 1621 case ARM::STRD_PRE: 1622 case ARM::STRD_POST: 1623 if (P == 0 && W == 1) 1624 S = MCDisassembler::SoftFail; 1625 1626 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1627 S = MCDisassembler::SoftFail; 1628 if (type && Rm == 15) 1629 S = MCDisassembler::SoftFail; 1630 if (Rt2 == 15) 1631 S = MCDisassembler::SoftFail; 1632 if (!type && fieldFromInstruction(Insn, 8, 4)) 1633 S = MCDisassembler::SoftFail; 1634 break; 1635 case ARM::STRH: 1636 case ARM::STRH_PRE: 1637 case ARM::STRH_POST: 1638 if (Rt == 15) 1639 S = MCDisassembler::SoftFail; 1640 if (writeback && (Rn == 15 || Rn == Rt)) 1641 S = MCDisassembler::SoftFail; 1642 if (!type && Rm == 15) 1643 S = MCDisassembler::SoftFail; 1644 break; 1645 case ARM::LDRD: 1646 case ARM::LDRD_PRE: 1647 case ARM::LDRD_POST: 1648 if (type && Rn == 15){ 1649 if (Rt2 == 15) 1650 S = MCDisassembler::SoftFail; 1651 break; 1652 } 1653 if (P == 0 && W == 1) 1654 S = MCDisassembler::SoftFail; 1655 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1656 S = MCDisassembler::SoftFail; 1657 if (!type && writeback && Rn == 15) 1658 S = MCDisassembler::SoftFail; 1659 if (writeback && (Rn == Rt || Rn == Rt2)) 1660 S = MCDisassembler::SoftFail; 1661 break; 1662 case ARM::LDRH: 1663 case ARM::LDRH_PRE: 1664 case ARM::LDRH_POST: 1665 if (type && Rn == 15){ 1666 if (Rt == 15) 1667 S = MCDisassembler::SoftFail; 1668 break; 1669 } 1670 if (Rt == 15) 1671 S = MCDisassembler::SoftFail; 1672 if (!type && Rm == 15) 1673 S = MCDisassembler::SoftFail; 1674 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1675 S = MCDisassembler::SoftFail; 1676 break; 1677 case ARM::LDRSH: 1678 case ARM::LDRSH_PRE: 1679 case ARM::LDRSH_POST: 1680 case ARM::LDRSB: 1681 case ARM::LDRSB_PRE: 1682 case ARM::LDRSB_POST: 1683 if (type && Rn == 15){ 1684 if (Rt == 15) 1685 S = MCDisassembler::SoftFail; 1686 break; 1687 } 1688 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1689 S = MCDisassembler::SoftFail; 1690 if (!type && (Rt == 15 || Rm == 15)) 1691 S = MCDisassembler::SoftFail; 1692 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1693 S = MCDisassembler::SoftFail; 1694 break; 1695 default: 1696 break; 1697 } 1698 1699 if (writeback) { // Writeback 1700 if (P) 1701 U |= ARMII::IndexModePre << 9; 1702 else 1703 U |= ARMII::IndexModePost << 9; 1704 1705 // On stores, the writeback operand precedes Rt. 1706 switch (Inst.getOpcode()) { 1707 case ARM::STRD: 1708 case ARM::STRD_PRE: 1709 case ARM::STRD_POST: 1710 case ARM::STRH: 1711 case ARM::STRH_PRE: 1712 case ARM::STRH_POST: 1713 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1714 return MCDisassembler::Fail; 1715 break; 1716 default: 1717 break; 1718 } 1719 } 1720 1721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1722 return MCDisassembler::Fail; 1723 switch (Inst.getOpcode()) { 1724 case ARM::STRD: 1725 case ARM::STRD_PRE: 1726 case ARM::STRD_POST: 1727 case ARM::LDRD: 1728 case ARM::LDRD_PRE: 1729 case ARM::LDRD_POST: 1730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1731 return MCDisassembler::Fail; 1732 break; 1733 default: 1734 break; 1735 } 1736 1737 if (writeback) { 1738 // On loads, the writeback operand comes after Rt. 1739 switch (Inst.getOpcode()) { 1740 case ARM::LDRD: 1741 case ARM::LDRD_PRE: 1742 case ARM::LDRD_POST: 1743 case ARM::LDRH: 1744 case ARM::LDRH_PRE: 1745 case ARM::LDRH_POST: 1746 case ARM::LDRSH: 1747 case ARM::LDRSH_PRE: 1748 case ARM::LDRSH_POST: 1749 case ARM::LDRSB: 1750 case ARM::LDRSB_PRE: 1751 case ARM::LDRSB_POST: 1752 case ARM::LDRHTr: 1753 case ARM::LDRSBTr: 1754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1755 return MCDisassembler::Fail; 1756 break; 1757 default: 1758 break; 1759 } 1760 } 1761 1762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1763 return MCDisassembler::Fail; 1764 1765 if (type) { 1766 Inst.addOperand(MCOperand::CreateReg(0)); 1767 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1768 } else { 1769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1770 return MCDisassembler::Fail; 1771 Inst.addOperand(MCOperand::CreateImm(U)); 1772 } 1773 1774 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1775 return MCDisassembler::Fail; 1776 1777 return S; 1778} 1779 1780static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1781 uint64_t Address, const void *Decoder) { 1782 DecodeStatus S = MCDisassembler::Success; 1783 1784 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1785 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1786 1787 switch (mode) { 1788 case 0: 1789 mode = ARM_AM::da; 1790 break; 1791 case 1: 1792 mode = ARM_AM::ia; 1793 break; 1794 case 2: 1795 mode = ARM_AM::db; 1796 break; 1797 case 3: 1798 mode = ARM_AM::ib; 1799 break; 1800 } 1801 1802 Inst.addOperand(MCOperand::CreateImm(mode)); 1803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1804 return MCDisassembler::Fail; 1805 1806 return S; 1807} 1808 1809static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1810 uint64_t Address, const void *Decoder) { 1811 DecodeStatus S = MCDisassembler::Success; 1812 1813 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1814 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1815 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1816 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1817 1818 if (pred == 0xF) 1819 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1820 1821 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1822 return MCDisassembler::Fail; 1823 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1824 return MCDisassembler::Fail; 1825 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1826 return MCDisassembler::Fail; 1827 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1828 return MCDisassembler::Fail; 1829 return S; 1830} 1831 1832static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1833 unsigned Insn, 1834 uint64_t Address, const void *Decoder) { 1835 DecodeStatus S = MCDisassembler::Success; 1836 1837 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1838 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1839 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1840 1841 if (pred == 0xF) { 1842 // Ambiguous with RFE and SRS 1843 switch (Inst.getOpcode()) { 1844 case ARM::LDMDA: 1845 Inst.setOpcode(ARM::RFEDA); 1846 break; 1847 case ARM::LDMDA_UPD: 1848 Inst.setOpcode(ARM::RFEDA_UPD); 1849 break; 1850 case ARM::LDMDB: 1851 Inst.setOpcode(ARM::RFEDB); 1852 break; 1853 case ARM::LDMDB_UPD: 1854 Inst.setOpcode(ARM::RFEDB_UPD); 1855 break; 1856 case ARM::LDMIA: 1857 Inst.setOpcode(ARM::RFEIA); 1858 break; 1859 case ARM::LDMIA_UPD: 1860 Inst.setOpcode(ARM::RFEIA_UPD); 1861 break; 1862 case ARM::LDMIB: 1863 Inst.setOpcode(ARM::RFEIB); 1864 break; 1865 case ARM::LDMIB_UPD: 1866 Inst.setOpcode(ARM::RFEIB_UPD); 1867 break; 1868 case ARM::STMDA: 1869 Inst.setOpcode(ARM::SRSDA); 1870 break; 1871 case ARM::STMDA_UPD: 1872 Inst.setOpcode(ARM::SRSDA_UPD); 1873 break; 1874 case ARM::STMDB: 1875 Inst.setOpcode(ARM::SRSDB); 1876 break; 1877 case ARM::STMDB_UPD: 1878 Inst.setOpcode(ARM::SRSDB_UPD); 1879 break; 1880 case ARM::STMIA: 1881 Inst.setOpcode(ARM::SRSIA); 1882 break; 1883 case ARM::STMIA_UPD: 1884 Inst.setOpcode(ARM::SRSIA_UPD); 1885 break; 1886 case ARM::STMIB: 1887 Inst.setOpcode(ARM::SRSIB); 1888 break; 1889 case ARM::STMIB_UPD: 1890 Inst.setOpcode(ARM::SRSIB_UPD); 1891 break; 1892 default: 1893 return MCDisassembler::Fail; 1894 } 1895 1896 // For stores (which become SRS's, the only operand is the mode. 1897 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1898 // Check SRS encoding constraints 1899 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1900 fieldFromInstruction(Insn, 20, 1) == 0)) 1901 return MCDisassembler::Fail; 1902 1903 Inst.addOperand( 1904 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1905 return S; 1906 } 1907 1908 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1909 } 1910 1911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1912 return MCDisassembler::Fail; 1913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1914 return MCDisassembler::Fail; // Tied 1915 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1916 return MCDisassembler::Fail; 1917 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1918 return MCDisassembler::Fail; 1919 1920 return S; 1921} 1922 1923static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1924 uint64_t Address, const void *Decoder) { 1925 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1926 unsigned M = fieldFromInstruction(Insn, 17, 1); 1927 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1928 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1929 1930 DecodeStatus S = MCDisassembler::Success; 1931 1932 // This decoder is called from multiple location that do not check 1933 // the full encoding is valid before they do. 1934 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1935 fieldFromInstruction(Insn, 16, 1) != 0 || 1936 fieldFromInstruction(Insn, 20, 8) != 0x10) 1937 return MCDisassembler::Fail; 1938 1939 // imod == '01' --> UNPREDICTABLE 1940 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1941 // return failure here. The '01' imod value is unprintable, so there's 1942 // nothing useful we could do even if we returned UNPREDICTABLE. 1943 1944 if (imod == 1) return MCDisassembler::Fail; 1945 1946 if (imod && M) { 1947 Inst.setOpcode(ARM::CPS3p); 1948 Inst.addOperand(MCOperand::CreateImm(imod)); 1949 Inst.addOperand(MCOperand::CreateImm(iflags)); 1950 Inst.addOperand(MCOperand::CreateImm(mode)); 1951 } else if (imod && !M) { 1952 Inst.setOpcode(ARM::CPS2p); 1953 Inst.addOperand(MCOperand::CreateImm(imod)); 1954 Inst.addOperand(MCOperand::CreateImm(iflags)); 1955 if (mode) S = MCDisassembler::SoftFail; 1956 } else if (!imod && M) { 1957 Inst.setOpcode(ARM::CPS1p); 1958 Inst.addOperand(MCOperand::CreateImm(mode)); 1959 if (iflags) S = MCDisassembler::SoftFail; 1960 } else { 1961 // imod == '00' && M == '0' --> UNPREDICTABLE 1962 Inst.setOpcode(ARM::CPS1p); 1963 Inst.addOperand(MCOperand::CreateImm(mode)); 1964 S = MCDisassembler::SoftFail; 1965 } 1966 1967 return S; 1968} 1969 1970static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1971 uint64_t Address, const void *Decoder) { 1972 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1973 unsigned M = fieldFromInstruction(Insn, 8, 1); 1974 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1975 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1976 1977 DecodeStatus S = MCDisassembler::Success; 1978 1979 // imod == '01' --> UNPREDICTABLE 1980 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1981 // return failure here. The '01' imod value is unprintable, so there's 1982 // nothing useful we could do even if we returned UNPREDICTABLE. 1983 1984 if (imod == 1) return MCDisassembler::Fail; 1985 1986 if (imod && M) { 1987 Inst.setOpcode(ARM::t2CPS3p); 1988 Inst.addOperand(MCOperand::CreateImm(imod)); 1989 Inst.addOperand(MCOperand::CreateImm(iflags)); 1990 Inst.addOperand(MCOperand::CreateImm(mode)); 1991 } else if (imod && !M) { 1992 Inst.setOpcode(ARM::t2CPS2p); 1993 Inst.addOperand(MCOperand::CreateImm(imod)); 1994 Inst.addOperand(MCOperand::CreateImm(iflags)); 1995 if (mode) S = MCDisassembler::SoftFail; 1996 } else if (!imod && M) { 1997 Inst.setOpcode(ARM::t2CPS1p); 1998 Inst.addOperand(MCOperand::CreateImm(mode)); 1999 if (iflags) S = MCDisassembler::SoftFail; 2000 } else { 2001 // imod == '00' && M == '0' --> this is a HINT instruction 2002 int imm = fieldFromInstruction(Insn, 0, 8); 2003 // HINT are defined only for immediate in [0..4] 2004 if(imm > 4) return MCDisassembler::Fail; 2005 Inst.setOpcode(ARM::t2HINT); 2006 Inst.addOperand(MCOperand::CreateImm(imm)); 2007 } 2008 2009 return S; 2010} 2011 2012static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2013 uint64_t Address, const void *Decoder) { 2014 DecodeStatus S = MCDisassembler::Success; 2015 2016 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2017 unsigned imm = 0; 2018 2019 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2020 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2021 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2022 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2023 2024 if (Inst.getOpcode() == ARM::t2MOVTi16) 2025 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2026 return MCDisassembler::Fail; 2027 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2028 return MCDisassembler::Fail; 2029 2030 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2031 Inst.addOperand(MCOperand::CreateImm(imm)); 2032 2033 return S; 2034} 2035 2036static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2037 uint64_t Address, const void *Decoder) { 2038 DecodeStatus S = MCDisassembler::Success; 2039 2040 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2041 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2042 unsigned imm = 0; 2043 2044 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2045 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2046 2047 if (Inst.getOpcode() == ARM::MOVTi16) 2048 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2049 return MCDisassembler::Fail; 2050 2051 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2052 return MCDisassembler::Fail; 2053 2054 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2055 Inst.addOperand(MCOperand::CreateImm(imm)); 2056 2057 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2058 return MCDisassembler::Fail; 2059 2060 return S; 2061} 2062 2063static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2064 uint64_t Address, const void *Decoder) { 2065 DecodeStatus S = MCDisassembler::Success; 2066 2067 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2068 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2069 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2070 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2071 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2072 2073 if (pred == 0xF) 2074 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2075 2076 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2077 return MCDisassembler::Fail; 2078 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2079 return MCDisassembler::Fail; 2080 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2081 return MCDisassembler::Fail; 2082 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2083 return MCDisassembler::Fail; 2084 2085 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2086 return MCDisassembler::Fail; 2087 2088 return S; 2089} 2090 2091static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2092 uint64_t Address, const void *Decoder) { 2093 DecodeStatus S = MCDisassembler::Success; 2094 2095 unsigned add = fieldFromInstruction(Val, 12, 1); 2096 unsigned imm = fieldFromInstruction(Val, 0, 12); 2097 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2098 2099 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2100 return MCDisassembler::Fail; 2101 2102 if (!add) imm *= -1; 2103 if (imm == 0 && !add) imm = INT32_MIN; 2104 Inst.addOperand(MCOperand::CreateImm(imm)); 2105 if (Rn == 15) 2106 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2107 2108 return S; 2109} 2110 2111static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2112 uint64_t Address, const void *Decoder) { 2113 DecodeStatus S = MCDisassembler::Success; 2114 2115 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2116 unsigned U = fieldFromInstruction(Val, 8, 1); 2117 unsigned imm = fieldFromInstruction(Val, 0, 8); 2118 2119 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2120 return MCDisassembler::Fail; 2121 2122 if (U) 2123 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2124 else 2125 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2126 2127 return S; 2128} 2129 2130static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2131 uint64_t Address, const void *Decoder) { 2132 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2133} 2134 2135static DecodeStatus 2136DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2137 uint64_t Address, const void *Decoder) { 2138 DecodeStatus Status = MCDisassembler::Success; 2139 2140 // Note the J1 and J2 values are from the encoded instruction. So here 2141 // change them to I1 and I2 values via as documented: 2142 // I1 = NOT(J1 EOR S); 2143 // I2 = NOT(J2 EOR S); 2144 // and build the imm32 with one trailing zero as documented: 2145 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2146 unsigned S = fieldFromInstruction(Insn, 26, 1); 2147 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2148 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2149 unsigned I1 = !(J1 ^ S); 2150 unsigned I2 = !(J2 ^ S); 2151 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2152 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2153 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2154 int imm32 = SignExtend32<25>(tmp << 1); 2155 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2156 true, 4, Inst, Decoder)) 2157 Inst.addOperand(MCOperand::CreateImm(imm32)); 2158 2159 return Status; 2160} 2161 2162static DecodeStatus 2163DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2164 uint64_t Address, const void *Decoder) { 2165 DecodeStatus S = MCDisassembler::Success; 2166 2167 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2168 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2169 2170 if (pred == 0xF) { 2171 Inst.setOpcode(ARM::BLXi); 2172 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2173 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2174 true, 4, Inst, Decoder)) 2175 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2176 return S; 2177 } 2178 2179 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2180 true, 4, Inst, Decoder)) 2181 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2182 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2183 return MCDisassembler::Fail; 2184 2185 return S; 2186} 2187 2188 2189static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2190 uint64_t Address, const void *Decoder) { 2191 DecodeStatus S = MCDisassembler::Success; 2192 2193 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2194 unsigned align = fieldFromInstruction(Val, 4, 2); 2195 2196 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2197 return MCDisassembler::Fail; 2198 if (!align) 2199 Inst.addOperand(MCOperand::CreateImm(0)); 2200 else 2201 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2202 2203 return S; 2204} 2205 2206static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2207 uint64_t Address, const void *Decoder) { 2208 DecodeStatus S = MCDisassembler::Success; 2209 2210 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2211 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2212 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2213 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2214 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2215 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2216 2217 // First output register 2218 switch (Inst.getOpcode()) { 2219 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2220 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2221 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2222 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2223 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2224 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2225 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2226 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2227 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2228 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2229 return MCDisassembler::Fail; 2230 break; 2231 case ARM::VLD2b16: 2232 case ARM::VLD2b32: 2233 case ARM::VLD2b8: 2234 case ARM::VLD2b16wb_fixed: 2235 case ARM::VLD2b16wb_register: 2236 case ARM::VLD2b32wb_fixed: 2237 case ARM::VLD2b32wb_register: 2238 case ARM::VLD2b8wb_fixed: 2239 case ARM::VLD2b8wb_register: 2240 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2241 return MCDisassembler::Fail; 2242 break; 2243 default: 2244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2245 return MCDisassembler::Fail; 2246 } 2247 2248 // Second output register 2249 switch (Inst.getOpcode()) { 2250 case ARM::VLD3d8: 2251 case ARM::VLD3d16: 2252 case ARM::VLD3d32: 2253 case ARM::VLD3d8_UPD: 2254 case ARM::VLD3d16_UPD: 2255 case ARM::VLD3d32_UPD: 2256 case ARM::VLD4d8: 2257 case ARM::VLD4d16: 2258 case ARM::VLD4d32: 2259 case ARM::VLD4d8_UPD: 2260 case ARM::VLD4d16_UPD: 2261 case ARM::VLD4d32_UPD: 2262 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2263 return MCDisassembler::Fail; 2264 break; 2265 case ARM::VLD3q8: 2266 case ARM::VLD3q16: 2267 case ARM::VLD3q32: 2268 case ARM::VLD3q8_UPD: 2269 case ARM::VLD3q16_UPD: 2270 case ARM::VLD3q32_UPD: 2271 case ARM::VLD4q8: 2272 case ARM::VLD4q16: 2273 case ARM::VLD4q32: 2274 case ARM::VLD4q8_UPD: 2275 case ARM::VLD4q16_UPD: 2276 case ARM::VLD4q32_UPD: 2277 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2278 return MCDisassembler::Fail; 2279 default: 2280 break; 2281 } 2282 2283 // Third output register 2284 switch(Inst.getOpcode()) { 2285 case ARM::VLD3d8: 2286 case ARM::VLD3d16: 2287 case ARM::VLD3d32: 2288 case ARM::VLD3d8_UPD: 2289 case ARM::VLD3d16_UPD: 2290 case ARM::VLD3d32_UPD: 2291 case ARM::VLD4d8: 2292 case ARM::VLD4d16: 2293 case ARM::VLD4d32: 2294 case ARM::VLD4d8_UPD: 2295 case ARM::VLD4d16_UPD: 2296 case ARM::VLD4d32_UPD: 2297 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2298 return MCDisassembler::Fail; 2299 break; 2300 case ARM::VLD3q8: 2301 case ARM::VLD3q16: 2302 case ARM::VLD3q32: 2303 case ARM::VLD3q8_UPD: 2304 case ARM::VLD3q16_UPD: 2305 case ARM::VLD3q32_UPD: 2306 case ARM::VLD4q8: 2307 case ARM::VLD4q16: 2308 case ARM::VLD4q32: 2309 case ARM::VLD4q8_UPD: 2310 case ARM::VLD4q16_UPD: 2311 case ARM::VLD4q32_UPD: 2312 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2313 return MCDisassembler::Fail; 2314 break; 2315 default: 2316 break; 2317 } 2318 2319 // Fourth output register 2320 switch (Inst.getOpcode()) { 2321 case ARM::VLD4d8: 2322 case ARM::VLD4d16: 2323 case ARM::VLD4d32: 2324 case ARM::VLD4d8_UPD: 2325 case ARM::VLD4d16_UPD: 2326 case ARM::VLD4d32_UPD: 2327 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2328 return MCDisassembler::Fail; 2329 break; 2330 case ARM::VLD4q8: 2331 case ARM::VLD4q16: 2332 case ARM::VLD4q32: 2333 case ARM::VLD4q8_UPD: 2334 case ARM::VLD4q16_UPD: 2335 case ARM::VLD4q32_UPD: 2336 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2337 return MCDisassembler::Fail; 2338 break; 2339 default: 2340 break; 2341 } 2342 2343 // Writeback operand 2344 switch (Inst.getOpcode()) { 2345 case ARM::VLD1d8wb_fixed: 2346 case ARM::VLD1d16wb_fixed: 2347 case ARM::VLD1d32wb_fixed: 2348 case ARM::VLD1d64wb_fixed: 2349 case ARM::VLD1d8wb_register: 2350 case ARM::VLD1d16wb_register: 2351 case ARM::VLD1d32wb_register: 2352 case ARM::VLD1d64wb_register: 2353 case ARM::VLD1q8wb_fixed: 2354 case ARM::VLD1q16wb_fixed: 2355 case ARM::VLD1q32wb_fixed: 2356 case ARM::VLD1q64wb_fixed: 2357 case ARM::VLD1q8wb_register: 2358 case ARM::VLD1q16wb_register: 2359 case ARM::VLD1q32wb_register: 2360 case ARM::VLD1q64wb_register: 2361 case ARM::VLD1d8Twb_fixed: 2362 case ARM::VLD1d8Twb_register: 2363 case ARM::VLD1d16Twb_fixed: 2364 case ARM::VLD1d16Twb_register: 2365 case ARM::VLD1d32Twb_fixed: 2366 case ARM::VLD1d32Twb_register: 2367 case ARM::VLD1d64Twb_fixed: 2368 case ARM::VLD1d64Twb_register: 2369 case ARM::VLD1d8Qwb_fixed: 2370 case ARM::VLD1d8Qwb_register: 2371 case ARM::VLD1d16Qwb_fixed: 2372 case ARM::VLD1d16Qwb_register: 2373 case ARM::VLD1d32Qwb_fixed: 2374 case ARM::VLD1d32Qwb_register: 2375 case ARM::VLD1d64Qwb_fixed: 2376 case ARM::VLD1d64Qwb_register: 2377 case ARM::VLD2d8wb_fixed: 2378 case ARM::VLD2d16wb_fixed: 2379 case ARM::VLD2d32wb_fixed: 2380 case ARM::VLD2q8wb_fixed: 2381 case ARM::VLD2q16wb_fixed: 2382 case ARM::VLD2q32wb_fixed: 2383 case ARM::VLD2d8wb_register: 2384 case ARM::VLD2d16wb_register: 2385 case ARM::VLD2d32wb_register: 2386 case ARM::VLD2q8wb_register: 2387 case ARM::VLD2q16wb_register: 2388 case ARM::VLD2q32wb_register: 2389 case ARM::VLD2b8wb_fixed: 2390 case ARM::VLD2b16wb_fixed: 2391 case ARM::VLD2b32wb_fixed: 2392 case ARM::VLD2b8wb_register: 2393 case ARM::VLD2b16wb_register: 2394 case ARM::VLD2b32wb_register: 2395 Inst.addOperand(MCOperand::CreateImm(0)); 2396 break; 2397 case ARM::VLD3d8_UPD: 2398 case ARM::VLD3d16_UPD: 2399 case ARM::VLD3d32_UPD: 2400 case ARM::VLD3q8_UPD: 2401 case ARM::VLD3q16_UPD: 2402 case ARM::VLD3q32_UPD: 2403 case ARM::VLD4d8_UPD: 2404 case ARM::VLD4d16_UPD: 2405 case ARM::VLD4d32_UPD: 2406 case ARM::VLD4q8_UPD: 2407 case ARM::VLD4q16_UPD: 2408 case ARM::VLD4q32_UPD: 2409 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2410 return MCDisassembler::Fail; 2411 break; 2412 default: 2413 break; 2414 } 2415 2416 // AddrMode6 Base (register+alignment) 2417 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2418 return MCDisassembler::Fail; 2419 2420 // AddrMode6 Offset (register) 2421 switch (Inst.getOpcode()) { 2422 default: 2423 // The below have been updated to have explicit am6offset split 2424 // between fixed and register offset. For those instructions not 2425 // yet updated, we need to add an additional reg0 operand for the 2426 // fixed variant. 2427 // 2428 // The fixed offset encodes as Rm == 0xd, so we check for that. 2429 if (Rm == 0xd) { 2430 Inst.addOperand(MCOperand::CreateReg(0)); 2431 break; 2432 } 2433 // Fall through to handle the register offset variant. 2434 case ARM::VLD1d8wb_fixed: 2435 case ARM::VLD1d16wb_fixed: 2436 case ARM::VLD1d32wb_fixed: 2437 case ARM::VLD1d64wb_fixed: 2438 case ARM::VLD1d8Twb_fixed: 2439 case ARM::VLD1d16Twb_fixed: 2440 case ARM::VLD1d32Twb_fixed: 2441 case ARM::VLD1d64Twb_fixed: 2442 case ARM::VLD1d8Qwb_fixed: 2443 case ARM::VLD1d16Qwb_fixed: 2444 case ARM::VLD1d32Qwb_fixed: 2445 case ARM::VLD1d64Qwb_fixed: 2446 case ARM::VLD1d8wb_register: 2447 case ARM::VLD1d16wb_register: 2448 case ARM::VLD1d32wb_register: 2449 case ARM::VLD1d64wb_register: 2450 case ARM::VLD1q8wb_fixed: 2451 case ARM::VLD1q16wb_fixed: 2452 case ARM::VLD1q32wb_fixed: 2453 case ARM::VLD1q64wb_fixed: 2454 case ARM::VLD1q8wb_register: 2455 case ARM::VLD1q16wb_register: 2456 case ARM::VLD1q32wb_register: 2457 case ARM::VLD1q64wb_register: 2458 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2459 // variant encodes Rm == 0xf. Anything else is a register offset post- 2460 // increment and we need to add the register operand to the instruction. 2461 if (Rm != 0xD && Rm != 0xF && 2462 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2463 return MCDisassembler::Fail; 2464 break; 2465 case ARM::VLD2d8wb_fixed: 2466 case ARM::VLD2d16wb_fixed: 2467 case ARM::VLD2d32wb_fixed: 2468 case ARM::VLD2b8wb_fixed: 2469 case ARM::VLD2b16wb_fixed: 2470 case ARM::VLD2b32wb_fixed: 2471 case ARM::VLD2q8wb_fixed: 2472 case ARM::VLD2q16wb_fixed: 2473 case ARM::VLD2q32wb_fixed: 2474 break; 2475 } 2476 2477 return S; 2478} 2479 2480static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2481 uint64_t Address, const void *Decoder) { 2482 unsigned type = fieldFromInstruction(Insn, 8, 4); 2483 unsigned align = fieldFromInstruction(Insn, 4, 2); 2484 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2485 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2486 if (type == 10 && align == 3) return MCDisassembler::Fail; 2487 2488 unsigned load = fieldFromInstruction(Insn, 21, 1); 2489 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2490 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2491} 2492 2493static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2494 uint64_t Address, const void *Decoder) { 2495 unsigned size = fieldFromInstruction(Insn, 6, 2); 2496 if (size == 3) return MCDisassembler::Fail; 2497 2498 unsigned type = fieldFromInstruction(Insn, 8, 4); 2499 unsigned align = fieldFromInstruction(Insn, 4, 2); 2500 if (type == 8 && align == 3) return MCDisassembler::Fail; 2501 if (type == 9 && align == 3) return MCDisassembler::Fail; 2502 2503 unsigned load = fieldFromInstruction(Insn, 21, 1); 2504 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2505 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2506} 2507 2508static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2509 uint64_t Address, const void *Decoder) { 2510 unsigned size = fieldFromInstruction(Insn, 6, 2); 2511 if (size == 3) return MCDisassembler::Fail; 2512 2513 unsigned align = fieldFromInstruction(Insn, 4, 2); 2514 if (align & 2) return MCDisassembler::Fail; 2515 2516 unsigned load = fieldFromInstruction(Insn, 21, 1); 2517 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2518 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2519} 2520 2521static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2522 uint64_t Address, const void *Decoder) { 2523 unsigned size = fieldFromInstruction(Insn, 6, 2); 2524 if (size == 3) return MCDisassembler::Fail; 2525 2526 unsigned load = fieldFromInstruction(Insn, 21, 1); 2527 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2528 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2529} 2530 2531static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2532 uint64_t Address, const void *Decoder) { 2533 DecodeStatus S = MCDisassembler::Success; 2534 2535 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2536 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2537 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2538 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2539 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2540 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2541 2542 // Writeback Operand 2543 switch (Inst.getOpcode()) { 2544 case ARM::VST1d8wb_fixed: 2545 case ARM::VST1d16wb_fixed: 2546 case ARM::VST1d32wb_fixed: 2547 case ARM::VST1d64wb_fixed: 2548 case ARM::VST1d8wb_register: 2549 case ARM::VST1d16wb_register: 2550 case ARM::VST1d32wb_register: 2551 case ARM::VST1d64wb_register: 2552 case ARM::VST1q8wb_fixed: 2553 case ARM::VST1q16wb_fixed: 2554 case ARM::VST1q32wb_fixed: 2555 case ARM::VST1q64wb_fixed: 2556 case ARM::VST1q8wb_register: 2557 case ARM::VST1q16wb_register: 2558 case ARM::VST1q32wb_register: 2559 case ARM::VST1q64wb_register: 2560 case ARM::VST1d8Twb_fixed: 2561 case ARM::VST1d16Twb_fixed: 2562 case ARM::VST1d32Twb_fixed: 2563 case ARM::VST1d64Twb_fixed: 2564 case ARM::VST1d8Twb_register: 2565 case ARM::VST1d16Twb_register: 2566 case ARM::VST1d32Twb_register: 2567 case ARM::VST1d64Twb_register: 2568 case ARM::VST1d8Qwb_fixed: 2569 case ARM::VST1d16Qwb_fixed: 2570 case ARM::VST1d32Qwb_fixed: 2571 case ARM::VST1d64Qwb_fixed: 2572 case ARM::VST1d8Qwb_register: 2573 case ARM::VST1d16Qwb_register: 2574 case ARM::VST1d32Qwb_register: 2575 case ARM::VST1d64Qwb_register: 2576 case ARM::VST2d8wb_fixed: 2577 case ARM::VST2d16wb_fixed: 2578 case ARM::VST2d32wb_fixed: 2579 case ARM::VST2d8wb_register: 2580 case ARM::VST2d16wb_register: 2581 case ARM::VST2d32wb_register: 2582 case ARM::VST2q8wb_fixed: 2583 case ARM::VST2q16wb_fixed: 2584 case ARM::VST2q32wb_fixed: 2585 case ARM::VST2q8wb_register: 2586 case ARM::VST2q16wb_register: 2587 case ARM::VST2q32wb_register: 2588 case ARM::VST2b8wb_fixed: 2589 case ARM::VST2b16wb_fixed: 2590 case ARM::VST2b32wb_fixed: 2591 case ARM::VST2b8wb_register: 2592 case ARM::VST2b16wb_register: 2593 case ARM::VST2b32wb_register: 2594 if (Rm == 0xF) 2595 return MCDisassembler::Fail; 2596 Inst.addOperand(MCOperand::CreateImm(0)); 2597 break; 2598 case ARM::VST3d8_UPD: 2599 case ARM::VST3d16_UPD: 2600 case ARM::VST3d32_UPD: 2601 case ARM::VST3q8_UPD: 2602 case ARM::VST3q16_UPD: 2603 case ARM::VST3q32_UPD: 2604 case ARM::VST4d8_UPD: 2605 case ARM::VST4d16_UPD: 2606 case ARM::VST4d32_UPD: 2607 case ARM::VST4q8_UPD: 2608 case ARM::VST4q16_UPD: 2609 case ARM::VST4q32_UPD: 2610 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2611 return MCDisassembler::Fail; 2612 break; 2613 default: 2614 break; 2615 } 2616 2617 // AddrMode6 Base (register+alignment) 2618 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2619 return MCDisassembler::Fail; 2620 2621 // AddrMode6 Offset (register) 2622 switch (Inst.getOpcode()) { 2623 default: 2624 if (Rm == 0xD) 2625 Inst.addOperand(MCOperand::CreateReg(0)); 2626 else if (Rm != 0xF) { 2627 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2628 return MCDisassembler::Fail; 2629 } 2630 break; 2631 case ARM::VST1d8wb_fixed: 2632 case ARM::VST1d16wb_fixed: 2633 case ARM::VST1d32wb_fixed: 2634 case ARM::VST1d64wb_fixed: 2635 case ARM::VST1q8wb_fixed: 2636 case ARM::VST1q16wb_fixed: 2637 case ARM::VST1q32wb_fixed: 2638 case ARM::VST1q64wb_fixed: 2639 case ARM::VST1d8Twb_fixed: 2640 case ARM::VST1d16Twb_fixed: 2641 case ARM::VST1d32Twb_fixed: 2642 case ARM::VST1d64Twb_fixed: 2643 case ARM::VST1d8Qwb_fixed: 2644 case ARM::VST1d16Qwb_fixed: 2645 case ARM::VST1d32Qwb_fixed: 2646 case ARM::VST1d64Qwb_fixed: 2647 case ARM::VST2d8wb_fixed: 2648 case ARM::VST2d16wb_fixed: 2649 case ARM::VST2d32wb_fixed: 2650 case ARM::VST2q8wb_fixed: 2651 case ARM::VST2q16wb_fixed: 2652 case ARM::VST2q32wb_fixed: 2653 case ARM::VST2b8wb_fixed: 2654 case ARM::VST2b16wb_fixed: 2655 case ARM::VST2b32wb_fixed: 2656 break; 2657 } 2658 2659 2660 // First input register 2661 switch (Inst.getOpcode()) { 2662 case ARM::VST1q16: 2663 case ARM::VST1q32: 2664 case ARM::VST1q64: 2665 case ARM::VST1q8: 2666 case ARM::VST1q16wb_fixed: 2667 case ARM::VST1q16wb_register: 2668 case ARM::VST1q32wb_fixed: 2669 case ARM::VST1q32wb_register: 2670 case ARM::VST1q64wb_fixed: 2671 case ARM::VST1q64wb_register: 2672 case ARM::VST1q8wb_fixed: 2673 case ARM::VST1q8wb_register: 2674 case ARM::VST2d16: 2675 case ARM::VST2d32: 2676 case ARM::VST2d8: 2677 case ARM::VST2d16wb_fixed: 2678 case ARM::VST2d16wb_register: 2679 case ARM::VST2d32wb_fixed: 2680 case ARM::VST2d32wb_register: 2681 case ARM::VST2d8wb_fixed: 2682 case ARM::VST2d8wb_register: 2683 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2684 return MCDisassembler::Fail; 2685 break; 2686 case ARM::VST2b16: 2687 case ARM::VST2b32: 2688 case ARM::VST2b8: 2689 case ARM::VST2b16wb_fixed: 2690 case ARM::VST2b16wb_register: 2691 case ARM::VST2b32wb_fixed: 2692 case ARM::VST2b32wb_register: 2693 case ARM::VST2b8wb_fixed: 2694 case ARM::VST2b8wb_register: 2695 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2696 return MCDisassembler::Fail; 2697 break; 2698 default: 2699 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2700 return MCDisassembler::Fail; 2701 } 2702 2703 // Second input register 2704 switch (Inst.getOpcode()) { 2705 case ARM::VST3d8: 2706 case ARM::VST3d16: 2707 case ARM::VST3d32: 2708 case ARM::VST3d8_UPD: 2709 case ARM::VST3d16_UPD: 2710 case ARM::VST3d32_UPD: 2711 case ARM::VST4d8: 2712 case ARM::VST4d16: 2713 case ARM::VST4d32: 2714 case ARM::VST4d8_UPD: 2715 case ARM::VST4d16_UPD: 2716 case ARM::VST4d32_UPD: 2717 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2718 return MCDisassembler::Fail; 2719 break; 2720 case ARM::VST3q8: 2721 case ARM::VST3q16: 2722 case ARM::VST3q32: 2723 case ARM::VST3q8_UPD: 2724 case ARM::VST3q16_UPD: 2725 case ARM::VST3q32_UPD: 2726 case ARM::VST4q8: 2727 case ARM::VST4q16: 2728 case ARM::VST4q32: 2729 case ARM::VST4q8_UPD: 2730 case ARM::VST4q16_UPD: 2731 case ARM::VST4q32_UPD: 2732 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2733 return MCDisassembler::Fail; 2734 break; 2735 default: 2736 break; 2737 } 2738 2739 // Third input register 2740 switch (Inst.getOpcode()) { 2741 case ARM::VST3d8: 2742 case ARM::VST3d16: 2743 case ARM::VST3d32: 2744 case ARM::VST3d8_UPD: 2745 case ARM::VST3d16_UPD: 2746 case ARM::VST3d32_UPD: 2747 case ARM::VST4d8: 2748 case ARM::VST4d16: 2749 case ARM::VST4d32: 2750 case ARM::VST4d8_UPD: 2751 case ARM::VST4d16_UPD: 2752 case ARM::VST4d32_UPD: 2753 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2754 return MCDisassembler::Fail; 2755 break; 2756 case ARM::VST3q8: 2757 case ARM::VST3q16: 2758 case ARM::VST3q32: 2759 case ARM::VST3q8_UPD: 2760 case ARM::VST3q16_UPD: 2761 case ARM::VST3q32_UPD: 2762 case ARM::VST4q8: 2763 case ARM::VST4q16: 2764 case ARM::VST4q32: 2765 case ARM::VST4q8_UPD: 2766 case ARM::VST4q16_UPD: 2767 case ARM::VST4q32_UPD: 2768 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2769 return MCDisassembler::Fail; 2770 break; 2771 default: 2772 break; 2773 } 2774 2775 // Fourth input register 2776 switch (Inst.getOpcode()) { 2777 case ARM::VST4d8: 2778 case ARM::VST4d16: 2779 case ARM::VST4d32: 2780 case ARM::VST4d8_UPD: 2781 case ARM::VST4d16_UPD: 2782 case ARM::VST4d32_UPD: 2783 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2784 return MCDisassembler::Fail; 2785 break; 2786 case ARM::VST4q8: 2787 case ARM::VST4q16: 2788 case ARM::VST4q32: 2789 case ARM::VST4q8_UPD: 2790 case ARM::VST4q16_UPD: 2791 case ARM::VST4q32_UPD: 2792 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2793 return MCDisassembler::Fail; 2794 break; 2795 default: 2796 break; 2797 } 2798 2799 return S; 2800} 2801 2802static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2803 uint64_t Address, const void *Decoder) { 2804 DecodeStatus S = MCDisassembler::Success; 2805 2806 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2807 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2808 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2809 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2810 unsigned align = fieldFromInstruction(Insn, 4, 1); 2811 unsigned size = fieldFromInstruction(Insn, 6, 2); 2812 2813 if (size == 0 && align == 1) 2814 return MCDisassembler::Fail; 2815 align *= (1 << size); 2816 2817 switch (Inst.getOpcode()) { 2818 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2819 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2820 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2821 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2822 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2823 return MCDisassembler::Fail; 2824 break; 2825 default: 2826 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2827 return MCDisassembler::Fail; 2828 break; 2829 } 2830 if (Rm != 0xF) { 2831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2832 return MCDisassembler::Fail; 2833 } 2834 2835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2836 return MCDisassembler::Fail; 2837 Inst.addOperand(MCOperand::CreateImm(align)); 2838 2839 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2840 // variant encodes Rm == 0xf. Anything else is a register offset post- 2841 // increment and we need to add the register operand to the instruction. 2842 if (Rm != 0xD && Rm != 0xF && 2843 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2844 return MCDisassembler::Fail; 2845 2846 return S; 2847} 2848 2849static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2850 uint64_t Address, const void *Decoder) { 2851 DecodeStatus S = MCDisassembler::Success; 2852 2853 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2854 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2855 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2856 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2857 unsigned align = fieldFromInstruction(Insn, 4, 1); 2858 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2859 align *= 2*size; 2860 2861 switch (Inst.getOpcode()) { 2862 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2863 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2864 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2865 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2866 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2867 return MCDisassembler::Fail; 2868 break; 2869 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2870 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2871 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2872 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2873 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2874 return MCDisassembler::Fail; 2875 break; 2876 default: 2877 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2878 return MCDisassembler::Fail; 2879 break; 2880 } 2881 2882 if (Rm != 0xF) 2883 Inst.addOperand(MCOperand::CreateImm(0)); 2884 2885 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2886 return MCDisassembler::Fail; 2887 Inst.addOperand(MCOperand::CreateImm(align)); 2888 2889 if (Rm != 0xD && Rm != 0xF) { 2890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2891 return MCDisassembler::Fail; 2892 } 2893 2894 return S; 2895} 2896 2897static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2898 uint64_t Address, const void *Decoder) { 2899 DecodeStatus S = MCDisassembler::Success; 2900 2901 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2902 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2903 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2904 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2905 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2906 2907 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2908 return MCDisassembler::Fail; 2909 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2910 return MCDisassembler::Fail; 2911 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2912 return MCDisassembler::Fail; 2913 if (Rm != 0xF) { 2914 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2915 return MCDisassembler::Fail; 2916 } 2917 2918 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2919 return MCDisassembler::Fail; 2920 Inst.addOperand(MCOperand::CreateImm(0)); 2921 2922 if (Rm == 0xD) 2923 Inst.addOperand(MCOperand::CreateReg(0)); 2924 else if (Rm != 0xF) { 2925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2926 return MCDisassembler::Fail; 2927 } 2928 2929 return S; 2930} 2931 2932static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2933 uint64_t Address, const void *Decoder) { 2934 DecodeStatus S = MCDisassembler::Success; 2935 2936 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2937 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2938 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2939 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2940 unsigned size = fieldFromInstruction(Insn, 6, 2); 2941 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2942 unsigned align = fieldFromInstruction(Insn, 4, 1); 2943 2944 if (size == 0x3) { 2945 if (align == 0) 2946 return MCDisassembler::Fail; 2947 size = 4; 2948 align = 16; 2949 } else { 2950 if (size == 2) { 2951 size = 1 << size; 2952 align *= 8; 2953 } else { 2954 size = 1 << size; 2955 align *= 4*size; 2956 } 2957 } 2958 2959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2960 return MCDisassembler::Fail; 2961 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2962 return MCDisassembler::Fail; 2963 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2964 return MCDisassembler::Fail; 2965 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2966 return MCDisassembler::Fail; 2967 if (Rm != 0xF) { 2968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2969 return MCDisassembler::Fail; 2970 } 2971 2972 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2973 return MCDisassembler::Fail; 2974 Inst.addOperand(MCOperand::CreateImm(align)); 2975 2976 if (Rm == 0xD) 2977 Inst.addOperand(MCOperand::CreateReg(0)); 2978 else if (Rm != 0xF) { 2979 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2980 return MCDisassembler::Fail; 2981 } 2982 2983 return S; 2984} 2985 2986static DecodeStatus 2987DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2988 uint64_t Address, const void *Decoder) { 2989 DecodeStatus S = MCDisassembler::Success; 2990 2991 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2992 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2993 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2994 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2995 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2996 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2997 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2998 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2999 3000 if (Q) { 3001 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3002 return MCDisassembler::Fail; 3003 } else { 3004 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3005 return MCDisassembler::Fail; 3006 } 3007 3008 Inst.addOperand(MCOperand::CreateImm(imm)); 3009 3010 switch (Inst.getOpcode()) { 3011 case ARM::VORRiv4i16: 3012 case ARM::VORRiv2i32: 3013 case ARM::VBICiv4i16: 3014 case ARM::VBICiv2i32: 3015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3016 return MCDisassembler::Fail; 3017 break; 3018 case ARM::VORRiv8i16: 3019 case ARM::VORRiv4i32: 3020 case ARM::VBICiv8i16: 3021 case ARM::VBICiv4i32: 3022 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3023 return MCDisassembler::Fail; 3024 break; 3025 default: 3026 break; 3027 } 3028 3029 return S; 3030} 3031 3032static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3033 uint64_t Address, const void *Decoder) { 3034 DecodeStatus S = MCDisassembler::Success; 3035 3036 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3037 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3038 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3039 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3040 unsigned size = fieldFromInstruction(Insn, 18, 2); 3041 3042 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3043 return MCDisassembler::Fail; 3044 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3045 return MCDisassembler::Fail; 3046 Inst.addOperand(MCOperand::CreateImm(8 << size)); 3047 3048 return S; 3049} 3050 3051static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3052 uint64_t Address, const void *Decoder) { 3053 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 3054 return MCDisassembler::Success; 3055} 3056 3057static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3058 uint64_t Address, const void *Decoder) { 3059 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3060 return MCDisassembler::Success; 3061} 3062 3063static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3064 uint64_t Address, const void *Decoder) { 3065 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3066 return MCDisassembler::Success; 3067} 3068 3069static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3070 uint64_t Address, const void *Decoder) { 3071 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3072 return MCDisassembler::Success; 3073} 3074 3075static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3076 uint64_t Address, const void *Decoder) { 3077 DecodeStatus S = MCDisassembler::Success; 3078 3079 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3080 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3081 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3082 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3083 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3084 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3085 unsigned op = fieldFromInstruction(Insn, 6, 1); 3086 3087 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3088 return MCDisassembler::Fail; 3089 if (op) { 3090 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3091 return MCDisassembler::Fail; // Writeback 3092 } 3093 3094 switch (Inst.getOpcode()) { 3095 case ARM::VTBL2: 3096 case ARM::VTBX2: 3097 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3098 return MCDisassembler::Fail; 3099 break; 3100 default: 3101 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3102 return MCDisassembler::Fail; 3103 } 3104 3105 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3106 return MCDisassembler::Fail; 3107 3108 return S; 3109} 3110 3111static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3112 uint64_t Address, const void *Decoder) { 3113 DecodeStatus S = MCDisassembler::Success; 3114 3115 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3116 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3117 3118 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3119 return MCDisassembler::Fail; 3120 3121 switch(Inst.getOpcode()) { 3122 default: 3123 return MCDisassembler::Fail; 3124 case ARM::tADR: 3125 break; // tADR does not explicitly represent the PC as an operand. 3126 case ARM::tADDrSPi: 3127 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3128 break; 3129 } 3130 3131 Inst.addOperand(MCOperand::CreateImm(imm)); 3132 return S; 3133} 3134 3135static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3136 uint64_t Address, const void *Decoder) { 3137 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3138 true, 2, Inst, Decoder)) 3139 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3140 return MCDisassembler::Success; 3141} 3142 3143static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3144 uint64_t Address, const void *Decoder) { 3145 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3146 true, 4, Inst, Decoder)) 3147 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3148 return MCDisassembler::Success; 3149} 3150 3151static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3152 uint64_t Address, const void *Decoder) { 3153 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3154 true, 2, Inst, Decoder)) 3155 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3156 return MCDisassembler::Success; 3157} 3158 3159static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3160 uint64_t Address, const void *Decoder) { 3161 DecodeStatus S = MCDisassembler::Success; 3162 3163 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3164 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3165 3166 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3167 return MCDisassembler::Fail; 3168 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3169 return MCDisassembler::Fail; 3170 3171 return S; 3172} 3173 3174static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3175 uint64_t Address, const void *Decoder) { 3176 DecodeStatus S = MCDisassembler::Success; 3177 3178 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3179 unsigned imm = fieldFromInstruction(Val, 3, 5); 3180 3181 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3182 return MCDisassembler::Fail; 3183 Inst.addOperand(MCOperand::CreateImm(imm)); 3184 3185 return S; 3186} 3187 3188static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3189 uint64_t Address, const void *Decoder) { 3190 unsigned imm = Val << 2; 3191 3192 Inst.addOperand(MCOperand::CreateImm(imm)); 3193 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3194 3195 return MCDisassembler::Success; 3196} 3197 3198static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3199 uint64_t Address, const void *Decoder) { 3200 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3201 Inst.addOperand(MCOperand::CreateImm(Val)); 3202 3203 return MCDisassembler::Success; 3204} 3205 3206static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3207 uint64_t Address, const void *Decoder) { 3208 DecodeStatus S = MCDisassembler::Success; 3209 3210 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3211 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3212 unsigned imm = fieldFromInstruction(Val, 0, 2); 3213 3214 // Thumb stores cannot use PC as dest register. 3215 switch (Inst.getOpcode()) { 3216 case ARM::t2STRHs: 3217 case ARM::t2STRBs: 3218 case ARM::t2STRs: 3219 if (Rn == 15) 3220 return MCDisassembler::Fail; 3221 default: 3222 break; 3223 } 3224 3225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3226 return MCDisassembler::Fail; 3227 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3228 return MCDisassembler::Fail; 3229 Inst.addOperand(MCOperand::CreateImm(imm)); 3230 3231 return S; 3232} 3233 3234static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3235 uint64_t Address, const void *Decoder) { 3236 DecodeStatus S = MCDisassembler::Success; 3237 3238 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3239 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3240 3241 if (Rn == 15) { 3242 switch (Inst.getOpcode()) { 3243 case ARM::t2LDRBs: 3244 Inst.setOpcode(ARM::t2LDRBpci); 3245 break; 3246 case ARM::t2LDRHs: 3247 Inst.setOpcode(ARM::t2LDRHpci); 3248 break; 3249 case ARM::t2LDRSHs: 3250 Inst.setOpcode(ARM::t2LDRSHpci); 3251 break; 3252 case ARM::t2LDRSBs: 3253 Inst.setOpcode(ARM::t2LDRSBpci); 3254 break; 3255 case ARM::t2LDRs: 3256 Inst.setOpcode(ARM::t2LDRpci); 3257 break; 3258 case ARM::t2PLDs: 3259 Inst.setOpcode(ARM::t2PLDpci); 3260 break; 3261 case ARM::t2PLIs: 3262 Inst.setOpcode(ARM::t2PLIpci); 3263 break; 3264 default: 3265 return MCDisassembler::Fail; 3266 } 3267 3268 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3269 } 3270 3271 if (Rt == 15) { 3272 switch (Inst.getOpcode()) { 3273 case ARM::t2LDRSHs: 3274 return MCDisassembler::Fail; 3275 case ARM::t2LDRHs: 3276 // FIXME: this instruction is only available with MP extensions, 3277 // this should be checked first but we don't have access to the 3278 // feature bits here. 3279 Inst.setOpcode(ARM::t2PLDWs); 3280 break; 3281 default: 3282 break; 3283 } 3284 } 3285 3286 switch (Inst.getOpcode()) { 3287 case ARM::t2PLDs: 3288 case ARM::t2PLDWs: 3289 case ARM::t2PLIs: 3290 break; 3291 default: 3292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3293 return MCDisassembler::Fail; 3294 } 3295 3296 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3297 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3298 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3299 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3300 return MCDisassembler::Fail; 3301 3302 return S; 3303} 3304 3305static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3306 uint64_t Address, const void* Decoder) { 3307 DecodeStatus S = MCDisassembler::Success; 3308 3309 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3310 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3311 unsigned U = fieldFromInstruction(Insn, 9, 1); 3312 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3313 imm |= (U << 8); 3314 imm |= (Rn << 9); 3315 3316 if (Rn == 15) { 3317 switch (Inst.getOpcode()) { 3318 case ARM::t2LDRi8: 3319 Inst.setOpcode(ARM::t2LDRpci); 3320 break; 3321 case ARM::t2LDRBi8: 3322 Inst.setOpcode(ARM::t2LDRBpci); 3323 break; 3324 case ARM::t2LDRSBi8: 3325 Inst.setOpcode(ARM::t2LDRSBpci); 3326 break; 3327 case ARM::t2LDRHi8: 3328 Inst.setOpcode(ARM::t2LDRHpci); 3329 break; 3330 case ARM::t2LDRSHi8: 3331 Inst.setOpcode(ARM::t2LDRSHpci); 3332 break; 3333 case ARM::t2PLDi8: 3334 Inst.setOpcode(ARM::t2PLDpci); 3335 break; 3336 case ARM::t2PLIi8: 3337 Inst.setOpcode(ARM::t2PLIpci); 3338 break; 3339 default: 3340 return MCDisassembler::Fail; 3341 } 3342 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3343 } 3344 3345 if (Rt == 15) { 3346 switch (Inst.getOpcode()) { 3347 case ARM::t2LDRSHi8: 3348 return MCDisassembler::Fail; 3349 default: 3350 break; 3351 } 3352 } 3353 3354 switch (Inst.getOpcode()) { 3355 case ARM::t2PLDi8: 3356 case ARM::t2PLIi8: 3357 case ARM::t2PLDWi8: 3358 break; 3359 default: 3360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3361 return MCDisassembler::Fail; 3362 } 3363 3364 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3365 return MCDisassembler::Fail; 3366 return S; 3367} 3368 3369static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3370 uint64_t Address, const void* Decoder) { 3371 DecodeStatus S = MCDisassembler::Success; 3372 3373 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3374 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3375 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3376 imm |= (Rn << 13); 3377 3378 if (Rn == 15) { 3379 switch (Inst.getOpcode()) { 3380 case ARM::t2LDRi12: 3381 Inst.setOpcode(ARM::t2LDRpci); 3382 break; 3383 case ARM::t2LDRHi12: 3384 Inst.setOpcode(ARM::t2LDRHpci); 3385 break; 3386 case ARM::t2LDRSHi12: 3387 Inst.setOpcode(ARM::t2LDRSHpci); 3388 break; 3389 case ARM::t2LDRBi12: 3390 Inst.setOpcode(ARM::t2LDRBpci); 3391 break; 3392 case ARM::t2LDRSBi12: 3393 Inst.setOpcode(ARM::t2LDRSBpci); 3394 break; 3395 case ARM::t2PLDi12: 3396 Inst.setOpcode(ARM::t2PLDpci); 3397 break; 3398 case ARM::t2PLIi12: 3399 Inst.setOpcode(ARM::t2PLIpci); 3400 break; 3401 default: 3402 return MCDisassembler::Fail; 3403 } 3404 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3405 } 3406 3407 if (Rt == 15) { 3408 switch (Inst.getOpcode()) { 3409 case ARM::t2LDRSHi12: 3410 return MCDisassembler::Fail; 3411 case ARM::t2LDRHi12: 3412 Inst.setOpcode(ARM::t2PLDi12); 3413 break; 3414 default: 3415 break; 3416 } 3417 } 3418 3419 switch (Inst.getOpcode()) { 3420 case ARM::t2PLDi12: 3421 case ARM::t2PLDWi12: 3422 case ARM::t2PLIi12: 3423 break; 3424 default: 3425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3426 return MCDisassembler::Fail; 3427 } 3428 3429 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3430 return MCDisassembler::Fail; 3431 return S; 3432} 3433 3434static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3435 uint64_t Address, const void* Decoder) { 3436 DecodeStatus S = MCDisassembler::Success; 3437 3438 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3439 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3440 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3441 imm |= (Rn << 9); 3442 3443 if (Rn == 15) { 3444 switch (Inst.getOpcode()) { 3445 case ARM::t2LDRT: 3446 Inst.setOpcode(ARM::t2LDRpci); 3447 break; 3448 case ARM::t2LDRBT: 3449 Inst.setOpcode(ARM::t2LDRBpci); 3450 break; 3451 case ARM::t2LDRHT: 3452 Inst.setOpcode(ARM::t2LDRHpci); 3453 break; 3454 case ARM::t2LDRSBT: 3455 Inst.setOpcode(ARM::t2LDRSBpci); 3456 break; 3457 case ARM::t2LDRSHT: 3458 Inst.setOpcode(ARM::t2LDRSHpci); 3459 break; 3460 default: 3461 return MCDisassembler::Fail; 3462 } 3463 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3464 } 3465 3466 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3467 return MCDisassembler::Fail; 3468 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3469 return MCDisassembler::Fail; 3470 return S; 3471} 3472 3473static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3474 uint64_t Address, const void* Decoder) { 3475 DecodeStatus S = MCDisassembler::Success; 3476 3477 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3478 unsigned U = fieldFromInstruction(Insn, 23, 1); 3479 int imm = fieldFromInstruction(Insn, 0, 12); 3480 3481 if (Rt == 15) { 3482 switch (Inst.getOpcode()) { 3483 case ARM::t2LDRBpci: 3484 case ARM::t2LDRHpci: 3485 Inst.setOpcode(ARM::t2PLDpci); 3486 break; 3487 case ARM::t2LDRSBpci: 3488 Inst.setOpcode(ARM::t2PLIpci); 3489 break; 3490 case ARM::t2LDRSHpci: 3491 return MCDisassembler::Fail; 3492 default: 3493 break; 3494 } 3495 } 3496 3497 switch(Inst.getOpcode()) { 3498 case ARM::t2PLDpci: 3499 case ARM::t2PLIpci: 3500 break; 3501 default: 3502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3503 return MCDisassembler::Fail; 3504 } 3505 3506 if (!U) { 3507 // Special case for #-0. 3508 if (imm == 0) 3509 imm = INT32_MIN; 3510 else 3511 imm = -imm; 3512 } 3513 Inst.addOperand(MCOperand::CreateImm(imm)); 3514 3515 return S; 3516} 3517 3518static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3519 uint64_t Address, const void *Decoder) { 3520 if (Val == 0) 3521 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3522 else { 3523 int imm = Val & 0xFF; 3524 3525 if (!(Val & 0x100)) imm *= -1; 3526 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3527 } 3528 3529 return MCDisassembler::Success; 3530} 3531 3532static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3533 uint64_t Address, const void *Decoder) { 3534 DecodeStatus S = MCDisassembler::Success; 3535 3536 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3537 unsigned imm = fieldFromInstruction(Val, 0, 9); 3538 3539 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3540 return MCDisassembler::Fail; 3541 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3542 return MCDisassembler::Fail; 3543 3544 return S; 3545} 3546 3547static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3548 uint64_t Address, const void *Decoder) { 3549 DecodeStatus S = MCDisassembler::Success; 3550 3551 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3552 unsigned imm = fieldFromInstruction(Val, 0, 8); 3553 3554 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3555 return MCDisassembler::Fail; 3556 3557 Inst.addOperand(MCOperand::CreateImm(imm)); 3558 3559 return S; 3560} 3561 3562static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3563 uint64_t Address, const void *Decoder) { 3564 int imm = Val & 0xFF; 3565 if (Val == 0) 3566 imm = INT32_MIN; 3567 else if (!(Val & 0x100)) 3568 imm *= -1; 3569 Inst.addOperand(MCOperand::CreateImm(imm)); 3570 3571 return MCDisassembler::Success; 3572} 3573 3574 3575static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3576 uint64_t Address, const void *Decoder) { 3577 DecodeStatus S = MCDisassembler::Success; 3578 3579 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3580 unsigned imm = fieldFromInstruction(Val, 0, 9); 3581 3582 // Thumb stores cannot use PC as dest register. 3583 switch (Inst.getOpcode()) { 3584 case ARM::t2STRT: 3585 case ARM::t2STRBT: 3586 case ARM::t2STRHT: 3587 case ARM::t2STRi8: 3588 case ARM::t2STRHi8: 3589 case ARM::t2STRBi8: 3590 if (Rn == 15) 3591 return MCDisassembler::Fail; 3592 break; 3593 default: 3594 break; 3595 } 3596 3597 // Some instructions always use an additive offset. 3598 switch (Inst.getOpcode()) { 3599 case ARM::t2LDRT: 3600 case ARM::t2LDRBT: 3601 case ARM::t2LDRHT: 3602 case ARM::t2LDRSBT: 3603 case ARM::t2LDRSHT: 3604 case ARM::t2STRT: 3605 case ARM::t2STRBT: 3606 case ARM::t2STRHT: 3607 imm |= 0x100; 3608 break; 3609 default: 3610 break; 3611 } 3612 3613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3614 return MCDisassembler::Fail; 3615 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3616 return MCDisassembler::Fail; 3617 3618 return S; 3619} 3620 3621static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3622 uint64_t Address, const void *Decoder) { 3623 DecodeStatus S = MCDisassembler::Success; 3624 3625 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3626 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3627 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3628 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3629 addr |= Rn << 9; 3630 unsigned load = fieldFromInstruction(Insn, 20, 1); 3631 3632 if (Rn == 15) { 3633 switch (Inst.getOpcode()) { 3634 case ARM::t2LDR_PRE: 3635 case ARM::t2LDR_POST: 3636 Inst.setOpcode(ARM::t2LDRpci); 3637 break; 3638 case ARM::t2LDRB_PRE: 3639 case ARM::t2LDRB_POST: 3640 Inst.setOpcode(ARM::t2LDRBpci); 3641 break; 3642 case ARM::t2LDRH_PRE: 3643 case ARM::t2LDRH_POST: 3644 Inst.setOpcode(ARM::t2LDRHpci); 3645 break; 3646 case ARM::t2LDRSB_PRE: 3647 case ARM::t2LDRSB_POST: 3648 if (Rt == 15) 3649 Inst.setOpcode(ARM::t2PLIpci); 3650 else 3651 Inst.setOpcode(ARM::t2LDRSBpci); 3652 break; 3653 case ARM::t2LDRSH_PRE: 3654 case ARM::t2LDRSH_POST: 3655 Inst.setOpcode(ARM::t2LDRSHpci); 3656 break; 3657 default: 3658 return MCDisassembler::Fail; 3659 } 3660 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3661 } 3662 3663 if (!load) { 3664 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3665 return MCDisassembler::Fail; 3666 } 3667 3668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3669 return MCDisassembler::Fail; 3670 3671 if (load) { 3672 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3673 return MCDisassembler::Fail; 3674 } 3675 3676 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3677 return MCDisassembler::Fail; 3678 3679 return S; 3680} 3681 3682static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3683 uint64_t Address, const void *Decoder) { 3684 DecodeStatus S = MCDisassembler::Success; 3685 3686 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3687 unsigned imm = fieldFromInstruction(Val, 0, 12); 3688 3689 // Thumb stores cannot use PC as dest register. 3690 switch (Inst.getOpcode()) { 3691 case ARM::t2STRi12: 3692 case ARM::t2STRBi12: 3693 case ARM::t2STRHi12: 3694 if (Rn == 15) 3695 return MCDisassembler::Fail; 3696 default: 3697 break; 3698 } 3699 3700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3701 return MCDisassembler::Fail; 3702 Inst.addOperand(MCOperand::CreateImm(imm)); 3703 3704 return S; 3705} 3706 3707 3708static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3709 uint64_t Address, const void *Decoder) { 3710 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3711 3712 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3713 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3714 Inst.addOperand(MCOperand::CreateImm(imm)); 3715 3716 return MCDisassembler::Success; 3717} 3718 3719static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3720 uint64_t Address, const void *Decoder) { 3721 DecodeStatus S = MCDisassembler::Success; 3722 3723 if (Inst.getOpcode() == ARM::tADDrSP) { 3724 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3725 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3726 3727 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3728 return MCDisassembler::Fail; 3729 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3731 return MCDisassembler::Fail; 3732 } else if (Inst.getOpcode() == ARM::tADDspr) { 3733 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3734 3735 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3736 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3738 return MCDisassembler::Fail; 3739 } 3740 3741 return S; 3742} 3743 3744static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3745 uint64_t Address, const void *Decoder) { 3746 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3747 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3748 3749 Inst.addOperand(MCOperand::CreateImm(imod)); 3750 Inst.addOperand(MCOperand::CreateImm(flags)); 3751 3752 return MCDisassembler::Success; 3753} 3754 3755static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3756 uint64_t Address, const void *Decoder) { 3757 DecodeStatus S = MCDisassembler::Success; 3758 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3759 unsigned add = fieldFromInstruction(Insn, 4, 1); 3760 3761 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3762 return MCDisassembler::Fail; 3763 Inst.addOperand(MCOperand::CreateImm(add)); 3764 3765 return S; 3766} 3767 3768static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3769 uint64_t Address, const void *Decoder) { 3770 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3771 // Note only one trailing zero not two. Also the J1 and J2 values are from 3772 // the encoded instruction. So here change to I1 and I2 values via: 3773 // I1 = NOT(J1 EOR S); 3774 // I2 = NOT(J2 EOR S); 3775 // and build the imm32 with two trailing zeros as documented: 3776 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3777 unsigned S = (Val >> 23) & 1; 3778 unsigned J1 = (Val >> 22) & 1; 3779 unsigned J2 = (Val >> 21) & 1; 3780 unsigned I1 = !(J1 ^ S); 3781 unsigned I2 = !(J2 ^ S); 3782 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3783 int imm32 = SignExtend32<25>(tmp << 1); 3784 3785 if (!tryAddingSymbolicOperand(Address, 3786 (Address & ~2u) + imm32 + 4, 3787 true, 4, Inst, Decoder)) 3788 Inst.addOperand(MCOperand::CreateImm(imm32)); 3789 return MCDisassembler::Success; 3790} 3791 3792static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3793 uint64_t Address, const void *Decoder) { 3794 if (Val == 0xA || Val == 0xB) 3795 return MCDisassembler::Fail; 3796 3797 Inst.addOperand(MCOperand::CreateImm(Val)); 3798 return MCDisassembler::Success; 3799} 3800 3801static DecodeStatus 3802DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3803 uint64_t Address, const void *Decoder) { 3804 DecodeStatus S = MCDisassembler::Success; 3805 3806 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3807 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3808 3809 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3811 return MCDisassembler::Fail; 3812 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3813 return MCDisassembler::Fail; 3814 return S; 3815} 3816 3817static DecodeStatus 3818DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3819 uint64_t Address, const void *Decoder) { 3820 DecodeStatus S = MCDisassembler::Success; 3821 3822 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3823 if (pred == 0xE || pred == 0xF) { 3824 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3825 switch (opc) { 3826 default: 3827 return MCDisassembler::Fail; 3828 case 0xf3bf8f4: 3829 Inst.setOpcode(ARM::t2DSB); 3830 break; 3831 case 0xf3bf8f5: 3832 Inst.setOpcode(ARM::t2DMB); 3833 break; 3834 case 0xf3bf8f6: 3835 Inst.setOpcode(ARM::t2ISB); 3836 break; 3837 } 3838 3839 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3840 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3841 } 3842 3843 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3844 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3845 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3846 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3847 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3848 3849 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3850 return MCDisassembler::Fail; 3851 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3852 return MCDisassembler::Fail; 3853 3854 return S; 3855} 3856 3857// Decode a shifted immediate operand. These basically consist 3858// of an 8-bit value, and a 4-bit directive that specifies either 3859// a splat operation or a rotation. 3860static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3861 uint64_t Address, const void *Decoder) { 3862 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3863 if (ctrl == 0) { 3864 unsigned byte = fieldFromInstruction(Val, 8, 2); 3865 unsigned imm = fieldFromInstruction(Val, 0, 8); 3866 switch (byte) { 3867 case 0: 3868 Inst.addOperand(MCOperand::CreateImm(imm)); 3869 break; 3870 case 1: 3871 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3872 break; 3873 case 2: 3874 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3875 break; 3876 case 3: 3877 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3878 (imm << 8) | imm)); 3879 break; 3880 } 3881 } else { 3882 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3883 unsigned rot = fieldFromInstruction(Val, 7, 5); 3884 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3885 Inst.addOperand(MCOperand::CreateImm(imm)); 3886 } 3887 3888 return MCDisassembler::Success; 3889} 3890 3891static DecodeStatus 3892DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3893 uint64_t Address, const void *Decoder){ 3894 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3895 true, 2, Inst, Decoder)) 3896 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3897 return MCDisassembler::Success; 3898} 3899 3900static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3901 uint64_t Address, const void *Decoder){ 3902 // Val is passed in as S:J1:J2:imm10:imm11 3903 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3904 // the encoded instruction. So here change to I1 and I2 values via: 3905 // I1 = NOT(J1 EOR S); 3906 // I2 = NOT(J2 EOR S); 3907 // and build the imm32 with one trailing zero as documented: 3908 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3909 unsigned S = (Val >> 23) & 1; 3910 unsigned J1 = (Val >> 22) & 1; 3911 unsigned J2 = (Val >> 21) & 1; 3912 unsigned I1 = !(J1 ^ S); 3913 unsigned I2 = !(J2 ^ S); 3914 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3915 int imm32 = SignExtend32<25>(tmp << 1); 3916 3917 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3918 true, 4, Inst, Decoder)) 3919 Inst.addOperand(MCOperand::CreateImm(imm32)); 3920 return MCDisassembler::Success; 3921} 3922 3923static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3924 uint64_t Address, const void *Decoder) { 3925 if (Val & ~0xf) 3926 return MCDisassembler::Fail; 3927 3928 Inst.addOperand(MCOperand::CreateImm(Val)); 3929 return MCDisassembler::Success; 3930} 3931 3932static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 3933 uint64_t Address, const void *Decoder) { 3934 if (Val & ~0xf) 3935 return MCDisassembler::Fail; 3936 3937 Inst.addOperand(MCOperand::CreateImm(Val)); 3938 return MCDisassembler::Success; 3939} 3940 3941static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3942 uint64_t Address, const void *Decoder) { 3943 if (!Val) return MCDisassembler::Fail; 3944 Inst.addOperand(MCOperand::CreateImm(Val)); 3945 return MCDisassembler::Success; 3946} 3947 3948static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3949 uint64_t Address, const void *Decoder) { 3950 DecodeStatus S = MCDisassembler::Success; 3951 3952 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3953 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3954 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3955 3956 if (Rn == 0xF) 3957 S = MCDisassembler::SoftFail; 3958 3959 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3960 return MCDisassembler::Fail; 3961 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3962 return MCDisassembler::Fail; 3963 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3964 return MCDisassembler::Fail; 3965 3966 return S; 3967} 3968 3969static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3970 uint64_t Address, const void *Decoder){ 3971 DecodeStatus S = MCDisassembler::Success; 3972 3973 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3974 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3975 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3976 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3977 3978 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3979 return MCDisassembler::Fail; 3980 3981 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 3982 S = MCDisassembler::SoftFail; 3983 3984 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3985 return MCDisassembler::Fail; 3986 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3987 return MCDisassembler::Fail; 3988 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3989 return MCDisassembler::Fail; 3990 3991 return S; 3992} 3993 3994static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3995 uint64_t Address, const void *Decoder) { 3996 DecodeStatus S = MCDisassembler::Success; 3997 3998 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3999 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4000 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4001 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4002 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4003 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4004 4005 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4006 4007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4008 return MCDisassembler::Fail; 4009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4010 return MCDisassembler::Fail; 4011 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4012 return MCDisassembler::Fail; 4013 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4014 return MCDisassembler::Fail; 4015 4016 return S; 4017} 4018 4019static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4020 uint64_t Address, const void *Decoder) { 4021 DecodeStatus S = MCDisassembler::Success; 4022 4023 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4024 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4025 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4026 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4027 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4028 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4029 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4030 4031 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4032 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4033 4034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4035 return MCDisassembler::Fail; 4036 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4037 return MCDisassembler::Fail; 4038 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4039 return MCDisassembler::Fail; 4040 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4041 return MCDisassembler::Fail; 4042 4043 return S; 4044} 4045 4046 4047static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4048 uint64_t Address, const void *Decoder) { 4049 DecodeStatus S = MCDisassembler::Success; 4050 4051 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4052 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4053 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4054 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4055 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4056 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4057 4058 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4059 4060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4061 return MCDisassembler::Fail; 4062 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4063 return MCDisassembler::Fail; 4064 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4065 return MCDisassembler::Fail; 4066 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4067 return MCDisassembler::Fail; 4068 4069 return S; 4070} 4071 4072static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4073 uint64_t Address, const void *Decoder) { 4074 DecodeStatus S = MCDisassembler::Success; 4075 4076 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4077 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4078 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4079 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4080 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4081 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4082 4083 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4084 4085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4086 return MCDisassembler::Fail; 4087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4088 return MCDisassembler::Fail; 4089 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4090 return MCDisassembler::Fail; 4091 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4092 return MCDisassembler::Fail; 4093 4094 return S; 4095} 4096 4097static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4098 uint64_t Address, const void *Decoder) { 4099 DecodeStatus S = MCDisassembler::Success; 4100 4101 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4102 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4103 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4104 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4105 unsigned size = fieldFromInstruction(Insn, 10, 2); 4106 4107 unsigned align = 0; 4108 unsigned index = 0; 4109 switch (size) { 4110 default: 4111 return MCDisassembler::Fail; 4112 case 0: 4113 if (fieldFromInstruction(Insn, 4, 1)) 4114 return MCDisassembler::Fail; // UNDEFINED 4115 index = fieldFromInstruction(Insn, 5, 3); 4116 break; 4117 case 1: 4118 if (fieldFromInstruction(Insn, 5, 1)) 4119 return MCDisassembler::Fail; // UNDEFINED 4120 index = fieldFromInstruction(Insn, 6, 2); 4121 if (fieldFromInstruction(Insn, 4, 1)) 4122 align = 2; 4123 break; 4124 case 2: 4125 if (fieldFromInstruction(Insn, 6, 1)) 4126 return MCDisassembler::Fail; // UNDEFINED 4127 index = fieldFromInstruction(Insn, 7, 1); 4128 4129 switch (fieldFromInstruction(Insn, 4, 2)) { 4130 case 0 : 4131 align = 0; break; 4132 case 3: 4133 align = 4; break; 4134 default: 4135 return MCDisassembler::Fail; 4136 } 4137 break; 4138 } 4139 4140 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4141 return MCDisassembler::Fail; 4142 if (Rm != 0xF) { // Writeback 4143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4144 return MCDisassembler::Fail; 4145 } 4146 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4147 return MCDisassembler::Fail; 4148 Inst.addOperand(MCOperand::CreateImm(align)); 4149 if (Rm != 0xF) { 4150 if (Rm != 0xD) { 4151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4152 return MCDisassembler::Fail; 4153 } else 4154 Inst.addOperand(MCOperand::CreateReg(0)); 4155 } 4156 4157 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4158 return MCDisassembler::Fail; 4159 Inst.addOperand(MCOperand::CreateImm(index)); 4160 4161 return S; 4162} 4163 4164static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4165 uint64_t Address, const void *Decoder) { 4166 DecodeStatus S = MCDisassembler::Success; 4167 4168 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4169 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4170 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4171 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4172 unsigned size = fieldFromInstruction(Insn, 10, 2); 4173 4174 unsigned align = 0; 4175 unsigned index = 0; 4176 switch (size) { 4177 default: 4178 return MCDisassembler::Fail; 4179 case 0: 4180 if (fieldFromInstruction(Insn, 4, 1)) 4181 return MCDisassembler::Fail; // UNDEFINED 4182 index = fieldFromInstruction(Insn, 5, 3); 4183 break; 4184 case 1: 4185 if (fieldFromInstruction(Insn, 5, 1)) 4186 return MCDisassembler::Fail; // UNDEFINED 4187 index = fieldFromInstruction(Insn, 6, 2); 4188 if (fieldFromInstruction(Insn, 4, 1)) 4189 align = 2; 4190 break; 4191 case 2: 4192 if (fieldFromInstruction(Insn, 6, 1)) 4193 return MCDisassembler::Fail; // UNDEFINED 4194 index = fieldFromInstruction(Insn, 7, 1); 4195 4196 switch (fieldFromInstruction(Insn, 4, 2)) { 4197 case 0: 4198 align = 0; break; 4199 case 3: 4200 align = 4; break; 4201 default: 4202 return MCDisassembler::Fail; 4203 } 4204 break; 4205 } 4206 4207 if (Rm != 0xF) { // Writeback 4208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4209 return MCDisassembler::Fail; 4210 } 4211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4212 return MCDisassembler::Fail; 4213 Inst.addOperand(MCOperand::CreateImm(align)); 4214 if (Rm != 0xF) { 4215 if (Rm != 0xD) { 4216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4217 return MCDisassembler::Fail; 4218 } else 4219 Inst.addOperand(MCOperand::CreateReg(0)); 4220 } 4221 4222 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4223 return MCDisassembler::Fail; 4224 Inst.addOperand(MCOperand::CreateImm(index)); 4225 4226 return S; 4227} 4228 4229 4230static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4231 uint64_t Address, const void *Decoder) { 4232 DecodeStatus S = MCDisassembler::Success; 4233 4234 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4235 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4236 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4237 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4238 unsigned size = fieldFromInstruction(Insn, 10, 2); 4239 4240 unsigned align = 0; 4241 unsigned index = 0; 4242 unsigned inc = 1; 4243 switch (size) { 4244 default: 4245 return MCDisassembler::Fail; 4246 case 0: 4247 index = fieldFromInstruction(Insn, 5, 3); 4248 if (fieldFromInstruction(Insn, 4, 1)) 4249 align = 2; 4250 break; 4251 case 1: 4252 index = fieldFromInstruction(Insn, 6, 2); 4253 if (fieldFromInstruction(Insn, 4, 1)) 4254 align = 4; 4255 if (fieldFromInstruction(Insn, 5, 1)) 4256 inc = 2; 4257 break; 4258 case 2: 4259 if (fieldFromInstruction(Insn, 5, 1)) 4260 return MCDisassembler::Fail; // UNDEFINED 4261 index = fieldFromInstruction(Insn, 7, 1); 4262 if (fieldFromInstruction(Insn, 4, 1) != 0) 4263 align = 8; 4264 if (fieldFromInstruction(Insn, 6, 1)) 4265 inc = 2; 4266 break; 4267 } 4268 4269 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4270 return MCDisassembler::Fail; 4271 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4272 return MCDisassembler::Fail; 4273 if (Rm != 0xF) { // Writeback 4274 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4275 return MCDisassembler::Fail; 4276 } 4277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4278 return MCDisassembler::Fail; 4279 Inst.addOperand(MCOperand::CreateImm(align)); 4280 if (Rm != 0xF) { 4281 if (Rm != 0xD) { 4282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4283 return MCDisassembler::Fail; 4284 } else 4285 Inst.addOperand(MCOperand::CreateReg(0)); 4286 } 4287 4288 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4289 return MCDisassembler::Fail; 4290 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4291 return MCDisassembler::Fail; 4292 Inst.addOperand(MCOperand::CreateImm(index)); 4293 4294 return S; 4295} 4296 4297static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4298 uint64_t Address, const void *Decoder) { 4299 DecodeStatus S = MCDisassembler::Success; 4300 4301 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4302 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4303 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4304 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4305 unsigned size = fieldFromInstruction(Insn, 10, 2); 4306 4307 unsigned align = 0; 4308 unsigned index = 0; 4309 unsigned inc = 1; 4310 switch (size) { 4311 default: 4312 return MCDisassembler::Fail; 4313 case 0: 4314 index = fieldFromInstruction(Insn, 5, 3); 4315 if (fieldFromInstruction(Insn, 4, 1)) 4316 align = 2; 4317 break; 4318 case 1: 4319 index = fieldFromInstruction(Insn, 6, 2); 4320 if (fieldFromInstruction(Insn, 4, 1)) 4321 align = 4; 4322 if (fieldFromInstruction(Insn, 5, 1)) 4323 inc = 2; 4324 break; 4325 case 2: 4326 if (fieldFromInstruction(Insn, 5, 1)) 4327 return MCDisassembler::Fail; // UNDEFINED 4328 index = fieldFromInstruction(Insn, 7, 1); 4329 if (fieldFromInstruction(Insn, 4, 1) != 0) 4330 align = 8; 4331 if (fieldFromInstruction(Insn, 6, 1)) 4332 inc = 2; 4333 break; 4334 } 4335 4336 if (Rm != 0xF) { // Writeback 4337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4338 return MCDisassembler::Fail; 4339 } 4340 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4341 return MCDisassembler::Fail; 4342 Inst.addOperand(MCOperand::CreateImm(align)); 4343 if (Rm != 0xF) { 4344 if (Rm != 0xD) { 4345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4346 return MCDisassembler::Fail; 4347 } else 4348 Inst.addOperand(MCOperand::CreateReg(0)); 4349 } 4350 4351 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4352 return MCDisassembler::Fail; 4353 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4354 return MCDisassembler::Fail; 4355 Inst.addOperand(MCOperand::CreateImm(index)); 4356 4357 return S; 4358} 4359 4360 4361static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4362 uint64_t Address, const void *Decoder) { 4363 DecodeStatus S = MCDisassembler::Success; 4364 4365 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4366 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4367 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4368 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4369 unsigned size = fieldFromInstruction(Insn, 10, 2); 4370 4371 unsigned align = 0; 4372 unsigned index = 0; 4373 unsigned inc = 1; 4374 switch (size) { 4375 default: 4376 return MCDisassembler::Fail; 4377 case 0: 4378 if (fieldFromInstruction(Insn, 4, 1)) 4379 return MCDisassembler::Fail; // UNDEFINED 4380 index = fieldFromInstruction(Insn, 5, 3); 4381 break; 4382 case 1: 4383 if (fieldFromInstruction(Insn, 4, 1)) 4384 return MCDisassembler::Fail; // UNDEFINED 4385 index = fieldFromInstruction(Insn, 6, 2); 4386 if (fieldFromInstruction(Insn, 5, 1)) 4387 inc = 2; 4388 break; 4389 case 2: 4390 if (fieldFromInstruction(Insn, 4, 2)) 4391 return MCDisassembler::Fail; // UNDEFINED 4392 index = fieldFromInstruction(Insn, 7, 1); 4393 if (fieldFromInstruction(Insn, 6, 1)) 4394 inc = 2; 4395 break; 4396 } 4397 4398 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4399 return MCDisassembler::Fail; 4400 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4401 return MCDisassembler::Fail; 4402 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4403 return MCDisassembler::Fail; 4404 4405 if (Rm != 0xF) { // Writeback 4406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4407 return MCDisassembler::Fail; 4408 } 4409 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4410 return MCDisassembler::Fail; 4411 Inst.addOperand(MCOperand::CreateImm(align)); 4412 if (Rm != 0xF) { 4413 if (Rm != 0xD) { 4414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4415 return MCDisassembler::Fail; 4416 } else 4417 Inst.addOperand(MCOperand::CreateReg(0)); 4418 } 4419 4420 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4421 return MCDisassembler::Fail; 4422 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4423 return MCDisassembler::Fail; 4424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4425 return MCDisassembler::Fail; 4426 Inst.addOperand(MCOperand::CreateImm(index)); 4427 4428 return S; 4429} 4430 4431static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4432 uint64_t Address, const void *Decoder) { 4433 DecodeStatus S = MCDisassembler::Success; 4434 4435 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4436 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4437 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4438 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4439 unsigned size = fieldFromInstruction(Insn, 10, 2); 4440 4441 unsigned align = 0; 4442 unsigned index = 0; 4443 unsigned inc = 1; 4444 switch (size) { 4445 default: 4446 return MCDisassembler::Fail; 4447 case 0: 4448 if (fieldFromInstruction(Insn, 4, 1)) 4449 return MCDisassembler::Fail; // UNDEFINED 4450 index = fieldFromInstruction(Insn, 5, 3); 4451 break; 4452 case 1: 4453 if (fieldFromInstruction(Insn, 4, 1)) 4454 return MCDisassembler::Fail; // UNDEFINED 4455 index = fieldFromInstruction(Insn, 6, 2); 4456 if (fieldFromInstruction(Insn, 5, 1)) 4457 inc = 2; 4458 break; 4459 case 2: 4460 if (fieldFromInstruction(Insn, 4, 2)) 4461 return MCDisassembler::Fail; // UNDEFINED 4462 index = fieldFromInstruction(Insn, 7, 1); 4463 if (fieldFromInstruction(Insn, 6, 1)) 4464 inc = 2; 4465 break; 4466 } 4467 4468 if (Rm != 0xF) { // Writeback 4469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4470 return MCDisassembler::Fail; 4471 } 4472 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4473 return MCDisassembler::Fail; 4474 Inst.addOperand(MCOperand::CreateImm(align)); 4475 if (Rm != 0xF) { 4476 if (Rm != 0xD) { 4477 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4478 return MCDisassembler::Fail; 4479 } else 4480 Inst.addOperand(MCOperand::CreateReg(0)); 4481 } 4482 4483 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4484 return MCDisassembler::Fail; 4485 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4486 return MCDisassembler::Fail; 4487 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4488 return MCDisassembler::Fail; 4489 Inst.addOperand(MCOperand::CreateImm(index)); 4490 4491 return S; 4492} 4493 4494 4495static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4496 uint64_t Address, const void *Decoder) { 4497 DecodeStatus S = MCDisassembler::Success; 4498 4499 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4500 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4501 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4502 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4503 unsigned size = fieldFromInstruction(Insn, 10, 2); 4504 4505 unsigned align = 0; 4506 unsigned index = 0; 4507 unsigned inc = 1; 4508 switch (size) { 4509 default: 4510 return MCDisassembler::Fail; 4511 case 0: 4512 if (fieldFromInstruction(Insn, 4, 1)) 4513 align = 4; 4514 index = fieldFromInstruction(Insn, 5, 3); 4515 break; 4516 case 1: 4517 if (fieldFromInstruction(Insn, 4, 1)) 4518 align = 8; 4519 index = fieldFromInstruction(Insn, 6, 2); 4520 if (fieldFromInstruction(Insn, 5, 1)) 4521 inc = 2; 4522 break; 4523 case 2: 4524 switch (fieldFromInstruction(Insn, 4, 2)) { 4525 case 0: 4526 align = 0; break; 4527 case 3: 4528 return MCDisassembler::Fail; 4529 default: 4530 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4531 } 4532 4533 index = fieldFromInstruction(Insn, 7, 1); 4534 if (fieldFromInstruction(Insn, 6, 1)) 4535 inc = 2; 4536 break; 4537 } 4538 4539 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4540 return MCDisassembler::Fail; 4541 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4542 return MCDisassembler::Fail; 4543 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4544 return MCDisassembler::Fail; 4545 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4546 return MCDisassembler::Fail; 4547 4548 if (Rm != 0xF) { // Writeback 4549 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4550 return MCDisassembler::Fail; 4551 } 4552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4553 return MCDisassembler::Fail; 4554 Inst.addOperand(MCOperand::CreateImm(align)); 4555 if (Rm != 0xF) { 4556 if (Rm != 0xD) { 4557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4558 return MCDisassembler::Fail; 4559 } else 4560 Inst.addOperand(MCOperand::CreateReg(0)); 4561 } 4562 4563 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4564 return MCDisassembler::Fail; 4565 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4566 return MCDisassembler::Fail; 4567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4568 return MCDisassembler::Fail; 4569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4570 return MCDisassembler::Fail; 4571 Inst.addOperand(MCOperand::CreateImm(index)); 4572 4573 return S; 4574} 4575 4576static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4577 uint64_t Address, const void *Decoder) { 4578 DecodeStatus S = MCDisassembler::Success; 4579 4580 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4581 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4582 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4583 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4584 unsigned size = fieldFromInstruction(Insn, 10, 2); 4585 4586 unsigned align = 0; 4587 unsigned index = 0; 4588 unsigned inc = 1; 4589 switch (size) { 4590 default: 4591 return MCDisassembler::Fail; 4592 case 0: 4593 if (fieldFromInstruction(Insn, 4, 1)) 4594 align = 4; 4595 index = fieldFromInstruction(Insn, 5, 3); 4596 break; 4597 case 1: 4598 if (fieldFromInstruction(Insn, 4, 1)) 4599 align = 8; 4600 index = fieldFromInstruction(Insn, 6, 2); 4601 if (fieldFromInstruction(Insn, 5, 1)) 4602 inc = 2; 4603 break; 4604 case 2: 4605 switch (fieldFromInstruction(Insn, 4, 2)) { 4606 case 0: 4607 align = 0; break; 4608 case 3: 4609 return MCDisassembler::Fail; 4610 default: 4611 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4612 } 4613 4614 index = fieldFromInstruction(Insn, 7, 1); 4615 if (fieldFromInstruction(Insn, 6, 1)) 4616 inc = 2; 4617 break; 4618 } 4619 4620 if (Rm != 0xF) { // Writeback 4621 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4622 return MCDisassembler::Fail; 4623 } 4624 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4625 return MCDisassembler::Fail; 4626 Inst.addOperand(MCOperand::CreateImm(align)); 4627 if (Rm != 0xF) { 4628 if (Rm != 0xD) { 4629 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4630 return MCDisassembler::Fail; 4631 } else 4632 Inst.addOperand(MCOperand::CreateReg(0)); 4633 } 4634 4635 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4636 return MCDisassembler::Fail; 4637 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4638 return MCDisassembler::Fail; 4639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4640 return MCDisassembler::Fail; 4641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4642 return MCDisassembler::Fail; 4643 Inst.addOperand(MCOperand::CreateImm(index)); 4644 4645 return S; 4646} 4647 4648static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4649 uint64_t Address, const void *Decoder) { 4650 DecodeStatus S = MCDisassembler::Success; 4651 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4652 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4653 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4654 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4655 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4656 4657 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4658 S = MCDisassembler::SoftFail; 4659 4660 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4661 return MCDisassembler::Fail; 4662 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4663 return MCDisassembler::Fail; 4664 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4665 return MCDisassembler::Fail; 4666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4667 return MCDisassembler::Fail; 4668 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4669 return MCDisassembler::Fail; 4670 4671 return S; 4672} 4673 4674static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4675 uint64_t Address, const void *Decoder) { 4676 DecodeStatus S = MCDisassembler::Success; 4677 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4678 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4679 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4680 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4681 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4682 4683 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4684 S = MCDisassembler::SoftFail; 4685 4686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4687 return MCDisassembler::Fail; 4688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4689 return MCDisassembler::Fail; 4690 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4691 return MCDisassembler::Fail; 4692 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4693 return MCDisassembler::Fail; 4694 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4695 return MCDisassembler::Fail; 4696 4697 return S; 4698} 4699 4700static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4701 uint64_t Address, const void *Decoder) { 4702 DecodeStatus S = MCDisassembler::Success; 4703 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4704 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4705 4706 if (pred == 0xF) { 4707 pred = 0xE; 4708 S = MCDisassembler::SoftFail; 4709 } 4710 4711 if (mask == 0x0) 4712 return MCDisassembler::Fail; 4713 4714 Inst.addOperand(MCOperand::CreateImm(pred)); 4715 Inst.addOperand(MCOperand::CreateImm(mask)); 4716 return S; 4717} 4718 4719static DecodeStatus 4720DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4721 uint64_t Address, const void *Decoder) { 4722 DecodeStatus S = MCDisassembler::Success; 4723 4724 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4725 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4726 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4727 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4728 unsigned W = fieldFromInstruction(Insn, 21, 1); 4729 unsigned U = fieldFromInstruction(Insn, 23, 1); 4730 unsigned P = fieldFromInstruction(Insn, 24, 1); 4731 bool writeback = (W == 1) | (P == 0); 4732 4733 addr |= (U << 8) | (Rn << 9); 4734 4735 if (writeback && (Rn == Rt || Rn == Rt2)) 4736 Check(S, MCDisassembler::SoftFail); 4737 if (Rt == Rt2) 4738 Check(S, MCDisassembler::SoftFail); 4739 4740 // Rt 4741 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4742 return MCDisassembler::Fail; 4743 // Rt2 4744 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4745 return MCDisassembler::Fail; 4746 // Writeback operand 4747 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4748 return MCDisassembler::Fail; 4749 // addr 4750 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4751 return MCDisassembler::Fail; 4752 4753 return S; 4754} 4755 4756static DecodeStatus 4757DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4758 uint64_t Address, const void *Decoder) { 4759 DecodeStatus S = MCDisassembler::Success; 4760 4761 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4762 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4763 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4764 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4765 unsigned W = fieldFromInstruction(Insn, 21, 1); 4766 unsigned U = fieldFromInstruction(Insn, 23, 1); 4767 unsigned P = fieldFromInstruction(Insn, 24, 1); 4768 bool writeback = (W == 1) | (P == 0); 4769 4770 addr |= (U << 8) | (Rn << 9); 4771 4772 if (writeback && (Rn == Rt || Rn == Rt2)) 4773 Check(S, MCDisassembler::SoftFail); 4774 4775 // Writeback operand 4776 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4777 return MCDisassembler::Fail; 4778 // Rt 4779 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4780 return MCDisassembler::Fail; 4781 // Rt2 4782 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4783 return MCDisassembler::Fail; 4784 // addr 4785 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4786 return MCDisassembler::Fail; 4787 4788 return S; 4789} 4790 4791static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4792 uint64_t Address, const void *Decoder) { 4793 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4794 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4795 if (sign1 != sign2) return MCDisassembler::Fail; 4796 4797 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4798 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4799 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4800 Val |= sign1 << 12; 4801 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4802 4803 return MCDisassembler::Success; 4804} 4805 4806static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4807 uint64_t Address, 4808 const void *Decoder) { 4809 DecodeStatus S = MCDisassembler::Success; 4810 4811 // Shift of "asr #32" is not allowed in Thumb2 mode. 4812 if (Val == 0x20) S = MCDisassembler::SoftFail; 4813 Inst.addOperand(MCOperand::CreateImm(Val)); 4814 return S; 4815} 4816 4817static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4818 uint64_t Address, const void *Decoder) { 4819 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4820 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4821 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4822 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4823 4824 if (pred == 0xF) 4825 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4826 4827 DecodeStatus S = MCDisassembler::Success; 4828 4829 if (Rt == Rn || Rn == Rt2) 4830 S = MCDisassembler::SoftFail; 4831 4832 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4833 return MCDisassembler::Fail; 4834 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4835 return MCDisassembler::Fail; 4836 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4837 return MCDisassembler::Fail; 4838 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4839 return MCDisassembler::Fail; 4840 4841 return S; 4842} 4843 4844static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4845 uint64_t Address, const void *Decoder) { 4846 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4847 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4848 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4849 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4850 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4851 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4852 unsigned op = fieldFromInstruction(Insn, 5, 1); 4853 4854 DecodeStatus S = MCDisassembler::Success; 4855 4856 // VMOVv2f32 is ambiguous with these decodings. 4857 if (!(imm & 0x38) && cmode == 0xF) { 4858 if (op == 1) return MCDisassembler::Fail; 4859 Inst.setOpcode(ARM::VMOVv2f32); 4860 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4861 } 4862 4863 if (!(imm & 0x20)) return MCDisassembler::Fail; 4864 4865 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4866 return MCDisassembler::Fail; 4867 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4868 return MCDisassembler::Fail; 4869 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4870 4871 return S; 4872} 4873 4874static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4875 uint64_t Address, const void *Decoder) { 4876 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4877 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4878 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4879 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4880 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4881 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4882 unsigned op = fieldFromInstruction(Insn, 5, 1); 4883 4884 DecodeStatus S = MCDisassembler::Success; 4885 4886 // VMOVv4f32 is ambiguous with these decodings. 4887 if (!(imm & 0x38) && cmode == 0xF) { 4888 if (op == 1) return MCDisassembler::Fail; 4889 Inst.setOpcode(ARM::VMOVv4f32); 4890 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4891 } 4892 4893 if (!(imm & 0x20)) return MCDisassembler::Fail; 4894 4895 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4896 return MCDisassembler::Fail; 4897 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4898 return MCDisassembler::Fail; 4899 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4900 4901 return S; 4902} 4903 4904static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4905 const void *Decoder) 4906{ 4907 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4908 if (Imm > 4) return MCDisassembler::Fail; 4909 Inst.addOperand(MCOperand::CreateImm(Imm)); 4910 return MCDisassembler::Success; 4911} 4912 4913static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4914 uint64_t Address, const void *Decoder) { 4915 DecodeStatus S = MCDisassembler::Success; 4916 4917 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4918 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4919 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4920 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4921 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4922 4923 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4924 S = MCDisassembler::SoftFail; 4925 4926 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4927 return MCDisassembler::Fail; 4928 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4929 return MCDisassembler::Fail; 4930 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4931 return MCDisassembler::Fail; 4932 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4933 return MCDisassembler::Fail; 4934 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4935 return MCDisassembler::Fail; 4936 4937 return S; 4938} 4939 4940static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4941 uint64_t Address, const void *Decoder) { 4942 4943 DecodeStatus S = MCDisassembler::Success; 4944 4945 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4946 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4947 unsigned cop = fieldFromInstruction(Val, 8, 4); 4948 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4949 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4950 4951 if ((cop & ~0x1) == 0xa) 4952 return MCDisassembler::Fail; 4953 4954 if (Rt == Rt2) 4955 S = MCDisassembler::SoftFail; 4956 4957 Inst.addOperand(MCOperand::CreateImm(cop)); 4958 Inst.addOperand(MCOperand::CreateImm(opc1)); 4959 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4960 return MCDisassembler::Fail; 4961 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4962 return MCDisassembler::Fail; 4963 Inst.addOperand(MCOperand::CreateImm(CRm)); 4964 4965 return S; 4966} 4967 4968