ARMDisassembler.cpp revision de317f40f7a9962372adea162a12ec35a628efa1
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "ARMDisassembler.h" 13#include "ARM.h" 14#include "ARMRegisterInfo.h" 15#include "MCTargetDesc/ARMAddressingModes.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "llvm/MC/EDInstInfo.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCContext.h" 21#include "llvm/Target/TargetRegistry.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/MemoryObject.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/raw_ostream.h" 26 27// Forward declare these because the autogenerated code will reference them. 28// Definitions are further down. 29static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136 137 138static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 139 uint64_t Address, const void *Decoder); 140static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 147 uint64_t Address, const void *Decoder); 148static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 149 uint64_t Address, const void *Decoder); 150static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 151 uint64_t Address, const void *Decoder); 152static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 153 uint64_t Address, const void *Decoder); 154static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 155 uint64_t Address, const void *Decoder); 156static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 157 uint64_t Address, const void *Decoder); 158static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 159 uint64_t Address, const void *Decoder); 160static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 161 uint64_t Address, const void *Decoder); 162static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 163 uint64_t Address, const void *Decoder); 164static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 167 uint64_t Address, const void *Decoder); 168static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 169 uint64_t Address, const void *Decoder); 170static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 171 uint64_t Address, const void *Decoder); 172static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 187#include "ARMGenDisassemblerTables.inc" 188#include "ARMGenInstrInfo.inc" 189#include "ARMGenEDInfo.inc" 190 191using namespace llvm; 192 193static MCDisassembler *createARMDisassembler(const Target &T) { 194 return new ARMDisassembler; 195} 196 197static MCDisassembler *createThumbDisassembler(const Target &T) { 198 return new ThumbDisassembler; 199} 200 201EDInstInfo *ARMDisassembler::getEDInfo() const { 202 return instInfoARM; 203} 204 205EDInstInfo *ThumbDisassembler::getEDInfo() const { 206 return instInfoARM; 207} 208 209 210bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 211 const MemoryObject &Region, 212 uint64_t Address,raw_ostream &os) const { 213 uint8_t bytes[4]; 214 215 // We want to read exactly 4 bytes of data. 216 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 217 return false; 218 219 // Encoded as a small-endian 32-bit word in the stream. 220 uint32_t insn = (bytes[3] << 24) | 221 (bytes[2] << 16) | 222 (bytes[1] << 8) | 223 (bytes[0] << 0); 224 225 // Calling the auto-generated decoder function. 226 bool result = decodeARMInstruction32(MI, insn, Address, this); 227 if (result) { 228 Size = 4; 229 return true; 230 } 231 232 // Instructions that are shared between ARM and Thumb modes. 233 // FIXME: This shouldn't really exist. It's an artifact of the 234 // fact that we fail to encode a few instructions properly for Thumb. 235 MI.clear(); 236 result = decodeCommonInstruction32(MI, insn, Address, this); 237 if (result) { 238 Size = 4; 239 return true; 240 } 241 242 // VFP and NEON instructions, similarly, are shared between ARM 243 // and Thumb modes. 244 MI.clear(); 245 result = decodeVFPInstruction32(MI, insn, Address, this); 246 if (result) { 247 Size = 4; 248 return true; 249 } 250 251 MI.clear(); 252 result = decodeNEONInstruction32(MI, insn, Address, this); 253 if (result) { 254 // Add a fake predicate operand, because we share these instruction 255 // definitions with Thumb2 where these instructions are predicable. 256 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 257 Size = 4; 258 return true; 259 } 260 261 MI.clear(); 262 263 return false; 264} 265 266namespace llvm { 267extern MCInstrDesc ARMInsts[]; 268} 269 270// Thumb1 instructions don't have explicit S bits. Rather, they 271// implicitly set CPSR. Since it's not represented in the encoding, the 272// auto-generated decoder won't inject the CPSR operand. We need to fix 273// that as a post-pass. 274static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 275 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 276 MCInst::iterator I = MI.begin(); 277 for (unsigned i = 0; i < MI.size(); ++i, ++I) { 278 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 279 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 280 return; 281 } 282 } 283 284 if (OpInfo[MI.size()].isOptionalDef() && 285 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 286 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 287} 288 289// Most Thumb instructions don't have explicit predicates in the 290// encoding, but rather get their predicates from IT context. We need 291// to fix up the predicate operands using this context information as a 292// post-pass. 293void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 294 // A few instructions actually have predicates encoded in them. Don't 295 // try to overwrite it if we're seeing one of those. 296 switch (MI.getOpcode()) { 297 case ARM::tBcc: 298 case ARM::t2Bcc: 299 return; 300 default: 301 break; 302 } 303 304 // If we're in an IT block, base the predicate on that. Otherwise, 305 // assume a predicate of AL. 306 unsigned CC; 307 if (ITBlock.size()) { 308 CC = ITBlock.back(); 309 ITBlock.pop_back(); 310 } else 311 CC = ARMCC::AL; 312 313 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 314 MCInst::iterator I = MI.begin(); 315 for (unsigned i = 0; i < MI.size(); ++i, ++I) { 316 if (OpInfo[i].isPredicate()) { 317 I = MI.insert(I, MCOperand::CreateImm(CC)); 318 ++I; 319 if (CC == ARMCC::AL) 320 MI.insert(I, MCOperand::CreateReg(0)); 321 else 322 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 323 return; 324 } 325 } 326 327 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 328 if (CC == ARMCC::AL) 329 MI.insert(MI.end(), MCOperand::CreateReg(0)); 330 else 331 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 332} 333 334// Thumb VFP instructions are a special case. Because we share their 335// encodings between ARM and Thumb modes, and they are predicable in ARM 336// mode, the auto-generated decoder will give them an (incorrect) 337// predicate operand. We need to rewrite these operands based on the IT 338// context as a post-pass. 339void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 340 unsigned CC; 341 if (ITBlock.size()) { 342 CC = ITBlock.back(); 343 ITBlock.pop_back(); 344 } else 345 CC = ARMCC::AL; 346 347 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 348 MCInst::iterator I = MI.begin(); 349 for (unsigned i = 0; i < MI.size(); ++i, ++I) { 350 if (OpInfo[i].isPredicate() ) { 351 I->setImm(CC); 352 ++I; 353 if (CC == ARMCC::AL) 354 I->setReg(0); 355 else 356 I->setReg(ARM::CPSR); 357 return; 358 } 359 } 360} 361 362 363bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 364 const MemoryObject &Region, 365 uint64_t Address,raw_ostream &os) const { 366 uint8_t bytes[4]; 367 368 // We want to read exactly 2 bytes of data. 369 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 370 return false; 371 372 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 373 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 374 if (result) { 375 Size = 2; 376 bool InITBlock = ITBlock.size(); 377 AddThumbPredicate(MI); 378 AddThumb1SBit(MI, InITBlock); 379 return true; 380 } 381 382 MI.clear(); 383 result = decodeThumb2Instruction16(MI, insn16, Address, this); 384 if (result) { 385 Size = 2; 386 AddThumbPredicate(MI); 387 388 // If we find an IT instruction, we need to parse its condition 389 // code and mask operands so that we can apply them correctly 390 // to the subsequent instructions. 391 if (MI.getOpcode() == ARM::t2IT) { 392 unsigned firstcond = MI.getOperand(0).getImm(); 393 uint32_t mask = MI.getOperand(1).getImm(); 394 unsigned zeros = CountTrailingZeros_32(mask); 395 mask >>= zeros+1; 396 397 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 398 if (firstcond ^ (mask & 1)) 399 ITBlock.push_back(firstcond ^ 1); 400 else 401 ITBlock.push_back(firstcond); 402 mask >>= 1; 403 } 404 ITBlock.push_back(firstcond); 405 } 406 407 return true; 408 } 409 410 // We want to read exactly 4 bytes of data. 411 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 412 return false; 413 414 uint32_t insn32 = (bytes[3] << 8) | 415 (bytes[2] << 0) | 416 (bytes[1] << 24) | 417 (bytes[0] << 16); 418 MI.clear(); 419 result = decodeThumbInstruction32(MI, insn32, Address, this); 420 if (result) { 421 Size = 4; 422 bool InITBlock = ITBlock.size(); 423 AddThumbPredicate(MI); 424 AddThumb1SBit(MI, InITBlock); 425 return true; 426 } 427 428 MI.clear(); 429 result = decodeThumb2Instruction32(MI, insn32, Address, this); 430 if (result) { 431 Size = 4; 432 AddThumbPredicate(MI); 433 return true; 434 } 435 436 MI.clear(); 437 result = decodeVFPInstruction32(MI, insn32, Address, this); 438 if (result) { 439 Size = 4; 440 UpdateThumbVFPPredicate(MI); 441 return true; 442 } 443 444 MI.clear(); 445 result = decodeCommonInstruction32(MI, insn32, Address, this); 446 if (result) { 447 Size = 4; 448 AddThumbPredicate(MI); 449 return true; 450 } 451 452 return false; 453} 454 455 456extern "C" void LLVMInitializeARMDisassembler() { 457 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 458 createARMDisassembler); 459 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 460 createThumbDisassembler); 461} 462 463static const unsigned GPRDecoderTable[] = { 464 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 465 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 466 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 467 ARM::R12, ARM::SP, ARM::LR, ARM::PC 468}; 469 470static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 471 uint64_t Address, const void *Decoder) { 472 if (RegNo > 15) 473 return false; 474 475 unsigned Register = GPRDecoderTable[RegNo]; 476 Inst.addOperand(MCOperand::CreateReg(Register)); 477 return true; 478} 479 480static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 481 uint64_t Address, const void *Decoder) { 482 if (RegNo == 15) return false; 483 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 484} 485 486static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 487 uint64_t Address, const void *Decoder) { 488 if (RegNo > 7) 489 return false; 490 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 491} 492 493static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 494 uint64_t Address, const void *Decoder) { 495 unsigned Register = 0; 496 switch (RegNo) { 497 case 0: 498 Register = ARM::R0; 499 break; 500 case 1: 501 Register = ARM::R1; 502 break; 503 case 2: 504 Register = ARM::R2; 505 break; 506 case 3: 507 Register = ARM::R3; 508 break; 509 case 9: 510 Register = ARM::R9; 511 break; 512 case 12: 513 Register = ARM::R12; 514 break; 515 default: 516 return false; 517 } 518 519 Inst.addOperand(MCOperand::CreateReg(Register)); 520 return true; 521} 522 523static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 524 uint64_t Address, const void *Decoder) { 525 if (RegNo == 13 || RegNo == 15) return false; 526 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 527} 528 529static const unsigned SPRDecoderTable[] = { 530 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 531 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 532 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 533 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 534 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 535 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 536 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 537 ARM::S28, ARM::S29, ARM::S30, ARM::S31 538}; 539 540static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 541 uint64_t Address, const void *Decoder) { 542 if (RegNo > 31) 543 return false; 544 545 unsigned Register = SPRDecoderTable[RegNo]; 546 Inst.addOperand(MCOperand::CreateReg(Register)); 547 return true; 548} 549 550static const unsigned DPRDecoderTable[] = { 551 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 552 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 553 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 554 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 555 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 556 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 557 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 558 ARM::D28, ARM::D29, ARM::D30, ARM::D31 559}; 560 561static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 562 uint64_t Address, const void *Decoder) { 563 if (RegNo > 31) 564 return false; 565 566 unsigned Register = DPRDecoderTable[RegNo]; 567 Inst.addOperand(MCOperand::CreateReg(Register)); 568 return true; 569} 570 571static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 572 uint64_t Address, const void *Decoder) { 573 if (RegNo > 7) 574 return false; 575 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 576} 577 578static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 579 uint64_t Address, const void *Decoder) { 580 if (RegNo > 15) 581 return false; 582 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 583} 584 585static const unsigned QPRDecoderTable[] = { 586 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 587 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 588 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 589 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 590}; 591 592 593static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 594 uint64_t Address, const void *Decoder) { 595 if (RegNo > 31) 596 return false; 597 RegNo >>= 1; 598 599 unsigned Register = QPRDecoderTable[RegNo]; 600 Inst.addOperand(MCOperand::CreateReg(Register)); 601 return true; 602} 603 604static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 605 uint64_t Address, const void *Decoder) { 606 if (Val == 0xF) return false; 607 // AL predicate is not allowed on Thumb1 branches. 608 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 609 return false; 610 Inst.addOperand(MCOperand::CreateImm(Val)); 611 if (Val == ARMCC::AL) { 612 Inst.addOperand(MCOperand::CreateReg(0)); 613 } else 614 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 615 return true; 616} 617 618static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 619 uint64_t Address, const void *Decoder) { 620 if (Val) 621 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 622 else 623 Inst.addOperand(MCOperand::CreateReg(0)); 624 return true; 625} 626 627static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 628 uint64_t Address, const void *Decoder) { 629 uint32_t imm = Val & 0xFF; 630 uint32_t rot = (Val & 0xF00) >> 7; 631 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 632 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 633 return true; 634} 635 636static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 637 uint64_t Address, const void *Decoder) { 638 Val <<= 2; 639 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 640 return true; 641} 642 643static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 644 uint64_t Address, const void *Decoder) { 645 646 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 647 unsigned type = fieldFromInstruction32(Val, 5, 2); 648 unsigned imm = fieldFromInstruction32(Val, 7, 5); 649 650 // Register-immediate 651 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 652 653 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 654 switch (type) { 655 case 0: 656 Shift = ARM_AM::lsl; 657 break; 658 case 1: 659 Shift = ARM_AM::lsr; 660 break; 661 case 2: 662 Shift = ARM_AM::asr; 663 break; 664 case 3: 665 Shift = ARM_AM::ror; 666 break; 667 } 668 669 if (Shift == ARM_AM::ror && imm == 0) 670 Shift = ARM_AM::rrx; 671 672 unsigned Op = Shift | (imm << 3); 673 Inst.addOperand(MCOperand::CreateImm(Op)); 674 675 return true; 676} 677 678static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 679 uint64_t Address, const void *Decoder) { 680 681 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 682 unsigned type = fieldFromInstruction32(Val, 5, 2); 683 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 684 685 // Register-register 686 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 687 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 688 689 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 690 switch (type) { 691 case 0: 692 Shift = ARM_AM::lsl; 693 break; 694 case 1: 695 Shift = ARM_AM::lsr; 696 break; 697 case 2: 698 Shift = ARM_AM::asr; 699 break; 700 case 3: 701 Shift = ARM_AM::ror; 702 break; 703 } 704 705 Inst.addOperand(MCOperand::CreateImm(Shift)); 706 707 return true; 708} 709 710static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 711 uint64_t Address, const void *Decoder) { 712 for (unsigned i = 0; i < 16; ++i) { 713 if (Val & (1 << i)) 714 DecodeGPRRegisterClass(Inst, i, Address, Decoder); 715 } 716 717 return true; 718} 719 720static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 721 uint64_t Address, const void *Decoder) { 722 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 723 unsigned regs = Val & 0xFF; 724 725 DecodeSPRRegisterClass(Inst, Vd, Address, Decoder); 726 for (unsigned i = 0; i < (regs - 1); ++i) 727 DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder); 728 729 return true; 730} 731 732static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 733 uint64_t Address, const void *Decoder) { 734 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 735 unsigned regs = (Val & 0xFF) / 2; 736 737 DecodeDPRRegisterClass(Inst, Vd, Address, Decoder); 738 for (unsigned i = 0; i < (regs - 1); ++i) 739 DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder); 740 741 return true; 742} 743 744static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 745 uint64_t Address, const void *Decoder) { 746 unsigned msb = fieldFromInstruction32(Val, 5, 5); 747 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 748 uint32_t msb_mask = (1 << (msb+1)) - 1; 749 uint32_t lsb_mask = (1 << lsb) - 1; 750 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 751 return true; 752} 753 754static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 755 uint64_t Address, const void *Decoder) { 756 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 757 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 758 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 759 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 760 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 761 unsigned U = fieldFromInstruction32(Insn, 23, 1); 762 763 switch (Inst.getOpcode()) { 764 case ARM::LDC_OFFSET: 765 case ARM::LDC_PRE: 766 case ARM::LDC_POST: 767 case ARM::LDC_OPTION: 768 case ARM::LDCL_OFFSET: 769 case ARM::LDCL_PRE: 770 case ARM::LDCL_POST: 771 case ARM::LDCL_OPTION: 772 case ARM::STC_OFFSET: 773 case ARM::STC_PRE: 774 case ARM::STC_POST: 775 case ARM::STC_OPTION: 776 case ARM::STCL_OFFSET: 777 case ARM::STCL_PRE: 778 case ARM::STCL_POST: 779 case ARM::STCL_OPTION: 780 if (coproc == 0xA || coproc == 0xB) 781 return false; 782 break; 783 default: 784 break; 785 } 786 787 Inst.addOperand(MCOperand::CreateImm(coproc)); 788 Inst.addOperand(MCOperand::CreateImm(CRd)); 789 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 790 switch (Inst.getOpcode()) { 791 case ARM::LDC_OPTION: 792 case ARM::LDCL_OPTION: 793 case ARM::LDC2_OPTION: 794 case ARM::LDC2L_OPTION: 795 case ARM::STC_OPTION: 796 case ARM::STCL_OPTION: 797 case ARM::STC2_OPTION: 798 case ARM::STC2L_OPTION: 799 case ARM::LDCL_POST: 800 case ARM::STCL_POST: 801 break; 802 default: 803 Inst.addOperand(MCOperand::CreateReg(0)); 804 break; 805 } 806 807 unsigned P = fieldFromInstruction32(Insn, 24, 1); 808 unsigned W = fieldFromInstruction32(Insn, 21, 1); 809 810 bool writeback = (P == 0) || (W == 1); 811 unsigned idx_mode = 0; 812 if (P && writeback) 813 idx_mode = ARMII::IndexModePre; 814 else if (!P && writeback) 815 idx_mode = ARMII::IndexModePost; 816 817 switch (Inst.getOpcode()) { 818 case ARM::LDCL_POST: 819 case ARM::STCL_POST: 820 imm |= U << 8; 821 case ARM::LDC_OPTION: 822 case ARM::LDCL_OPTION: 823 case ARM::LDC2_OPTION: 824 case ARM::LDC2L_OPTION: 825 case ARM::STC_OPTION: 826 case ARM::STCL_OPTION: 827 case ARM::STC2_OPTION: 828 case ARM::STC2L_OPTION: 829 Inst.addOperand(MCOperand::CreateImm(imm)); 830 break; 831 default: 832 if (U) 833 Inst.addOperand(MCOperand::CreateImm( 834 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 835 else 836 Inst.addOperand(MCOperand::CreateImm( 837 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 838 break; 839 } 840 841 switch (Inst.getOpcode()) { 842 case ARM::LDC_OFFSET: 843 case ARM::LDC_PRE: 844 case ARM::LDC_POST: 845 case ARM::LDC_OPTION: 846 case ARM::LDCL_OFFSET: 847 case ARM::LDCL_PRE: 848 case ARM::LDCL_POST: 849 case ARM::LDCL_OPTION: 850 case ARM::STC_OFFSET: 851 case ARM::STC_PRE: 852 case ARM::STC_POST: 853 case ARM::STC_OPTION: 854 case ARM::STCL_OFFSET: 855 case ARM::STCL_PRE: 856 case ARM::STCL_POST: 857 case ARM::STCL_OPTION: 858 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 859 break; 860 default: 861 break; 862 } 863 864 return true; 865} 866 867static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 868 uint64_t Address, const void *Decoder) { 869 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 870 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 871 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 872 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 873 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 874 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 875 unsigned P = fieldFromInstruction32(Insn, 24, 1); 876 unsigned W = fieldFromInstruction32(Insn, 21, 1); 877 878 // On stores, the writeback operand precedes Rt. 879 switch (Inst.getOpcode()) { 880 case ARM::STR_POST_IMM: 881 case ARM::STR_POST_REG: 882 case ARM::STRTr: 883 case ARM::STRTi: 884 case ARM::STRBTr: 885 case ARM::STRBTi: 886 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 887 break; 888 default: 889 break; 890 } 891 892 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder); 893 894 // On loads, the writeback operand comes after Rt. 895 switch (Inst.getOpcode()) { 896 case ARM::LDR_POST_IMM: 897 case ARM::LDR_POST_REG: 898 case ARM::LDR_PRE: 899 case ARM::LDRBT_POST_REG: 900 case ARM::LDRBT_POST_IMM: 901 case ARM::LDRTr: 902 case ARM::LDRTi: 903 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 904 break; 905 default: 906 break; 907 } 908 909 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 910 911 ARM_AM::AddrOpc Op = ARM_AM::add; 912 if (!fieldFromInstruction32(Insn, 23, 1)) 913 Op = ARM_AM::sub; 914 915 bool writeback = (P == 0) || (W == 1); 916 unsigned idx_mode = 0; 917 if (P && writeback) 918 idx_mode = ARMII::IndexModePre; 919 else if (!P && writeback) 920 idx_mode = ARMII::IndexModePost; 921 922 if (reg) { 923 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 924 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 925 switch( fieldFromInstruction32(Insn, 5, 2)) { 926 case 0: 927 Opc = ARM_AM::lsl; 928 break; 929 case 1: 930 Opc = ARM_AM::lsr; 931 break; 932 case 2: 933 Opc = ARM_AM::asr; 934 break; 935 case 3: 936 Opc = ARM_AM::ror; 937 break; 938 default: 939 return false; 940 } 941 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 942 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 943 944 Inst.addOperand(MCOperand::CreateImm(imm)); 945 } else { 946 Inst.addOperand(MCOperand::CreateReg(0)); 947 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 948 Inst.addOperand(MCOperand::CreateImm(tmp)); 949 } 950 951 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 952 953 return true; 954} 955 956static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 957 uint64_t Address, const void *Decoder) { 958 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 959 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 960 unsigned type = fieldFromInstruction32(Val, 5, 2); 961 unsigned imm = fieldFromInstruction32(Val, 7, 5); 962 unsigned U = fieldFromInstruction32(Val, 12, 1); 963 964 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 965 switch (type) { 966 case 0: 967 ShOp = ARM_AM::lsl; 968 break; 969 case 1: 970 ShOp = ARM_AM::lsr; 971 break; 972 case 2: 973 ShOp = ARM_AM::asr; 974 break; 975 case 3: 976 ShOp = ARM_AM::ror; 977 break; 978 } 979 980 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 981 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 982 unsigned shift; 983 if (U) 984 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 985 else 986 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 987 Inst.addOperand(MCOperand::CreateImm(shift)); 988 989 return true; 990} 991 992static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 993 uint64_t Address, const void *Decoder) { 994 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 995 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 996 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 997 unsigned type = fieldFromInstruction32(Insn, 22, 1); 998 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 999 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1000 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1001 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1002 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1003 1004 bool writeback = (W == 1) | (P == 0); 1005 if (writeback) { // Writeback 1006 if (P) 1007 U |= ARMII::IndexModePre << 9; 1008 else 1009 U |= ARMII::IndexModePost << 9; 1010 1011 // On stores, the writeback operand precedes Rt. 1012 switch (Inst.getOpcode()) { 1013 case ARM::STRD: 1014 case ARM::STRD_PRE: 1015 case ARM::STRD_POST: 1016 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1017 break; 1018 default: 1019 break; 1020 } 1021 } 1022 1023 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder); 1024 switch (Inst.getOpcode()) { 1025 case ARM::STRD: 1026 case ARM::STRD_PRE: 1027 case ARM::STRD_POST: 1028 case ARM::LDRD: 1029 case ARM::LDRD_PRE: 1030 case ARM::LDRD_POST: 1031 DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder); 1032 break; 1033 default: 1034 break; 1035 } 1036 1037 if (writeback) { 1038 // On loads, the writeback operand comes after Rt. 1039 switch (Inst.getOpcode()) { 1040 case ARM::LDRD: 1041 case ARM::LDRD_PRE: 1042 case ARM::LDRD_POST: 1043 case ARM::LDRHTr: 1044 case ARM::LDRSBTr: 1045 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1046 break; 1047 default: 1048 break; 1049 } 1050 } 1051 1052 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1053 1054 if (type) { 1055 Inst.addOperand(MCOperand::CreateReg(0)); 1056 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1057 } else { 1058 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1059 Inst.addOperand(MCOperand::CreateImm(U)); 1060 } 1061 1062 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1063 1064 return true; 1065} 1066 1067static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1068 uint64_t Address, const void *Decoder) { 1069 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1070 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1071 1072 switch (mode) { 1073 case 0: 1074 mode = ARM_AM::da; 1075 break; 1076 case 1: 1077 mode = ARM_AM::ia; 1078 break; 1079 case 2: 1080 mode = ARM_AM::db; 1081 break; 1082 case 3: 1083 mode = ARM_AM::ib; 1084 break; 1085 } 1086 1087 Inst.addOperand(MCOperand::CreateImm(mode)); 1088 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1089 1090 return true; 1091} 1092 1093static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1094 unsigned Insn, 1095 uint64_t Address, const void *Decoder) { 1096 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1097 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1098 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1099 1100 if (pred == 0xF) { 1101 switch (Inst.getOpcode()) { 1102 case ARM::STMDA: 1103 Inst.setOpcode(ARM::RFEDA); 1104 break; 1105 case ARM::STMDA_UPD: 1106 Inst.setOpcode(ARM::RFEDA_UPD); 1107 break; 1108 case ARM::STMDB: 1109 Inst.setOpcode(ARM::RFEDB); 1110 break; 1111 case ARM::STMDB_UPD: 1112 Inst.setOpcode(ARM::RFEDB_UPD); 1113 break; 1114 case ARM::STMIA: 1115 Inst.setOpcode(ARM::RFEIA); 1116 break; 1117 case ARM::STMIA_UPD: 1118 Inst.setOpcode(ARM::RFEIA_UPD); 1119 break; 1120 case ARM::STMIB: 1121 Inst.setOpcode(ARM::RFEIB); 1122 break; 1123 case ARM::STMIB_UPD: 1124 Inst.setOpcode(ARM::RFEIB_UPD); 1125 break; 1126 1127 } 1128 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1129 } 1130 1131 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1132 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); // Tied 1133 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1134 DecodeRegListOperand(Inst, reglist, Address, Decoder); 1135 1136 return true; 1137} 1138 1139static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1140 uint64_t Address, const void *Decoder) { 1141 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1142 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1143 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1144 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1145 1146 // imod == '01' --> UNPREDICTABLE 1147 if (imod == 1) return false; 1148 1149 if (M && mode && imod && iflags) { 1150 Inst.setOpcode(ARM::CPS3p); 1151 Inst.addOperand(MCOperand::CreateImm(imod)); 1152 Inst.addOperand(MCOperand::CreateImm(iflags)); 1153 Inst.addOperand(MCOperand::CreateImm(mode)); 1154 return true; 1155 } else if (!mode && !M) { 1156 Inst.setOpcode(ARM::CPS2p); 1157 Inst.addOperand(MCOperand::CreateImm(imod)); 1158 Inst.addOperand(MCOperand::CreateImm(iflags)); 1159 return true; 1160 } else if (!imod && !iflags && M) { 1161 Inst.setOpcode(ARM::CPS1p); 1162 Inst.addOperand(MCOperand::CreateImm(mode)); 1163 return true; 1164 } 1165 1166 return false; 1167} 1168 1169static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1170 uint64_t Address, const void *Decoder) { 1171 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1172 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1173 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1174 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1175 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1176 1177 if (pred == 0xF) 1178 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1179 1180 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); 1181 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1182 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1183 DecodeGPRRegisterClass(Inst, Ra, Address, Decoder); 1184 1185 return true; 1186} 1187 1188static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1189 uint64_t Address, const void *Decoder) { 1190 unsigned add = fieldFromInstruction32(Val, 12, 1); 1191 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1192 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1193 1194 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1195 1196 if (!add) imm *= -1; 1197 if (imm == 0 && !add) imm = INT32_MIN; 1198 Inst.addOperand(MCOperand::CreateImm(imm)); 1199 1200 return true; 1201} 1202 1203static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1204 uint64_t Address, const void *Decoder) { 1205 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1206 unsigned U = fieldFromInstruction32(Val, 8, 1); 1207 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1208 1209 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1210 1211 if (U) 1212 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1213 else 1214 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1215 1216 return true; 1217} 1218 1219static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1220 uint64_t Address, const void *Decoder) { 1221 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1222} 1223 1224static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1225 uint64_t Address, const void *Decoder) { 1226 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1227 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1228 1229 if (pred == 0xF) { 1230 Inst.setOpcode(ARM::BLXi); 1231 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1232 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1233 return true; 1234 } 1235 1236 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1237 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1238 1239 return true; 1240} 1241 1242 1243static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1244 uint64_t Address, const void *Decoder) { 1245 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1246 return true; 1247} 1248 1249static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1250 uint64_t Address, const void *Decoder) { 1251 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1252 unsigned align = fieldFromInstruction32(Val, 4, 2); 1253 1254 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1255 if (!align) 1256 Inst.addOperand(MCOperand::CreateImm(0)); 1257 else 1258 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1259 1260 return true; 1261} 1262 1263static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1264 uint64_t Address, const void *Decoder) { 1265 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1266 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1267 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1268 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1269 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1270 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1271 1272 // First output register 1273 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1274 1275 // Second output register 1276 switch (Inst.getOpcode()) { 1277 case ARM::VLD1q8: 1278 case ARM::VLD1q16: 1279 case ARM::VLD1q32: 1280 case ARM::VLD1q64: 1281 case ARM::VLD1q8_UPD: 1282 case ARM::VLD1q16_UPD: 1283 case ARM::VLD1q32_UPD: 1284 case ARM::VLD1q64_UPD: 1285 case ARM::VLD1d8T: 1286 case ARM::VLD1d16T: 1287 case ARM::VLD1d32T: 1288 case ARM::VLD1d64T: 1289 case ARM::VLD1d8T_UPD: 1290 case ARM::VLD1d16T_UPD: 1291 case ARM::VLD1d32T_UPD: 1292 case ARM::VLD1d64T_UPD: 1293 case ARM::VLD1d8Q: 1294 case ARM::VLD1d16Q: 1295 case ARM::VLD1d32Q: 1296 case ARM::VLD1d64Q: 1297 case ARM::VLD1d8Q_UPD: 1298 case ARM::VLD1d16Q_UPD: 1299 case ARM::VLD1d32Q_UPD: 1300 case ARM::VLD1d64Q_UPD: 1301 case ARM::VLD2d8: 1302 case ARM::VLD2d16: 1303 case ARM::VLD2d32: 1304 case ARM::VLD2d8_UPD: 1305 case ARM::VLD2d16_UPD: 1306 case ARM::VLD2d32_UPD: 1307 case ARM::VLD2q8: 1308 case ARM::VLD2q16: 1309 case ARM::VLD2q32: 1310 case ARM::VLD2q8_UPD: 1311 case ARM::VLD2q16_UPD: 1312 case ARM::VLD2q32_UPD: 1313 case ARM::VLD3d8: 1314 case ARM::VLD3d16: 1315 case ARM::VLD3d32: 1316 case ARM::VLD3d8_UPD: 1317 case ARM::VLD3d16_UPD: 1318 case ARM::VLD3d32_UPD: 1319 case ARM::VLD4d8: 1320 case ARM::VLD4d16: 1321 case ARM::VLD4d32: 1322 case ARM::VLD4d8_UPD: 1323 case ARM::VLD4d16_UPD: 1324 case ARM::VLD4d32_UPD: 1325 DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder); 1326 break; 1327 case ARM::VLD2b8: 1328 case ARM::VLD2b16: 1329 case ARM::VLD2b32: 1330 case ARM::VLD2b8_UPD: 1331 case ARM::VLD2b16_UPD: 1332 case ARM::VLD2b32_UPD: 1333 case ARM::VLD3q8: 1334 case ARM::VLD3q16: 1335 case ARM::VLD3q32: 1336 case ARM::VLD3q8_UPD: 1337 case ARM::VLD3q16_UPD: 1338 case ARM::VLD3q32_UPD: 1339 case ARM::VLD4q8: 1340 case ARM::VLD4q16: 1341 case ARM::VLD4q32: 1342 case ARM::VLD4q8_UPD: 1343 case ARM::VLD4q16_UPD: 1344 case ARM::VLD4q32_UPD: 1345 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1346 default: 1347 break; 1348 } 1349 1350 // Third output register 1351 switch(Inst.getOpcode()) { 1352 case ARM::VLD1d8T: 1353 case ARM::VLD1d16T: 1354 case ARM::VLD1d32T: 1355 case ARM::VLD1d64T: 1356 case ARM::VLD1d8T_UPD: 1357 case ARM::VLD1d16T_UPD: 1358 case ARM::VLD1d32T_UPD: 1359 case ARM::VLD1d64T_UPD: 1360 case ARM::VLD1d8Q: 1361 case ARM::VLD1d16Q: 1362 case ARM::VLD1d32Q: 1363 case ARM::VLD1d64Q: 1364 case ARM::VLD1d8Q_UPD: 1365 case ARM::VLD1d16Q_UPD: 1366 case ARM::VLD1d32Q_UPD: 1367 case ARM::VLD1d64Q_UPD: 1368 case ARM::VLD2q8: 1369 case ARM::VLD2q16: 1370 case ARM::VLD2q32: 1371 case ARM::VLD2q8_UPD: 1372 case ARM::VLD2q16_UPD: 1373 case ARM::VLD2q32_UPD: 1374 case ARM::VLD3d8: 1375 case ARM::VLD3d16: 1376 case ARM::VLD3d32: 1377 case ARM::VLD3d8_UPD: 1378 case ARM::VLD3d16_UPD: 1379 case ARM::VLD3d32_UPD: 1380 case ARM::VLD4d8: 1381 case ARM::VLD4d16: 1382 case ARM::VLD4d32: 1383 case ARM::VLD4d8_UPD: 1384 case ARM::VLD4d16_UPD: 1385 case ARM::VLD4d32_UPD: 1386 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1387 break; 1388 case ARM::VLD3q8: 1389 case ARM::VLD3q16: 1390 case ARM::VLD3q32: 1391 case ARM::VLD3q8_UPD: 1392 case ARM::VLD3q16_UPD: 1393 case ARM::VLD3q32_UPD: 1394 case ARM::VLD4q8: 1395 case ARM::VLD4q16: 1396 case ARM::VLD4q32: 1397 case ARM::VLD4q8_UPD: 1398 case ARM::VLD4q16_UPD: 1399 case ARM::VLD4q32_UPD: 1400 DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder); 1401 break; 1402 default: 1403 break; 1404 } 1405 1406 // Fourth output register 1407 switch (Inst.getOpcode()) { 1408 case ARM::VLD1d8Q: 1409 case ARM::VLD1d16Q: 1410 case ARM::VLD1d32Q: 1411 case ARM::VLD1d64Q: 1412 case ARM::VLD1d8Q_UPD: 1413 case ARM::VLD1d16Q_UPD: 1414 case ARM::VLD1d32Q_UPD: 1415 case ARM::VLD1d64Q_UPD: 1416 case ARM::VLD2q8: 1417 case ARM::VLD2q16: 1418 case ARM::VLD2q32: 1419 case ARM::VLD2q8_UPD: 1420 case ARM::VLD2q16_UPD: 1421 case ARM::VLD2q32_UPD: 1422 case ARM::VLD4d8: 1423 case ARM::VLD4d16: 1424 case ARM::VLD4d32: 1425 case ARM::VLD4d8_UPD: 1426 case ARM::VLD4d16_UPD: 1427 case ARM::VLD4d32_UPD: 1428 DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder); 1429 break; 1430 case ARM::VLD4q8: 1431 case ARM::VLD4q16: 1432 case ARM::VLD4q32: 1433 case ARM::VLD4q8_UPD: 1434 case ARM::VLD4q16_UPD: 1435 case ARM::VLD4q32_UPD: 1436 DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder); 1437 break; 1438 default: 1439 break; 1440 } 1441 1442 // Writeback operand 1443 switch (Inst.getOpcode()) { 1444 case ARM::VLD1d8_UPD: 1445 case ARM::VLD1d16_UPD: 1446 case ARM::VLD1d32_UPD: 1447 case ARM::VLD1d64_UPD: 1448 case ARM::VLD1q8_UPD: 1449 case ARM::VLD1q16_UPD: 1450 case ARM::VLD1q32_UPD: 1451 case ARM::VLD1q64_UPD: 1452 case ARM::VLD1d8T_UPD: 1453 case ARM::VLD1d16T_UPD: 1454 case ARM::VLD1d32T_UPD: 1455 case ARM::VLD1d64T_UPD: 1456 case ARM::VLD1d8Q_UPD: 1457 case ARM::VLD1d16Q_UPD: 1458 case ARM::VLD1d32Q_UPD: 1459 case ARM::VLD1d64Q_UPD: 1460 case ARM::VLD2d8_UPD: 1461 case ARM::VLD2d16_UPD: 1462 case ARM::VLD2d32_UPD: 1463 case ARM::VLD2q8_UPD: 1464 case ARM::VLD2q16_UPD: 1465 case ARM::VLD2q32_UPD: 1466 case ARM::VLD2b8_UPD: 1467 case ARM::VLD2b16_UPD: 1468 case ARM::VLD2b32_UPD: 1469 case ARM::VLD3d8_UPD: 1470 case ARM::VLD3d16_UPD: 1471 case ARM::VLD3d32_UPD: 1472 case ARM::VLD3q8_UPD: 1473 case ARM::VLD3q16_UPD: 1474 case ARM::VLD3q32_UPD: 1475 case ARM::VLD4d8_UPD: 1476 case ARM::VLD4d16_UPD: 1477 case ARM::VLD4d32_UPD: 1478 case ARM::VLD4q8_UPD: 1479 case ARM::VLD4q16_UPD: 1480 case ARM::VLD4q32_UPD: 1481 DecodeGPRRegisterClass(Inst, wb, Address, Decoder); 1482 break; 1483 default: 1484 break; 1485 } 1486 1487 // AddrMode6 Base (register+alignment) 1488 DecodeAddrMode6Operand(Inst, Rn, Address, Decoder); 1489 1490 // AddrMode6 Offset (register) 1491 if (Rm == 0xD) 1492 Inst.addOperand(MCOperand::CreateReg(0)); 1493 else if (Rm != 0xF) 1494 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1495 1496 return true; 1497} 1498 1499static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1500 uint64_t Address, const void *Decoder) { 1501 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1502 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1503 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1504 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1505 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1506 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1507 1508 // Writeback Operand 1509 switch (Inst.getOpcode()) { 1510 case ARM::VST1d8_UPD: 1511 case ARM::VST1d16_UPD: 1512 case ARM::VST1d32_UPD: 1513 case ARM::VST1d64_UPD: 1514 case ARM::VST1q8_UPD: 1515 case ARM::VST1q16_UPD: 1516 case ARM::VST1q32_UPD: 1517 case ARM::VST1q64_UPD: 1518 case ARM::VST1d8T_UPD: 1519 case ARM::VST1d16T_UPD: 1520 case ARM::VST1d32T_UPD: 1521 case ARM::VST1d64T_UPD: 1522 case ARM::VST1d8Q_UPD: 1523 case ARM::VST1d16Q_UPD: 1524 case ARM::VST1d32Q_UPD: 1525 case ARM::VST1d64Q_UPD: 1526 case ARM::VST2d8_UPD: 1527 case ARM::VST2d16_UPD: 1528 case ARM::VST2d32_UPD: 1529 case ARM::VST2q8_UPD: 1530 case ARM::VST2q16_UPD: 1531 case ARM::VST2q32_UPD: 1532 case ARM::VST2b8_UPD: 1533 case ARM::VST2b16_UPD: 1534 case ARM::VST2b32_UPD: 1535 case ARM::VST3d8_UPD: 1536 case ARM::VST3d16_UPD: 1537 case ARM::VST3d32_UPD: 1538 case ARM::VST3q8_UPD: 1539 case ARM::VST3q16_UPD: 1540 case ARM::VST3q32_UPD: 1541 case ARM::VST4d8_UPD: 1542 case ARM::VST4d16_UPD: 1543 case ARM::VST4d32_UPD: 1544 case ARM::VST4q8_UPD: 1545 case ARM::VST4q16_UPD: 1546 case ARM::VST4q32_UPD: 1547 DecodeGPRRegisterClass(Inst, wb, Address, Decoder); 1548 break; 1549 default: 1550 break; 1551 } 1552 1553 // AddrMode6 Base (register+alignment) 1554 DecodeAddrMode6Operand(Inst, Rn, Address, Decoder); 1555 1556 // AddrMode6 Offset (register) 1557 if (Rm == 0xD) 1558 Inst.addOperand(MCOperand::CreateReg(0)); 1559 else if (Rm != 0xF) 1560 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1561 1562 // First input register 1563 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1564 1565 // Second input register 1566 switch (Inst.getOpcode()) { 1567 case ARM::VST1q8: 1568 case ARM::VST1q16: 1569 case ARM::VST1q32: 1570 case ARM::VST1q64: 1571 case ARM::VST1q8_UPD: 1572 case ARM::VST1q16_UPD: 1573 case ARM::VST1q32_UPD: 1574 case ARM::VST1q64_UPD: 1575 case ARM::VST1d8T: 1576 case ARM::VST1d16T: 1577 case ARM::VST1d32T: 1578 case ARM::VST1d64T: 1579 case ARM::VST1d8T_UPD: 1580 case ARM::VST1d16T_UPD: 1581 case ARM::VST1d32T_UPD: 1582 case ARM::VST1d64T_UPD: 1583 case ARM::VST1d8Q: 1584 case ARM::VST1d16Q: 1585 case ARM::VST1d32Q: 1586 case ARM::VST1d64Q: 1587 case ARM::VST1d8Q_UPD: 1588 case ARM::VST1d16Q_UPD: 1589 case ARM::VST1d32Q_UPD: 1590 case ARM::VST1d64Q_UPD: 1591 case ARM::VST2d8: 1592 case ARM::VST2d16: 1593 case ARM::VST2d32: 1594 case ARM::VST2d8_UPD: 1595 case ARM::VST2d16_UPD: 1596 case ARM::VST2d32_UPD: 1597 case ARM::VST2q8: 1598 case ARM::VST2q16: 1599 case ARM::VST2q32: 1600 case ARM::VST2q8_UPD: 1601 case ARM::VST2q16_UPD: 1602 case ARM::VST2q32_UPD: 1603 case ARM::VST3d8: 1604 case ARM::VST3d16: 1605 case ARM::VST3d32: 1606 case ARM::VST3d8_UPD: 1607 case ARM::VST3d16_UPD: 1608 case ARM::VST3d32_UPD: 1609 case ARM::VST4d8: 1610 case ARM::VST4d16: 1611 case ARM::VST4d32: 1612 case ARM::VST4d8_UPD: 1613 case ARM::VST4d16_UPD: 1614 case ARM::VST4d32_UPD: 1615 DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder); 1616 break; 1617 case ARM::VST2b8: 1618 case ARM::VST2b16: 1619 case ARM::VST2b32: 1620 case ARM::VST2b8_UPD: 1621 case ARM::VST2b16_UPD: 1622 case ARM::VST2b32_UPD: 1623 case ARM::VST3q8: 1624 case ARM::VST3q16: 1625 case ARM::VST3q32: 1626 case ARM::VST3q8_UPD: 1627 case ARM::VST3q16_UPD: 1628 case ARM::VST3q32_UPD: 1629 case ARM::VST4q8: 1630 case ARM::VST4q16: 1631 case ARM::VST4q32: 1632 case ARM::VST4q8_UPD: 1633 case ARM::VST4q16_UPD: 1634 case ARM::VST4q32_UPD: 1635 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1636 break; 1637 default: 1638 break; 1639 } 1640 1641 // Third input register 1642 switch (Inst.getOpcode()) { 1643 case ARM::VST1d8T: 1644 case ARM::VST1d16T: 1645 case ARM::VST1d32T: 1646 case ARM::VST1d64T: 1647 case ARM::VST1d8T_UPD: 1648 case ARM::VST1d16T_UPD: 1649 case ARM::VST1d32T_UPD: 1650 case ARM::VST1d64T_UPD: 1651 case ARM::VST1d8Q: 1652 case ARM::VST1d16Q: 1653 case ARM::VST1d32Q: 1654 case ARM::VST1d64Q: 1655 case ARM::VST1d8Q_UPD: 1656 case ARM::VST1d16Q_UPD: 1657 case ARM::VST1d32Q_UPD: 1658 case ARM::VST1d64Q_UPD: 1659 case ARM::VST2q8: 1660 case ARM::VST2q16: 1661 case ARM::VST2q32: 1662 case ARM::VST2q8_UPD: 1663 case ARM::VST2q16_UPD: 1664 case ARM::VST2q32_UPD: 1665 case ARM::VST3d8: 1666 case ARM::VST3d16: 1667 case ARM::VST3d32: 1668 case ARM::VST3d8_UPD: 1669 case ARM::VST3d16_UPD: 1670 case ARM::VST3d32_UPD: 1671 case ARM::VST4d8: 1672 case ARM::VST4d16: 1673 case ARM::VST4d32: 1674 case ARM::VST4d8_UPD: 1675 case ARM::VST4d16_UPD: 1676 case ARM::VST4d32_UPD: 1677 DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder); 1678 break; 1679 case ARM::VST3q8: 1680 case ARM::VST3q16: 1681 case ARM::VST3q32: 1682 case ARM::VST3q8_UPD: 1683 case ARM::VST3q16_UPD: 1684 case ARM::VST3q32_UPD: 1685 case ARM::VST4q8: 1686 case ARM::VST4q16: 1687 case ARM::VST4q32: 1688 case ARM::VST4q8_UPD: 1689 case ARM::VST4q16_UPD: 1690 case ARM::VST4q32_UPD: 1691 DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder); 1692 break; 1693 default: 1694 break; 1695 } 1696 1697 // Fourth input register 1698 switch (Inst.getOpcode()) { 1699 case ARM::VST1d8Q: 1700 case ARM::VST1d16Q: 1701 case ARM::VST1d32Q: 1702 case ARM::VST1d64Q: 1703 case ARM::VST1d8Q_UPD: 1704 case ARM::VST1d16Q_UPD: 1705 case ARM::VST1d32Q_UPD: 1706 case ARM::VST1d64Q_UPD: 1707 case ARM::VST2q8: 1708 case ARM::VST2q16: 1709 case ARM::VST2q32: 1710 case ARM::VST2q8_UPD: 1711 case ARM::VST2q16_UPD: 1712 case ARM::VST2q32_UPD: 1713 case ARM::VST4d8: 1714 case ARM::VST4d16: 1715 case ARM::VST4d32: 1716 case ARM::VST4d8_UPD: 1717 case ARM::VST4d16_UPD: 1718 case ARM::VST4d32_UPD: 1719 DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder); 1720 break; 1721 case ARM::VST4q8: 1722 case ARM::VST4q16: 1723 case ARM::VST4q32: 1724 case ARM::VST4q8_UPD: 1725 case ARM::VST4q16_UPD: 1726 case ARM::VST4q32_UPD: 1727 DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder); 1728 break; 1729 default: 1730 break; 1731 } 1732 1733 return true; 1734} 1735 1736static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1737 uint64_t Address, const void *Decoder) { 1738 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1739 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1740 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1741 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1742 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1743 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1744 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1745 1746 align *= (1 << size); 1747 1748 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1749 if (regs == 2) DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder); 1750 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1751 1752 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1753 Inst.addOperand(MCOperand::CreateImm(align)); 1754 1755 if (Rm == 0xD) 1756 Inst.addOperand(MCOperand::CreateReg(0)); 1757 else if (Rm != 0xF) 1758 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1759 1760 return true; 1761} 1762 1763static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1764 uint64_t Address, const void *Decoder) { 1765 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1766 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1767 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1768 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1769 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1770 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1771 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1772 align *= 2*size; 1773 1774 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1775 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder); 1776 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1777 1778 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1779 Inst.addOperand(MCOperand::CreateImm(align)); 1780 1781 if (Rm == 0xD) 1782 Inst.addOperand(MCOperand::CreateReg(0)); 1783 else if (Rm != 0xF) 1784 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1785 1786 return true; 1787} 1788 1789static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1790 uint64_t Address, const void *Decoder) { 1791 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1792 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1793 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1794 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1795 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1796 1797 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1798 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder); 1799 DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder); 1800 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1801 1802 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1803 Inst.addOperand(MCOperand::CreateImm(0)); 1804 1805 if (Rm == 0xD) 1806 Inst.addOperand(MCOperand::CreateReg(0)); 1807 else if (Rm != 0xF) 1808 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1809 1810 return true; 1811} 1812 1813static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1814 uint64_t Address, const void *Decoder) { 1815 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1816 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1817 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1818 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1819 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1820 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1821 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1822 1823 if (size == 0x3) { 1824 size = 4; 1825 align = 16; 1826 } else { 1827 if (size == 2) { 1828 size = 1 << size; 1829 align *= 8; 1830 } else { 1831 size = 1 << size; 1832 align *= 4*size; 1833 } 1834 } 1835 1836 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1837 DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder); 1838 DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder); 1839 DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder); 1840 if (Rm == 0xD) DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1841 1842 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 1843 Inst.addOperand(MCOperand::CreateImm(align)); 1844 1845 if (Rm == 0xD) 1846 Inst.addOperand(MCOperand::CreateReg(0)); 1847 else if (Rm != 0xF) 1848 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 1849 1850 return true; 1851} 1852 1853static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1854 uint64_t Address, const void *Decoder) { 1855 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1856 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1857 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 1858 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 1859 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 1860 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 1861 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 1862 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 1863 1864 if (Q) 1865 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder); 1866 else 1867 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1868 1869 Inst.addOperand(MCOperand::CreateImm(imm)); 1870 1871 switch (Inst.getOpcode()) { 1872 case ARM::VORRiv4i16: 1873 case ARM::VORRiv2i32: 1874 case ARM::VBICiv4i16: 1875 case ARM::VBICiv2i32: 1876 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1877 break; 1878 case ARM::VORRiv8i16: 1879 case ARM::VORRiv4i32: 1880 case ARM::VBICiv8i16: 1881 case ARM::VBICiv4i32: 1882 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder); 1883 break; 1884 default: 1885 break; 1886 } 1887 1888 1889 return true; 1890} 1891 1892static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 1893 uint64_t Address, const void *Decoder) { 1894 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1895 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1896 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1897 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 1898 unsigned size = fieldFromInstruction32(Insn, 18, 2); 1899 1900 DecodeQPRRegisterClass(Inst, Rd, Address, Decoder); 1901 DecodeDPRRegisterClass(Inst, Rm, Address, Decoder); 1902 Inst.addOperand(MCOperand::CreateImm(8 << size)); 1903 1904 return true; 1905} 1906 1907static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 1908 uint64_t Address, const void *Decoder) { 1909 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 1910 return true; 1911} 1912 1913static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 1914 uint64_t Address, const void *Decoder) { 1915 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 1916 return true; 1917} 1918 1919static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 1920 uint64_t Address, const void *Decoder) { 1921 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 1922 return true; 1923} 1924 1925static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 1926 uint64_t Address, const void *Decoder) { 1927 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1928 return true; 1929} 1930 1931static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 1932 uint64_t Address, const void *Decoder) { 1933 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1934 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1935 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1936 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 1937 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1938 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 1939 unsigned op = fieldFromInstruction32(Insn, 6, 1); 1940 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 1941 1942 DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); 1943 if (op) DecodeDPRRegisterClass(Inst, Rd, Address, Decoder); // Writeback 1944 1945 for (unsigned i = 0; i < length; ++i) 1946 DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder); 1947 1948 DecodeDPRRegisterClass(Inst, Rm, Address, Decoder); 1949 1950 return true; 1951} 1952 1953static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 1954 uint64_t Address, const void *Decoder) { 1955 // The immediate needs to be a fully instantiated float. However, the 1956 // auto-generated decoder is only able to fill in some of the bits 1957 // necessary. For instance, the 'b' bit is replicated multiple times, 1958 // and is even present in inverted form in one bit. We do a little 1959 // binary parsing here to fill in those missing bits, and then 1960 // reinterpret it all as a float. 1961 union { 1962 uint32_t integer; 1963 float fp; 1964 } fp_conv; 1965 1966 fp_conv.integer = Val; 1967 uint32_t b = fieldFromInstruction32(Val, 25, 1); 1968 fp_conv.integer |= b << 26; 1969 fp_conv.integer |= b << 27; 1970 fp_conv.integer |= b << 28; 1971 fp_conv.integer |= b << 29; 1972 fp_conv.integer |= (~b & 0x1) << 30; 1973 1974 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 1975 return true; 1976} 1977 1978static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 1979 uint64_t Address, const void *Decoder) { 1980 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 1981 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 1982 1983 DecodetGPRRegisterClass(Inst, dst, Address, Decoder); 1984 1985 if (Inst.getOpcode() == ARM::tADR) 1986 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 1987 else if (Inst.getOpcode() == ARM::tADDrSPi) 1988 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 1989 else 1990 return false; 1991 1992 Inst.addOperand(MCOperand::CreateImm(imm)); 1993 return true; 1994} 1995 1996static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 1997 uint64_t Address, const void *Decoder) { 1998 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 1999 return true; 2000} 2001 2002static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2003 uint64_t Address, const void *Decoder) { 2004 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2005 return true; 2006} 2007 2008static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2009 uint64_t Address, const void *Decoder) { 2010 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2011 return true; 2012} 2013 2014static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2015 uint64_t Address, const void *Decoder) { 2016 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2017 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2018 2019 DecodetGPRRegisterClass(Inst, Rn, Address, Decoder); 2020 DecodetGPRRegisterClass(Inst, Rm, Address, Decoder); 2021 2022 return true; 2023} 2024 2025static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2026 uint64_t Address, const void *Decoder) { 2027 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2028 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2029 2030 DecodetGPRRegisterClass(Inst, Rn, Address, Decoder); 2031 Inst.addOperand(MCOperand::CreateImm(imm)); 2032 2033 return true; 2034} 2035 2036static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2037 uint64_t Address, const void *Decoder) { 2038 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2039 2040 return true; 2041} 2042 2043static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2044 uint64_t Address, const void *Decoder) { 2045 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2046 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2047 2048 return true; 2049} 2050 2051static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2052 uint64_t Address, const void *Decoder) { 2053 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2054 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2055 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2056 2057 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2058 DecoderGPRRegisterClass(Inst, Rm, Address, Decoder); 2059 Inst.addOperand(MCOperand::CreateImm(imm)); 2060 2061 return true; 2062} 2063 2064static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2065 uint64_t Address, const void *Decoder) { 2066 if (Inst.getOpcode() != ARM::t2PLDs) { 2067 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2068 DecodeGPRRegisterClass(Inst, Rt, Address, Decoder); 2069 } 2070 2071 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2072 if (Rn == 0xF) { 2073 switch (Inst.getOpcode()) { 2074 case ARM::t2LDRBs: 2075 Inst.setOpcode(ARM::t2LDRBpci); 2076 break; 2077 case ARM::t2LDRHs: 2078 Inst.setOpcode(ARM::t2LDRHpci); 2079 break; 2080 case ARM::t2LDRSHs: 2081 Inst.setOpcode(ARM::t2LDRSHpci); 2082 break; 2083 case ARM::t2LDRSBs: 2084 Inst.setOpcode(ARM::t2LDRSBpci); 2085 break; 2086 case ARM::t2PLDs: 2087 Inst.setOpcode(ARM::t2PLDi12); 2088 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2089 break; 2090 default: 2091 return false; 2092 } 2093 2094 int imm = fieldFromInstruction32(Insn, 0, 12); 2095 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2096 Inst.addOperand(MCOperand::CreateImm(imm)); 2097 2098 return true; 2099 } 2100 2101 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2102 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2103 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2104 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2105 2106 return true; 2107} 2108 2109static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2110 uint64_t Address, const void *Decoder) { 2111 int imm = Val & 0xFF; 2112 if (!(Val & 0x100)) imm *= -1; 2113 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2114 2115 return true; 2116} 2117 2118static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2119 uint64_t Address, const void *Decoder) { 2120 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2121 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2122 2123 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2124 DecodeT2Imm8S4(Inst, imm, Address, Decoder); 2125 2126 return true; 2127} 2128 2129static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2130 uint64_t Address, const void *Decoder) { 2131 int imm = Val & 0xFF; 2132 if (!(Val & 0x100)) imm *= -1; 2133 Inst.addOperand(MCOperand::CreateImm(imm)); 2134 2135 return true; 2136} 2137 2138 2139static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2140 uint64_t Address, const void *Decoder) { 2141 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2142 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2143 2144 // Some instructions always use an additive offset. 2145 switch (Inst.getOpcode()) { 2146 case ARM::t2LDRT: 2147 case ARM::t2LDRBT: 2148 case ARM::t2LDRHT: 2149 case ARM::t2LDRSBT: 2150 case ARM::t2LDRSHT: 2151 imm |= 0x100; 2152 break; 2153 default: 2154 break; 2155 } 2156 2157 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2158 DecodeT2Imm8(Inst, imm, Address, Decoder); 2159 2160 return true; 2161} 2162 2163 2164static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2165 uint64_t Address, const void *Decoder) { 2166 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2167 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2168 2169 DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); 2170 Inst.addOperand(MCOperand::CreateImm(imm)); 2171 2172 return true; 2173} 2174 2175 2176static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2177 uint64_t Address, const void *Decoder) { 2178 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2179 2180 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2181 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2182 Inst.addOperand(MCOperand::CreateImm(imm)); 2183 2184 return true; 2185} 2186 2187static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2188 uint64_t Address, const void *Decoder) { 2189 if (Inst.getOpcode() == ARM::tADDrSP) { 2190 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2191 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2192 2193 DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder); 2194 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2195 DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder); 2196 } else if (Inst.getOpcode() == ARM::tADDspr) { 2197 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2198 2199 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2200 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2201 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 2202 } 2203 2204 return true; 2205} 2206 2207static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2208 uint64_t Address, const void *Decoder) { 2209 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2210 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2211 2212 Inst.addOperand(MCOperand::CreateImm(imod)); 2213 Inst.addOperand(MCOperand::CreateImm(flags)); 2214 2215 return true; 2216} 2217 2218static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2219 uint64_t Address, const void *Decoder) { 2220 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2221 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2222 2223 DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); 2224 Inst.addOperand(MCOperand::CreateImm(add)); 2225 2226 return true; 2227} 2228 2229static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2230 uint64_t Address, const void *Decoder) { 2231 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2232 return true; 2233} 2234 2235static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2236 uint64_t Address, const void *Decoder) { 2237 if (Val == 0xA || Val == 0xB) 2238 return false; 2239 2240 Inst.addOperand(MCOperand::CreateImm(Val)); 2241 return true; 2242} 2243 2244static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2245 uint64_t Address, const void *Decoder) { 2246 if (Val == 0) 2247 Inst.addOperand(MCOperand::CreateImm(32)); 2248 else 2249 Inst.addOperand(MCOperand::CreateImm(Val)); 2250 return true; 2251} 2252 2253static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2254 uint64_t Address, const void *Decoder) { 2255 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2256 if (pred == 0xE || pred == 0xF) { 2257 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2258 switch (opc) { 2259 default: 2260 return false; 2261 case 0: 2262 Inst.setOpcode(ARM::t2DSB); 2263 break; 2264 case 1: 2265 Inst.setOpcode(ARM::t2DMB); 2266 break; 2267 case 2: 2268 Inst.setOpcode(ARM::t2ISB); 2269 return true; 2270 } 2271 2272 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2273 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2274 } 2275 2276 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2277 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2278 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2279 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2280 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2281 2282 DecodeT2BROperand(Inst, brtarget, Address, Decoder); 2283 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) 2284 return false; 2285 2286 return true; 2287} 2288 2289// Decode a shifted immediate operand. These basically consist 2290// of an 8-bit value, and a 4-bit directive that specifies either 2291// a splat operation or a rotation. 2292static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2293 uint64_t Address, const void *Decoder) { 2294 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2295 if (ctrl == 0) { 2296 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2297 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2298 switch (byte) { 2299 case 0: 2300 Inst.addOperand(MCOperand::CreateImm(imm)); 2301 break; 2302 case 1: 2303 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2304 break; 2305 case 2: 2306 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2307 break; 2308 case 3: 2309 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2310 (imm << 8) | imm)); 2311 break; 2312 } 2313 } else { 2314 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2315 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2316 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2317 Inst.addOperand(MCOperand::CreateImm(imm)); 2318 } 2319 2320 return true; 2321} 2322 2323static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2324 uint64_t Address, const void *Decoder){ 2325 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2326 return true; 2327} 2328 2329static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2330 uint64_t Address, const void *Decoder){ 2331 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2332 return true; 2333} 2334 2335static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, 2336 uint64_t Address, const void *Decoder) { 2337 bool isImm = fieldFromInstruction32(Val, 9, 1); 2338 bool isAdd = fieldFromInstruction32(Val, 8, 1); 2339 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2340 2341 if (!isImm) { 2342 DecodeGPRRegisterClass(Inst, imm, Address, Decoder); 2343 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); 2344 } else { 2345 Inst.addOperand(MCOperand::CreateReg(0)); 2346 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); 2347 } 2348 2349 return true; 2350} 2351 2352static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2353 uint64_t Address, const void *Decoder) { 2354 switch (Val) { 2355 default: 2356 return false; 2357 case 0xF: // SY 2358 case 0xE: // ST 2359 case 0xB: // ISH 2360 case 0xA: // ISHST 2361 case 0x7: // NSH 2362 case 0x6: // NSHST 2363 case 0x3: // OSH 2364 case 0x2: // OSHST 2365 break; 2366 } 2367 2368 Inst.addOperand(MCOperand::CreateImm(Val)); 2369 return true; 2370} 2371 2372