ARMDisassembler.cpp revision ebc3938ae717d7352de800344c3ad5a1bceb74e5
1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "llvm/MC/MCDisassembler.h" 13#include "MCTargetDesc/ARMAddressingModes.h" 14#include "MCTargetDesc/ARMBaseInfo.h" 15#include "MCTargetDesc/ARMMCExpr.h" 16#include "llvm/MC/MCContext.h" 17#include "llvm/MC/MCExpr.h" 18#include "llvm/MC/MCFixedLenDisassembler.h" 19#include "llvm/MC/MCInst.h" 20#include "llvm/MC/MCInstrDesc.h" 21#include "llvm/MC/MCSubtargetInfo.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/LEB128.h" 25#include "llvm/Support/MemoryObject.h" 26#include "llvm/Support/TargetRegistry.h" 27#include "llvm/Support/raw_ostream.h" 28#include <vector> 29 30using namespace llvm; 31 32typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85} 86 87namespace { 88/// ARMDisassembler - ARM disassembler for all ARM platforms. 89class ARMDisassembler : public MCDisassembler { 90public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107}; 108 109/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110class ThumbDisassembler : public MCDisassembler { 111public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133}; 134} 135 136static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149} 150 151 152// Forward declare these because the autogenerated code will reference them. 153// Definitions are further down. 154static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 185 unsigned RegNo, uint64_t Address, 186 const void *Decoder); 187 188static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 201static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 212 uint64_t Address, const void *Decoder); 213static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 218static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 219 unsigned Insn, 220 uint64_t Adddress, 221 const void *Decoder); 222static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 265 uint64_t Address, const void *Decoder); 266static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 327 const void *Decoder); 328 329 330static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 331 uint64_t Address, const void *Decoder); 332static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void* Decoder); 354static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void* Decoder); 356static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void* Decoder); 358static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 363 uint64_t Address, const void *Decoder); 364static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 365 uint64_t Address, const void *Decoder); 366static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 369 uint64_t Address, const void *Decoder); 370static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 371 uint64_t Address, const void *Decoder); 372static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 373 uint64_t Address, const void *Decoder); 374static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 387 uint64_t Address, const void *Decoder); 388static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 393 uint64_t Address, const void *Decoder); 394static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 395 uint64_t Address, const void *Decoder); 396static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 401 uint64_t Address, const void *Decoder); 402 403static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 406 uint64_t Address, const void *Decoder); 407#include "ARMGenDisassemblerTables.inc" 408 409static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 410 return new ARMDisassembler(STI); 411} 412 413static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 414 return new ThumbDisassembler(STI); 415} 416 417DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 418 const MemoryObject &Region, 419 uint64_t Address, 420 raw_ostream &os, 421 raw_ostream &cs) const { 422 CommentStream = &cs; 423 424 uint8_t bytes[4]; 425 426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 428 429 // We want to read exactly 4 bytes of data. 430 if (Region.readBytes(Address, 4, bytes) == -1) { 431 Size = 0; 432 return MCDisassembler::Fail; 433 } 434 435 // Encoded as a small-endian 32-bit word in the stream. 436 uint32_t insn = (bytes[3] << 24) | 437 (bytes[2] << 16) | 438 (bytes[1] << 8) | 439 (bytes[0] << 0); 440 441 // Calling the auto-generated decoder function. 442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 443 Address, this, STI); 444 if (result != MCDisassembler::Fail) { 445 Size = 4; 446 return result; 447 } 448 449 // VFP and NEON instructions, similarly, are shared between ARM 450 // and Thumb modes. 451 MI.clear(); 452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 453 if (result != MCDisassembler::Fail) { 454 Size = 4; 455 return result; 456 } 457 458 MI.clear(); 459 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 460 this, STI); 461 if (result != MCDisassembler::Fail) { 462 Size = 4; 463 // Add a fake predicate operand, because we share these instruction 464 // definitions with Thumb2 where these instructions are predicable. 465 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 466 return MCDisassembler::Fail; 467 return result; 468 } 469 470 MI.clear(); 471 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 472 this, STI); 473 if (result != MCDisassembler::Fail) { 474 Size = 4; 475 // Add a fake predicate operand, because we share these instruction 476 // definitions with Thumb2 where these instructions are predicable. 477 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 478 return MCDisassembler::Fail; 479 return result; 480 } 481 482 MI.clear(); 483 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 484 this, STI); 485 if (result != MCDisassembler::Fail) { 486 Size = 4; 487 // Add a fake predicate operand, because we share these instruction 488 // definitions with Thumb2 where these instructions are predicable. 489 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 490 return MCDisassembler::Fail; 491 return result; 492 } 493 494 MI.clear(); 495 496 Size = 0; 497 return MCDisassembler::Fail; 498} 499 500namespace llvm { 501extern const MCInstrDesc ARMInsts[]; 502} 503 504/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 505/// immediate Value in the MCInst. The immediate Value has had any PC 506/// adjustment made by the caller. If the instruction is a branch instruction 507/// then isBranch is true, else false. If the getOpInfo() function was set as 508/// part of the setupForSymbolicDisassembly() call then that function is called 509/// to get any symbolic information at the Address for this instruction. If 510/// that returns non-zero then the symbolic information it returns is used to 511/// create an MCExpr and that is added as an operand to the MCInst. If 512/// getOpInfo() returns zero and isBranch is true then a symbol look up for 513/// Value is done and if a symbol is found an MCExpr is created with that, else 514/// an MCExpr with Value is created. This function returns true if it adds an 515/// operand to the MCInst and false otherwise. 516static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 517 bool isBranch, uint64_t InstSize, 518 MCInst &MI, const void *Decoder) { 519 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 520 // FIXME: Does it make sense for value to be negative? 521 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 522 /* Offset */ 0, InstSize); 523} 524 525/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 526/// referenced by a load instruction with the base register that is the Pc. 527/// These can often be values in a literal pool near the Address of the 528/// instruction. The Address of the instruction and its immediate Value are 529/// used as a possible literal pool entry. The SymbolLookUp call back will 530/// return the name of a symbol referenced by the literal pool's entry if 531/// the referenced address is that of a symbol. Or it will return a pointer to 532/// a literal 'C' string if the referenced address of the literal pool's entry 533/// is an address into a section with 'C' string literals. 534static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 535 const void *Decoder) { 536 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 537 Dis->tryAddingPcLoadReferenceComment(Value, Address); 538} 539 540// Thumb1 instructions don't have explicit S bits. Rather, they 541// implicitly set CPSR. Since it's not represented in the encoding, the 542// auto-generated decoder won't inject the CPSR operand. We need to fix 543// that as a post-pass. 544static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 545 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 546 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 547 MCInst::iterator I = MI.begin(); 548 for (unsigned i = 0; i < NumOps; ++i, ++I) { 549 if (I == MI.end()) break; 550 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 551 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 552 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 553 return; 554 } 555 } 556 557 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 558} 559 560// Most Thumb instructions don't have explicit predicates in the 561// encoding, but rather get their predicates from IT context. We need 562// to fix up the predicate operands using this context information as a 563// post-pass. 564MCDisassembler::DecodeStatus 565ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 566 MCDisassembler::DecodeStatus S = Success; 567 568 // A few instructions actually have predicates encoded in them. Don't 569 // try to overwrite it if we're seeing one of those. 570 switch (MI.getOpcode()) { 571 case ARM::tBcc: 572 case ARM::t2Bcc: 573 case ARM::tCBZ: 574 case ARM::tCBNZ: 575 case ARM::tCPS: 576 case ARM::t2CPS3p: 577 case ARM::t2CPS2p: 578 case ARM::t2CPS1p: 579 case ARM::tMOVSr: 580 case ARM::tSETEND: 581 // Some instructions (mostly conditional branches) are not 582 // allowed in IT blocks. 583 if (ITBlock.instrInITBlock()) 584 S = SoftFail; 585 else 586 return Success; 587 break; 588 case ARM::tB: 589 case ARM::t2B: 590 case ARM::t2TBB: 591 case ARM::t2TBH: 592 // Some instructions (mostly unconditional branches) can 593 // only appears at the end of, or outside of, an IT. 594 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 595 S = SoftFail; 596 break; 597 default: 598 break; 599 } 600 601 // If we're in an IT block, base the predicate on that. Otherwise, 602 // assume a predicate of AL. 603 unsigned CC; 604 CC = ITBlock.getITCC(); 605 if (CC == 0xF) 606 CC = ARMCC::AL; 607 if (ITBlock.instrInITBlock()) 608 ITBlock.advanceITState(); 609 610 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 611 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 612 MCInst::iterator I = MI.begin(); 613 for (unsigned i = 0; i < NumOps; ++i, ++I) { 614 if (I == MI.end()) break; 615 if (OpInfo[i].isPredicate()) { 616 I = MI.insert(I, MCOperand::CreateImm(CC)); 617 ++I; 618 if (CC == ARMCC::AL) 619 MI.insert(I, MCOperand::CreateReg(0)); 620 else 621 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 622 return S; 623 } 624 } 625 626 I = MI.insert(I, MCOperand::CreateImm(CC)); 627 ++I; 628 if (CC == ARMCC::AL) 629 MI.insert(I, MCOperand::CreateReg(0)); 630 else 631 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 632 633 return S; 634} 635 636// Thumb VFP instructions are a special case. Because we share their 637// encodings between ARM and Thumb modes, and they are predicable in ARM 638// mode, the auto-generated decoder will give them an (incorrect) 639// predicate operand. We need to rewrite these operands based on the IT 640// context as a post-pass. 641void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 642 unsigned CC; 643 CC = ITBlock.getITCC(); 644 if (ITBlock.instrInITBlock()) 645 ITBlock.advanceITState(); 646 647 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 648 MCInst::iterator I = MI.begin(); 649 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 650 for (unsigned i = 0; i < NumOps; ++i, ++I) { 651 if (OpInfo[i].isPredicate() ) { 652 I->setImm(CC); 653 ++I; 654 if (CC == ARMCC::AL) 655 I->setReg(0); 656 else 657 I->setReg(ARM::CPSR); 658 return; 659 } 660 } 661} 662 663DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 664 const MemoryObject &Region, 665 uint64_t Address, 666 raw_ostream &os, 667 raw_ostream &cs) const { 668 CommentStream = &cs; 669 670 uint8_t bytes[4]; 671 672 assert((STI.getFeatureBits() & ARM::ModeThumb) && 673 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 674 675 // We want to read exactly 2 bytes of data. 676 if (Region.readBytes(Address, 2, bytes) == -1) { 677 Size = 0; 678 return MCDisassembler::Fail; 679 } 680 681 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 682 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 683 Address, this, STI); 684 if (result != MCDisassembler::Fail) { 685 Size = 2; 686 Check(result, AddThumbPredicate(MI)); 687 return result; 688 } 689 690 MI.clear(); 691 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 692 Address, this, STI); 693 if (result) { 694 Size = 2; 695 bool InITBlock = ITBlock.instrInITBlock(); 696 Check(result, AddThumbPredicate(MI)); 697 AddThumb1SBit(MI, InITBlock); 698 return result; 699 } 700 701 MI.clear(); 702 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 703 Address, this, STI); 704 if (result != MCDisassembler::Fail) { 705 Size = 2; 706 707 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 708 // the Thumb predicate. 709 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 710 result = MCDisassembler::SoftFail; 711 712 Check(result, AddThumbPredicate(MI)); 713 714 // If we find an IT instruction, we need to parse its condition 715 // code and mask operands so that we can apply them correctly 716 // to the subsequent instructions. 717 if (MI.getOpcode() == ARM::t2IT) { 718 719 unsigned Firstcond = MI.getOperand(0).getImm(); 720 unsigned Mask = MI.getOperand(1).getImm(); 721 ITBlock.setITState(Firstcond, Mask); 722 } 723 724 return result; 725 } 726 727 // We want to read exactly 4 bytes of data. 728 if (Region.readBytes(Address, 4, bytes) == -1) { 729 Size = 0; 730 return MCDisassembler::Fail; 731 } 732 733 uint32_t insn32 = (bytes[3] << 8) | 734 (bytes[2] << 0) | 735 (bytes[1] << 24) | 736 (bytes[0] << 16); 737 MI.clear(); 738 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 739 this, STI); 740 if (result != MCDisassembler::Fail) { 741 Size = 4; 742 bool InITBlock = ITBlock.instrInITBlock(); 743 Check(result, AddThumbPredicate(MI)); 744 AddThumb1SBit(MI, InITBlock); 745 return result; 746 } 747 748 MI.clear(); 749 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 750 this, STI); 751 if (result != MCDisassembler::Fail) { 752 Size = 4; 753 Check(result, AddThumbPredicate(MI)); 754 return result; 755 } 756 757 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 758 MI.clear(); 759 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 760 if (result != MCDisassembler::Fail) { 761 Size = 4; 762 UpdateThumbVFPPredicate(MI); 763 return result; 764 } 765 } 766 767 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 768 MI.clear(); 769 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 770 this, STI); 771 if (result != MCDisassembler::Fail) { 772 Size = 4; 773 Check(result, AddThumbPredicate(MI)); 774 return result; 775 } 776 } 777 778 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 779 MI.clear(); 780 uint32_t NEONLdStInsn = insn32; 781 NEONLdStInsn &= 0xF0FFFFFF; 782 NEONLdStInsn |= 0x04000000; 783 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 784 Address, this, STI); 785 if (result != MCDisassembler::Fail) { 786 Size = 4; 787 Check(result, AddThumbPredicate(MI)); 788 return result; 789 } 790 } 791 792 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 793 MI.clear(); 794 uint32_t NEONDataInsn = insn32; 795 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 796 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 797 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 798 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 799 Address, this, STI); 800 if (result != MCDisassembler::Fail) { 801 Size = 4; 802 Check(result, AddThumbPredicate(MI)); 803 return result; 804 } 805 } 806 807 Size = 0; 808 return MCDisassembler::Fail; 809} 810 811 812extern "C" void LLVMInitializeARMDisassembler() { 813 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 814 createARMDisassembler); 815 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 816 createThumbDisassembler); 817} 818 819static const uint16_t GPRDecoderTable[] = { 820 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 821 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 822 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 823 ARM::R12, ARM::SP, ARM::LR, ARM::PC 824}; 825 826static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 827 uint64_t Address, const void *Decoder) { 828 if (RegNo > 15) 829 return MCDisassembler::Fail; 830 831 unsigned Register = GPRDecoderTable[RegNo]; 832 Inst.addOperand(MCOperand::CreateReg(Register)); 833 return MCDisassembler::Success; 834} 835 836static DecodeStatus 837DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 838 uint64_t Address, const void *Decoder) { 839 DecodeStatus S = MCDisassembler::Success; 840 841 if (RegNo == 15) 842 S = MCDisassembler::SoftFail; 843 844 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 845 846 return S; 847} 848 849static DecodeStatus 850DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 851 uint64_t Address, const void *Decoder) { 852 DecodeStatus S = MCDisassembler::Success; 853 854 if (RegNo == 15) 855 { 856 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 857 return MCDisassembler::Success; 858 } 859 860 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 861 return S; 862} 863 864static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 865 uint64_t Address, const void *Decoder) { 866 if (RegNo > 7) 867 return MCDisassembler::Fail; 868 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 869} 870 871static const uint16_t GPRPairDecoderTable[] = { 872 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 873 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 874}; 875 876static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 877 uint64_t Address, const void *Decoder) { 878 DecodeStatus S = MCDisassembler::Success; 879 880 if (RegNo > 13) 881 return MCDisassembler::Fail; 882 883 if ((RegNo & 1) || RegNo == 0xe) 884 S = MCDisassembler::SoftFail; 885 886 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 887 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 888 return S; 889} 890 891static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 892 uint64_t Address, const void *Decoder) { 893 unsigned Register = 0; 894 switch (RegNo) { 895 case 0: 896 Register = ARM::R0; 897 break; 898 case 1: 899 Register = ARM::R1; 900 break; 901 case 2: 902 Register = ARM::R2; 903 break; 904 case 3: 905 Register = ARM::R3; 906 break; 907 case 9: 908 Register = ARM::R9; 909 break; 910 case 12: 911 Register = ARM::R12; 912 break; 913 default: 914 return MCDisassembler::Fail; 915 } 916 917 Inst.addOperand(MCOperand::CreateReg(Register)); 918 return MCDisassembler::Success; 919} 920 921static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 922 uint64_t Address, const void *Decoder) { 923 DecodeStatus S = MCDisassembler::Success; 924 if (RegNo == 13 || RegNo == 15) 925 S = MCDisassembler::SoftFail; 926 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 927 return S; 928} 929 930static const uint16_t SPRDecoderTable[] = { 931 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 932 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 933 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 934 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 935 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 936 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 937 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 938 ARM::S28, ARM::S29, ARM::S30, ARM::S31 939}; 940 941static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 942 uint64_t Address, const void *Decoder) { 943 if (RegNo > 31) 944 return MCDisassembler::Fail; 945 946 unsigned Register = SPRDecoderTable[RegNo]; 947 Inst.addOperand(MCOperand::CreateReg(Register)); 948 return MCDisassembler::Success; 949} 950 951static const uint16_t DPRDecoderTable[] = { 952 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 953 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 954 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 955 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 956 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 957 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 958 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 959 ARM::D28, ARM::D29, ARM::D30, ARM::D31 960}; 961 962static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 963 uint64_t Address, const void *Decoder) { 964 if (RegNo > 31) 965 return MCDisassembler::Fail; 966 967 unsigned Register = DPRDecoderTable[RegNo]; 968 Inst.addOperand(MCOperand::CreateReg(Register)); 969 return MCDisassembler::Success; 970} 971 972static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 973 uint64_t Address, const void *Decoder) { 974 if (RegNo > 7) 975 return MCDisassembler::Fail; 976 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 977} 978 979static DecodeStatus 980DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 981 uint64_t Address, const void *Decoder) { 982 if (RegNo > 15) 983 return MCDisassembler::Fail; 984 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 985} 986 987static const uint16_t QPRDecoderTable[] = { 988 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 989 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 990 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 991 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 992}; 993 994 995static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 996 uint64_t Address, const void *Decoder) { 997 if (RegNo > 31 || (RegNo & 1) != 0) 998 return MCDisassembler::Fail; 999 RegNo >>= 1; 1000 1001 unsigned Register = QPRDecoderTable[RegNo]; 1002 Inst.addOperand(MCOperand::CreateReg(Register)); 1003 return MCDisassembler::Success; 1004} 1005 1006static const uint16_t DPairDecoderTable[] = { 1007 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1008 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1009 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1010 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1011 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1012 ARM::Q15 1013}; 1014 1015static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1016 uint64_t Address, const void *Decoder) { 1017 if (RegNo > 30) 1018 return MCDisassembler::Fail; 1019 1020 unsigned Register = DPairDecoderTable[RegNo]; 1021 Inst.addOperand(MCOperand::CreateReg(Register)); 1022 return MCDisassembler::Success; 1023} 1024 1025static const uint16_t DPairSpacedDecoderTable[] = { 1026 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1027 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1028 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1029 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1030 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1031 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1032 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1033 ARM::D28_D30, ARM::D29_D31 1034}; 1035 1036static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1037 unsigned RegNo, 1038 uint64_t Address, 1039 const void *Decoder) { 1040 if (RegNo > 29) 1041 return MCDisassembler::Fail; 1042 1043 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1044 Inst.addOperand(MCOperand::CreateReg(Register)); 1045 return MCDisassembler::Success; 1046} 1047 1048static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1049 uint64_t Address, const void *Decoder) { 1050 if (Val == 0xF) return MCDisassembler::Fail; 1051 // AL predicate is not allowed on Thumb1 branches. 1052 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1053 return MCDisassembler::Fail; 1054 Inst.addOperand(MCOperand::CreateImm(Val)); 1055 if (Val == ARMCC::AL) { 1056 Inst.addOperand(MCOperand::CreateReg(0)); 1057 } else 1058 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1059 return MCDisassembler::Success; 1060} 1061 1062static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1063 uint64_t Address, const void *Decoder) { 1064 if (Val) 1065 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1066 else 1067 Inst.addOperand(MCOperand::CreateReg(0)); 1068 return MCDisassembler::Success; 1069} 1070 1071static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1072 uint64_t Address, const void *Decoder) { 1073 uint32_t imm = Val & 0xFF; 1074 uint32_t rot = (Val & 0xF00) >> 7; 1075 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1076 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1077 return MCDisassembler::Success; 1078} 1079 1080static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1081 uint64_t Address, const void *Decoder) { 1082 DecodeStatus S = MCDisassembler::Success; 1083 1084 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1085 unsigned type = fieldFromInstruction(Val, 5, 2); 1086 unsigned imm = fieldFromInstruction(Val, 7, 5); 1087 1088 // Register-immediate 1089 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1090 return MCDisassembler::Fail; 1091 1092 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1093 switch (type) { 1094 case 0: 1095 Shift = ARM_AM::lsl; 1096 break; 1097 case 1: 1098 Shift = ARM_AM::lsr; 1099 break; 1100 case 2: 1101 Shift = ARM_AM::asr; 1102 break; 1103 case 3: 1104 Shift = ARM_AM::ror; 1105 break; 1106 } 1107 1108 if (Shift == ARM_AM::ror && imm == 0) 1109 Shift = ARM_AM::rrx; 1110 1111 unsigned Op = Shift | (imm << 3); 1112 Inst.addOperand(MCOperand::CreateImm(Op)); 1113 1114 return S; 1115} 1116 1117static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1118 uint64_t Address, const void *Decoder) { 1119 DecodeStatus S = MCDisassembler::Success; 1120 1121 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1122 unsigned type = fieldFromInstruction(Val, 5, 2); 1123 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1124 1125 // Register-register 1126 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1127 return MCDisassembler::Fail; 1128 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1129 return MCDisassembler::Fail; 1130 1131 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1132 switch (type) { 1133 case 0: 1134 Shift = ARM_AM::lsl; 1135 break; 1136 case 1: 1137 Shift = ARM_AM::lsr; 1138 break; 1139 case 2: 1140 Shift = ARM_AM::asr; 1141 break; 1142 case 3: 1143 Shift = ARM_AM::ror; 1144 break; 1145 } 1146 1147 Inst.addOperand(MCOperand::CreateImm(Shift)); 1148 1149 return S; 1150} 1151 1152static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1153 uint64_t Address, const void *Decoder) { 1154 DecodeStatus S = MCDisassembler::Success; 1155 1156 bool writebackLoad = false; 1157 unsigned writebackReg = 0; 1158 switch (Inst.getOpcode()) { 1159 default: 1160 break; 1161 case ARM::LDMIA_UPD: 1162 case ARM::LDMDB_UPD: 1163 case ARM::LDMIB_UPD: 1164 case ARM::LDMDA_UPD: 1165 case ARM::t2LDMIA_UPD: 1166 case ARM::t2LDMDB_UPD: 1167 writebackLoad = true; 1168 writebackReg = Inst.getOperand(0).getReg(); 1169 break; 1170 } 1171 1172 // Empty register lists are not allowed. 1173 if (Val == 0) return MCDisassembler::Fail; 1174 for (unsigned i = 0; i < 16; ++i) { 1175 if (Val & (1 << i)) { 1176 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1177 return MCDisassembler::Fail; 1178 // Writeback not allowed if Rn is in the target list. 1179 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1180 Check(S, MCDisassembler::SoftFail); 1181 } 1182 } 1183 1184 return S; 1185} 1186 1187static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1188 uint64_t Address, const void *Decoder) { 1189 DecodeStatus S = MCDisassembler::Success; 1190 1191 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1192 unsigned regs = fieldFromInstruction(Val, 0, 8); 1193 1194 // In case of unpredictable encoding, tweak the operands. 1195 if (regs == 0 || (Vd + regs) > 32) { 1196 regs = Vd + regs > 32 ? 32 - Vd : regs; 1197 regs = std::max( 1u, regs); 1198 S = MCDisassembler::SoftFail; 1199 } 1200 1201 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1202 return MCDisassembler::Fail; 1203 for (unsigned i = 0; i < (regs - 1); ++i) { 1204 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1205 return MCDisassembler::Fail; 1206 } 1207 1208 return S; 1209} 1210 1211static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1212 uint64_t Address, const void *Decoder) { 1213 DecodeStatus S = MCDisassembler::Success; 1214 1215 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1216 unsigned regs = fieldFromInstruction(Val, 1, 7); 1217 1218 // In case of unpredictable encoding, tweak the operands. 1219 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1220 regs = Vd + regs > 32 ? 32 - Vd : regs; 1221 regs = std::max( 1u, regs); 1222 regs = std::min(16u, regs); 1223 S = MCDisassembler::SoftFail; 1224 } 1225 1226 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1227 return MCDisassembler::Fail; 1228 for (unsigned i = 0; i < (regs - 1); ++i) { 1229 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1230 return MCDisassembler::Fail; 1231 } 1232 1233 return S; 1234} 1235 1236static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1237 uint64_t Address, const void *Decoder) { 1238 // This operand encodes a mask of contiguous zeros between a specified MSB 1239 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1240 // the mask of all bits LSB-and-lower, and then xor them to create 1241 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1242 // create the final mask. 1243 unsigned msb = fieldFromInstruction(Val, 5, 5); 1244 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1245 1246 DecodeStatus S = MCDisassembler::Success; 1247 if (lsb > msb) { 1248 Check(S, MCDisassembler::SoftFail); 1249 // The check above will cause the warning for the "potentially undefined 1250 // instruction encoding" but we can't build a bad MCOperand value here 1251 // with a lsb > msb or else printing the MCInst will cause a crash. 1252 lsb = msb; 1253 } 1254 1255 uint32_t msb_mask = 0xFFFFFFFF; 1256 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1257 uint32_t lsb_mask = (1U << lsb) - 1; 1258 1259 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1260 return S; 1261} 1262 1263static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1264 uint64_t Address, const void *Decoder) { 1265 DecodeStatus S = MCDisassembler::Success; 1266 1267 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1268 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1269 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1270 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1271 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1272 unsigned U = fieldFromInstruction(Insn, 23, 1); 1273 1274 switch (Inst.getOpcode()) { 1275 case ARM::LDC_OFFSET: 1276 case ARM::LDC_PRE: 1277 case ARM::LDC_POST: 1278 case ARM::LDC_OPTION: 1279 case ARM::LDCL_OFFSET: 1280 case ARM::LDCL_PRE: 1281 case ARM::LDCL_POST: 1282 case ARM::LDCL_OPTION: 1283 case ARM::STC_OFFSET: 1284 case ARM::STC_PRE: 1285 case ARM::STC_POST: 1286 case ARM::STC_OPTION: 1287 case ARM::STCL_OFFSET: 1288 case ARM::STCL_PRE: 1289 case ARM::STCL_POST: 1290 case ARM::STCL_OPTION: 1291 case ARM::t2LDC_OFFSET: 1292 case ARM::t2LDC_PRE: 1293 case ARM::t2LDC_POST: 1294 case ARM::t2LDC_OPTION: 1295 case ARM::t2LDCL_OFFSET: 1296 case ARM::t2LDCL_PRE: 1297 case ARM::t2LDCL_POST: 1298 case ARM::t2LDCL_OPTION: 1299 case ARM::t2STC_OFFSET: 1300 case ARM::t2STC_PRE: 1301 case ARM::t2STC_POST: 1302 case ARM::t2STC_OPTION: 1303 case ARM::t2STCL_OFFSET: 1304 case ARM::t2STCL_PRE: 1305 case ARM::t2STCL_POST: 1306 case ARM::t2STCL_OPTION: 1307 if (coproc == 0xA || coproc == 0xB) 1308 return MCDisassembler::Fail; 1309 break; 1310 default: 1311 break; 1312 } 1313 1314 Inst.addOperand(MCOperand::CreateImm(coproc)); 1315 Inst.addOperand(MCOperand::CreateImm(CRd)); 1316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1317 return MCDisassembler::Fail; 1318 1319 switch (Inst.getOpcode()) { 1320 case ARM::t2LDC2_OFFSET: 1321 case ARM::t2LDC2L_OFFSET: 1322 case ARM::t2LDC2_PRE: 1323 case ARM::t2LDC2L_PRE: 1324 case ARM::t2STC2_OFFSET: 1325 case ARM::t2STC2L_OFFSET: 1326 case ARM::t2STC2_PRE: 1327 case ARM::t2STC2L_PRE: 1328 case ARM::LDC2_OFFSET: 1329 case ARM::LDC2L_OFFSET: 1330 case ARM::LDC2_PRE: 1331 case ARM::LDC2L_PRE: 1332 case ARM::STC2_OFFSET: 1333 case ARM::STC2L_OFFSET: 1334 case ARM::STC2_PRE: 1335 case ARM::STC2L_PRE: 1336 case ARM::t2LDC_OFFSET: 1337 case ARM::t2LDCL_OFFSET: 1338 case ARM::t2LDC_PRE: 1339 case ARM::t2LDCL_PRE: 1340 case ARM::t2STC_OFFSET: 1341 case ARM::t2STCL_OFFSET: 1342 case ARM::t2STC_PRE: 1343 case ARM::t2STCL_PRE: 1344 case ARM::LDC_OFFSET: 1345 case ARM::LDCL_OFFSET: 1346 case ARM::LDC_PRE: 1347 case ARM::LDCL_PRE: 1348 case ARM::STC_OFFSET: 1349 case ARM::STCL_OFFSET: 1350 case ARM::STC_PRE: 1351 case ARM::STCL_PRE: 1352 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1353 Inst.addOperand(MCOperand::CreateImm(imm)); 1354 break; 1355 case ARM::t2LDC2_POST: 1356 case ARM::t2LDC2L_POST: 1357 case ARM::t2STC2_POST: 1358 case ARM::t2STC2L_POST: 1359 case ARM::LDC2_POST: 1360 case ARM::LDC2L_POST: 1361 case ARM::STC2_POST: 1362 case ARM::STC2L_POST: 1363 case ARM::t2LDC_POST: 1364 case ARM::t2LDCL_POST: 1365 case ARM::t2STC_POST: 1366 case ARM::t2STCL_POST: 1367 case ARM::LDC_POST: 1368 case ARM::LDCL_POST: 1369 case ARM::STC_POST: 1370 case ARM::STCL_POST: 1371 imm |= U << 8; 1372 // fall through. 1373 default: 1374 // The 'option' variant doesn't encode 'U' in the immediate since 1375 // the immediate is unsigned [0,255]. 1376 Inst.addOperand(MCOperand::CreateImm(imm)); 1377 break; 1378 } 1379 1380 switch (Inst.getOpcode()) { 1381 case ARM::LDC_OFFSET: 1382 case ARM::LDC_PRE: 1383 case ARM::LDC_POST: 1384 case ARM::LDC_OPTION: 1385 case ARM::LDCL_OFFSET: 1386 case ARM::LDCL_PRE: 1387 case ARM::LDCL_POST: 1388 case ARM::LDCL_OPTION: 1389 case ARM::STC_OFFSET: 1390 case ARM::STC_PRE: 1391 case ARM::STC_POST: 1392 case ARM::STC_OPTION: 1393 case ARM::STCL_OFFSET: 1394 case ARM::STCL_PRE: 1395 case ARM::STCL_POST: 1396 case ARM::STCL_OPTION: 1397 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1398 return MCDisassembler::Fail; 1399 break; 1400 default: 1401 break; 1402 } 1403 1404 return S; 1405} 1406 1407static DecodeStatus 1408DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1409 uint64_t Address, const void *Decoder) { 1410 DecodeStatus S = MCDisassembler::Success; 1411 1412 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1413 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1414 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1415 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1416 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1417 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1418 unsigned P = fieldFromInstruction(Insn, 24, 1); 1419 unsigned W = fieldFromInstruction(Insn, 21, 1); 1420 1421 // On stores, the writeback operand precedes Rt. 1422 switch (Inst.getOpcode()) { 1423 case ARM::STR_POST_IMM: 1424 case ARM::STR_POST_REG: 1425 case ARM::STRB_POST_IMM: 1426 case ARM::STRB_POST_REG: 1427 case ARM::STRT_POST_REG: 1428 case ARM::STRT_POST_IMM: 1429 case ARM::STRBT_POST_REG: 1430 case ARM::STRBT_POST_IMM: 1431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1432 return MCDisassembler::Fail; 1433 break; 1434 default: 1435 break; 1436 } 1437 1438 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1439 return MCDisassembler::Fail; 1440 1441 // On loads, the writeback operand comes after Rt. 1442 switch (Inst.getOpcode()) { 1443 case ARM::LDR_POST_IMM: 1444 case ARM::LDR_POST_REG: 1445 case ARM::LDRB_POST_IMM: 1446 case ARM::LDRB_POST_REG: 1447 case ARM::LDRBT_POST_REG: 1448 case ARM::LDRBT_POST_IMM: 1449 case ARM::LDRT_POST_REG: 1450 case ARM::LDRT_POST_IMM: 1451 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1452 return MCDisassembler::Fail; 1453 break; 1454 default: 1455 break; 1456 } 1457 1458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1459 return MCDisassembler::Fail; 1460 1461 ARM_AM::AddrOpc Op = ARM_AM::add; 1462 if (!fieldFromInstruction(Insn, 23, 1)) 1463 Op = ARM_AM::sub; 1464 1465 bool writeback = (P == 0) || (W == 1); 1466 unsigned idx_mode = 0; 1467 if (P && writeback) 1468 idx_mode = ARMII::IndexModePre; 1469 else if (!P && writeback) 1470 idx_mode = ARMII::IndexModePost; 1471 1472 if (writeback && (Rn == 15 || Rn == Rt)) 1473 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1474 1475 if (reg) { 1476 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1477 return MCDisassembler::Fail; 1478 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1479 switch( fieldFromInstruction(Insn, 5, 2)) { 1480 case 0: 1481 Opc = ARM_AM::lsl; 1482 break; 1483 case 1: 1484 Opc = ARM_AM::lsr; 1485 break; 1486 case 2: 1487 Opc = ARM_AM::asr; 1488 break; 1489 case 3: 1490 Opc = ARM_AM::ror; 1491 break; 1492 default: 1493 return MCDisassembler::Fail; 1494 } 1495 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1496 if (Opc == ARM_AM::ror && amt == 0) 1497 Opc = ARM_AM::rrx; 1498 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1499 1500 Inst.addOperand(MCOperand::CreateImm(imm)); 1501 } else { 1502 Inst.addOperand(MCOperand::CreateReg(0)); 1503 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1504 Inst.addOperand(MCOperand::CreateImm(tmp)); 1505 } 1506 1507 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1508 return MCDisassembler::Fail; 1509 1510 return S; 1511} 1512 1513static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1514 uint64_t Address, const void *Decoder) { 1515 DecodeStatus S = MCDisassembler::Success; 1516 1517 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1518 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1519 unsigned type = fieldFromInstruction(Val, 5, 2); 1520 unsigned imm = fieldFromInstruction(Val, 7, 5); 1521 unsigned U = fieldFromInstruction(Val, 12, 1); 1522 1523 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1524 switch (type) { 1525 case 0: 1526 ShOp = ARM_AM::lsl; 1527 break; 1528 case 1: 1529 ShOp = ARM_AM::lsr; 1530 break; 1531 case 2: 1532 ShOp = ARM_AM::asr; 1533 break; 1534 case 3: 1535 ShOp = ARM_AM::ror; 1536 break; 1537 } 1538 1539 if (ShOp == ARM_AM::ror && imm == 0) 1540 ShOp = ARM_AM::rrx; 1541 1542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1543 return MCDisassembler::Fail; 1544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1545 return MCDisassembler::Fail; 1546 unsigned shift; 1547 if (U) 1548 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1549 else 1550 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1551 Inst.addOperand(MCOperand::CreateImm(shift)); 1552 1553 return S; 1554} 1555 1556static DecodeStatus 1557DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1558 uint64_t Address, const void *Decoder) { 1559 DecodeStatus S = MCDisassembler::Success; 1560 1561 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1562 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1563 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1564 unsigned type = fieldFromInstruction(Insn, 22, 1); 1565 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1566 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1567 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1568 unsigned W = fieldFromInstruction(Insn, 21, 1); 1569 unsigned P = fieldFromInstruction(Insn, 24, 1); 1570 unsigned Rt2 = Rt + 1; 1571 1572 bool writeback = (W == 1) | (P == 0); 1573 1574 // For {LD,ST}RD, Rt must be even, else undefined. 1575 switch (Inst.getOpcode()) { 1576 case ARM::STRD: 1577 case ARM::STRD_PRE: 1578 case ARM::STRD_POST: 1579 case ARM::LDRD: 1580 case ARM::LDRD_PRE: 1581 case ARM::LDRD_POST: 1582 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1583 break; 1584 default: 1585 break; 1586 } 1587 switch (Inst.getOpcode()) { 1588 case ARM::STRD: 1589 case ARM::STRD_PRE: 1590 case ARM::STRD_POST: 1591 if (P == 0 && W == 1) 1592 S = MCDisassembler::SoftFail; 1593 1594 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1595 S = MCDisassembler::SoftFail; 1596 if (type && Rm == 15) 1597 S = MCDisassembler::SoftFail; 1598 if (Rt2 == 15) 1599 S = MCDisassembler::SoftFail; 1600 if (!type && fieldFromInstruction(Insn, 8, 4)) 1601 S = MCDisassembler::SoftFail; 1602 break; 1603 case ARM::STRH: 1604 case ARM::STRH_PRE: 1605 case ARM::STRH_POST: 1606 if (Rt == 15) 1607 S = MCDisassembler::SoftFail; 1608 if (writeback && (Rn == 15 || Rn == Rt)) 1609 S = MCDisassembler::SoftFail; 1610 if (!type && Rm == 15) 1611 S = MCDisassembler::SoftFail; 1612 break; 1613 case ARM::LDRD: 1614 case ARM::LDRD_PRE: 1615 case ARM::LDRD_POST: 1616 if (type && Rn == 15){ 1617 if (Rt2 == 15) 1618 S = MCDisassembler::SoftFail; 1619 break; 1620 } 1621 if (P == 0 && W == 1) 1622 S = MCDisassembler::SoftFail; 1623 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1624 S = MCDisassembler::SoftFail; 1625 if (!type && writeback && Rn == 15) 1626 S = MCDisassembler::SoftFail; 1627 if (writeback && (Rn == Rt || Rn == Rt2)) 1628 S = MCDisassembler::SoftFail; 1629 break; 1630 case ARM::LDRH: 1631 case ARM::LDRH_PRE: 1632 case ARM::LDRH_POST: 1633 if (type && Rn == 15){ 1634 if (Rt == 15) 1635 S = MCDisassembler::SoftFail; 1636 break; 1637 } 1638 if (Rt == 15) 1639 S = MCDisassembler::SoftFail; 1640 if (!type && Rm == 15) 1641 S = MCDisassembler::SoftFail; 1642 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1643 S = MCDisassembler::SoftFail; 1644 break; 1645 case ARM::LDRSH: 1646 case ARM::LDRSH_PRE: 1647 case ARM::LDRSH_POST: 1648 case ARM::LDRSB: 1649 case ARM::LDRSB_PRE: 1650 case ARM::LDRSB_POST: 1651 if (type && Rn == 15){ 1652 if (Rt == 15) 1653 S = MCDisassembler::SoftFail; 1654 break; 1655 } 1656 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1657 S = MCDisassembler::SoftFail; 1658 if (!type && (Rt == 15 || Rm == 15)) 1659 S = MCDisassembler::SoftFail; 1660 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1661 S = MCDisassembler::SoftFail; 1662 break; 1663 default: 1664 break; 1665 } 1666 1667 if (writeback) { // Writeback 1668 if (P) 1669 U |= ARMII::IndexModePre << 9; 1670 else 1671 U |= ARMII::IndexModePost << 9; 1672 1673 // On stores, the writeback operand precedes Rt. 1674 switch (Inst.getOpcode()) { 1675 case ARM::STRD: 1676 case ARM::STRD_PRE: 1677 case ARM::STRD_POST: 1678 case ARM::STRH: 1679 case ARM::STRH_PRE: 1680 case ARM::STRH_POST: 1681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1682 return MCDisassembler::Fail; 1683 break; 1684 default: 1685 break; 1686 } 1687 } 1688 1689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1690 return MCDisassembler::Fail; 1691 switch (Inst.getOpcode()) { 1692 case ARM::STRD: 1693 case ARM::STRD_PRE: 1694 case ARM::STRD_POST: 1695 case ARM::LDRD: 1696 case ARM::LDRD_PRE: 1697 case ARM::LDRD_POST: 1698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1699 return MCDisassembler::Fail; 1700 break; 1701 default: 1702 break; 1703 } 1704 1705 if (writeback) { 1706 // On loads, the writeback operand comes after Rt. 1707 switch (Inst.getOpcode()) { 1708 case ARM::LDRD: 1709 case ARM::LDRD_PRE: 1710 case ARM::LDRD_POST: 1711 case ARM::LDRH: 1712 case ARM::LDRH_PRE: 1713 case ARM::LDRH_POST: 1714 case ARM::LDRSH: 1715 case ARM::LDRSH_PRE: 1716 case ARM::LDRSH_POST: 1717 case ARM::LDRSB: 1718 case ARM::LDRSB_PRE: 1719 case ARM::LDRSB_POST: 1720 case ARM::LDRHTr: 1721 case ARM::LDRSBTr: 1722 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1723 return MCDisassembler::Fail; 1724 break; 1725 default: 1726 break; 1727 } 1728 } 1729 1730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1731 return MCDisassembler::Fail; 1732 1733 if (type) { 1734 Inst.addOperand(MCOperand::CreateReg(0)); 1735 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1736 } else { 1737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1738 return MCDisassembler::Fail; 1739 Inst.addOperand(MCOperand::CreateImm(U)); 1740 } 1741 1742 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1743 return MCDisassembler::Fail; 1744 1745 return S; 1746} 1747 1748static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1749 uint64_t Address, const void *Decoder) { 1750 DecodeStatus S = MCDisassembler::Success; 1751 1752 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1753 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1754 1755 switch (mode) { 1756 case 0: 1757 mode = ARM_AM::da; 1758 break; 1759 case 1: 1760 mode = ARM_AM::ia; 1761 break; 1762 case 2: 1763 mode = ARM_AM::db; 1764 break; 1765 case 3: 1766 mode = ARM_AM::ib; 1767 break; 1768 } 1769 1770 Inst.addOperand(MCOperand::CreateImm(mode)); 1771 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1772 return MCDisassembler::Fail; 1773 1774 return S; 1775} 1776 1777static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1778 uint64_t Address, const void *Decoder) { 1779 DecodeStatus S = MCDisassembler::Success; 1780 1781 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1782 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1783 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1784 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1785 1786 if (pred == 0xF) 1787 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1788 1789 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1790 return MCDisassembler::Fail; 1791 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1792 return MCDisassembler::Fail; 1793 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1794 return MCDisassembler::Fail; 1795 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1796 return MCDisassembler::Fail; 1797 return S; 1798} 1799 1800static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1801 unsigned Insn, 1802 uint64_t Address, const void *Decoder) { 1803 DecodeStatus S = MCDisassembler::Success; 1804 1805 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1806 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1807 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1808 1809 if (pred == 0xF) { 1810 // Ambiguous with RFE and SRS 1811 switch (Inst.getOpcode()) { 1812 case ARM::LDMDA: 1813 Inst.setOpcode(ARM::RFEDA); 1814 break; 1815 case ARM::LDMDA_UPD: 1816 Inst.setOpcode(ARM::RFEDA_UPD); 1817 break; 1818 case ARM::LDMDB: 1819 Inst.setOpcode(ARM::RFEDB); 1820 break; 1821 case ARM::LDMDB_UPD: 1822 Inst.setOpcode(ARM::RFEDB_UPD); 1823 break; 1824 case ARM::LDMIA: 1825 Inst.setOpcode(ARM::RFEIA); 1826 break; 1827 case ARM::LDMIA_UPD: 1828 Inst.setOpcode(ARM::RFEIA_UPD); 1829 break; 1830 case ARM::LDMIB: 1831 Inst.setOpcode(ARM::RFEIB); 1832 break; 1833 case ARM::LDMIB_UPD: 1834 Inst.setOpcode(ARM::RFEIB_UPD); 1835 break; 1836 case ARM::STMDA: 1837 Inst.setOpcode(ARM::SRSDA); 1838 break; 1839 case ARM::STMDA_UPD: 1840 Inst.setOpcode(ARM::SRSDA_UPD); 1841 break; 1842 case ARM::STMDB: 1843 Inst.setOpcode(ARM::SRSDB); 1844 break; 1845 case ARM::STMDB_UPD: 1846 Inst.setOpcode(ARM::SRSDB_UPD); 1847 break; 1848 case ARM::STMIA: 1849 Inst.setOpcode(ARM::SRSIA); 1850 break; 1851 case ARM::STMIA_UPD: 1852 Inst.setOpcode(ARM::SRSIA_UPD); 1853 break; 1854 case ARM::STMIB: 1855 Inst.setOpcode(ARM::SRSIB); 1856 break; 1857 case ARM::STMIB_UPD: 1858 Inst.setOpcode(ARM::SRSIB_UPD); 1859 break; 1860 default: 1861 return MCDisassembler::Fail; 1862 } 1863 1864 // For stores (which become SRS's, the only operand is the mode. 1865 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1866 // Check SRS encoding constraints 1867 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1868 fieldFromInstruction(Insn, 20, 1) == 0)) 1869 return MCDisassembler::Fail; 1870 1871 Inst.addOperand( 1872 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1873 return S; 1874 } 1875 1876 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1877 } 1878 1879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1880 return MCDisassembler::Fail; 1881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1882 return MCDisassembler::Fail; // Tied 1883 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1884 return MCDisassembler::Fail; 1885 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1886 return MCDisassembler::Fail; 1887 1888 return S; 1889} 1890 1891static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1892 uint64_t Address, const void *Decoder) { 1893 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1894 unsigned M = fieldFromInstruction(Insn, 17, 1); 1895 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1896 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1897 1898 DecodeStatus S = MCDisassembler::Success; 1899 1900 // This decoder is called from multiple location that do not check 1901 // the full encoding is valid before they do. 1902 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1903 fieldFromInstruction(Insn, 16, 1) != 0 || 1904 fieldFromInstruction(Insn, 20, 8) != 0x10) 1905 return MCDisassembler::Fail; 1906 1907 // imod == '01' --> UNPREDICTABLE 1908 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1909 // return failure here. The '01' imod value is unprintable, so there's 1910 // nothing useful we could do even if we returned UNPREDICTABLE. 1911 1912 if (imod == 1) return MCDisassembler::Fail; 1913 1914 if (imod && M) { 1915 Inst.setOpcode(ARM::CPS3p); 1916 Inst.addOperand(MCOperand::CreateImm(imod)); 1917 Inst.addOperand(MCOperand::CreateImm(iflags)); 1918 Inst.addOperand(MCOperand::CreateImm(mode)); 1919 } else if (imod && !M) { 1920 Inst.setOpcode(ARM::CPS2p); 1921 Inst.addOperand(MCOperand::CreateImm(imod)); 1922 Inst.addOperand(MCOperand::CreateImm(iflags)); 1923 if (mode) S = MCDisassembler::SoftFail; 1924 } else if (!imod && M) { 1925 Inst.setOpcode(ARM::CPS1p); 1926 Inst.addOperand(MCOperand::CreateImm(mode)); 1927 if (iflags) S = MCDisassembler::SoftFail; 1928 } else { 1929 // imod == '00' && M == '0' --> UNPREDICTABLE 1930 Inst.setOpcode(ARM::CPS1p); 1931 Inst.addOperand(MCOperand::CreateImm(mode)); 1932 S = MCDisassembler::SoftFail; 1933 } 1934 1935 return S; 1936} 1937 1938static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1939 uint64_t Address, const void *Decoder) { 1940 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1941 unsigned M = fieldFromInstruction(Insn, 8, 1); 1942 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1943 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1944 1945 DecodeStatus S = MCDisassembler::Success; 1946 1947 // imod == '01' --> UNPREDICTABLE 1948 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1949 // return failure here. The '01' imod value is unprintable, so there's 1950 // nothing useful we could do even if we returned UNPREDICTABLE. 1951 1952 if (imod == 1) return MCDisassembler::Fail; 1953 1954 if (imod && M) { 1955 Inst.setOpcode(ARM::t2CPS3p); 1956 Inst.addOperand(MCOperand::CreateImm(imod)); 1957 Inst.addOperand(MCOperand::CreateImm(iflags)); 1958 Inst.addOperand(MCOperand::CreateImm(mode)); 1959 } else if (imod && !M) { 1960 Inst.setOpcode(ARM::t2CPS2p); 1961 Inst.addOperand(MCOperand::CreateImm(imod)); 1962 Inst.addOperand(MCOperand::CreateImm(iflags)); 1963 if (mode) S = MCDisassembler::SoftFail; 1964 } else if (!imod && M) { 1965 Inst.setOpcode(ARM::t2CPS1p); 1966 Inst.addOperand(MCOperand::CreateImm(mode)); 1967 if (iflags) S = MCDisassembler::SoftFail; 1968 } else { 1969 // imod == '00' && M == '0' --> this is a HINT instruction 1970 int imm = fieldFromInstruction(Insn, 0, 8); 1971 // HINT are defined only for immediate in [0..4] 1972 if(imm > 4) return MCDisassembler::Fail; 1973 Inst.setOpcode(ARM::t2HINT); 1974 Inst.addOperand(MCOperand::CreateImm(imm)); 1975 } 1976 1977 return S; 1978} 1979 1980static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1981 uint64_t Address, const void *Decoder) { 1982 DecodeStatus S = MCDisassembler::Success; 1983 1984 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1985 unsigned imm = 0; 1986 1987 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1988 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1989 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1990 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1991 1992 if (Inst.getOpcode() == ARM::t2MOVTi16) 1993 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1994 return MCDisassembler::Fail; 1995 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1996 return MCDisassembler::Fail; 1997 1998 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1999 Inst.addOperand(MCOperand::CreateImm(imm)); 2000 2001 return S; 2002} 2003 2004static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2005 uint64_t Address, const void *Decoder) { 2006 DecodeStatus S = MCDisassembler::Success; 2007 2008 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2009 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2010 unsigned imm = 0; 2011 2012 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2013 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2014 2015 if (Inst.getOpcode() == ARM::MOVTi16) 2016 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2017 return MCDisassembler::Fail; 2018 2019 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2020 return MCDisassembler::Fail; 2021 2022 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2023 Inst.addOperand(MCOperand::CreateImm(imm)); 2024 2025 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2026 return MCDisassembler::Fail; 2027 2028 return S; 2029} 2030 2031static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2032 uint64_t Address, const void *Decoder) { 2033 DecodeStatus S = MCDisassembler::Success; 2034 2035 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2036 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2037 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2038 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2039 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2040 2041 if (pred == 0xF) 2042 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2043 2044 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2045 return MCDisassembler::Fail; 2046 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2047 return MCDisassembler::Fail; 2048 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2049 return MCDisassembler::Fail; 2050 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2051 return MCDisassembler::Fail; 2052 2053 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2054 return MCDisassembler::Fail; 2055 2056 return S; 2057} 2058 2059static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2060 uint64_t Address, const void *Decoder) { 2061 DecodeStatus S = MCDisassembler::Success; 2062 2063 unsigned add = fieldFromInstruction(Val, 12, 1); 2064 unsigned imm = fieldFromInstruction(Val, 0, 12); 2065 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2066 2067 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2068 return MCDisassembler::Fail; 2069 2070 if (!add) imm *= -1; 2071 if (imm == 0 && !add) imm = INT32_MIN; 2072 Inst.addOperand(MCOperand::CreateImm(imm)); 2073 if (Rn == 15) 2074 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2075 2076 return S; 2077} 2078 2079static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2080 uint64_t Address, const void *Decoder) { 2081 DecodeStatus S = MCDisassembler::Success; 2082 2083 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2084 unsigned U = fieldFromInstruction(Val, 8, 1); 2085 unsigned imm = fieldFromInstruction(Val, 0, 8); 2086 2087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2088 return MCDisassembler::Fail; 2089 2090 if (U) 2091 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2092 else 2093 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2094 2095 return S; 2096} 2097 2098static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2099 uint64_t Address, const void *Decoder) { 2100 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2101} 2102 2103static DecodeStatus 2104DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2105 uint64_t Address, const void *Decoder) { 2106 DecodeStatus Status = MCDisassembler::Success; 2107 2108 // Note the J1 and J2 values are from the encoded instruction. So here 2109 // change them to I1 and I2 values via as documented: 2110 // I1 = NOT(J1 EOR S); 2111 // I2 = NOT(J2 EOR S); 2112 // and build the imm32 with one trailing zero as documented: 2113 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2114 unsigned S = fieldFromInstruction(Insn, 26, 1); 2115 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2116 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2117 unsigned I1 = !(J1 ^ S); 2118 unsigned I2 = !(J2 ^ S); 2119 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2120 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2121 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2122 int imm32 = SignExtend32<25>(tmp << 1); 2123 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2124 true, 4, Inst, Decoder)) 2125 Inst.addOperand(MCOperand::CreateImm(imm32)); 2126 2127 return Status; 2128} 2129 2130static DecodeStatus 2131DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2132 uint64_t Address, const void *Decoder) { 2133 DecodeStatus S = MCDisassembler::Success; 2134 2135 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2136 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2137 2138 if (pred == 0xF) { 2139 Inst.setOpcode(ARM::BLXi); 2140 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2141 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2142 true, 4, Inst, Decoder)) 2143 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2144 return S; 2145 } 2146 2147 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2148 true, 4, Inst, Decoder)) 2149 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2150 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2151 return MCDisassembler::Fail; 2152 2153 return S; 2154} 2155 2156 2157static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2158 uint64_t Address, const void *Decoder) { 2159 DecodeStatus S = MCDisassembler::Success; 2160 2161 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2162 unsigned align = fieldFromInstruction(Val, 4, 2); 2163 2164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2165 return MCDisassembler::Fail; 2166 if (!align) 2167 Inst.addOperand(MCOperand::CreateImm(0)); 2168 else 2169 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2170 2171 return S; 2172} 2173 2174static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2175 uint64_t Address, const void *Decoder) { 2176 DecodeStatus S = MCDisassembler::Success; 2177 2178 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2179 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2180 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2181 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2182 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2183 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2184 2185 // First output register 2186 switch (Inst.getOpcode()) { 2187 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2188 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2189 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2190 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2191 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2192 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2193 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2194 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2195 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2196 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2197 return MCDisassembler::Fail; 2198 break; 2199 case ARM::VLD2b16: 2200 case ARM::VLD2b32: 2201 case ARM::VLD2b8: 2202 case ARM::VLD2b16wb_fixed: 2203 case ARM::VLD2b16wb_register: 2204 case ARM::VLD2b32wb_fixed: 2205 case ARM::VLD2b32wb_register: 2206 case ARM::VLD2b8wb_fixed: 2207 case ARM::VLD2b8wb_register: 2208 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2209 return MCDisassembler::Fail; 2210 break; 2211 default: 2212 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2213 return MCDisassembler::Fail; 2214 } 2215 2216 // Second output register 2217 switch (Inst.getOpcode()) { 2218 case ARM::VLD3d8: 2219 case ARM::VLD3d16: 2220 case ARM::VLD3d32: 2221 case ARM::VLD3d8_UPD: 2222 case ARM::VLD3d16_UPD: 2223 case ARM::VLD3d32_UPD: 2224 case ARM::VLD4d8: 2225 case ARM::VLD4d16: 2226 case ARM::VLD4d32: 2227 case ARM::VLD4d8_UPD: 2228 case ARM::VLD4d16_UPD: 2229 case ARM::VLD4d32_UPD: 2230 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2231 return MCDisassembler::Fail; 2232 break; 2233 case ARM::VLD3q8: 2234 case ARM::VLD3q16: 2235 case ARM::VLD3q32: 2236 case ARM::VLD3q8_UPD: 2237 case ARM::VLD3q16_UPD: 2238 case ARM::VLD3q32_UPD: 2239 case ARM::VLD4q8: 2240 case ARM::VLD4q16: 2241 case ARM::VLD4q32: 2242 case ARM::VLD4q8_UPD: 2243 case ARM::VLD4q16_UPD: 2244 case ARM::VLD4q32_UPD: 2245 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2246 return MCDisassembler::Fail; 2247 default: 2248 break; 2249 } 2250 2251 // Third output register 2252 switch(Inst.getOpcode()) { 2253 case ARM::VLD3d8: 2254 case ARM::VLD3d16: 2255 case ARM::VLD3d32: 2256 case ARM::VLD3d8_UPD: 2257 case ARM::VLD3d16_UPD: 2258 case ARM::VLD3d32_UPD: 2259 case ARM::VLD4d8: 2260 case ARM::VLD4d16: 2261 case ARM::VLD4d32: 2262 case ARM::VLD4d8_UPD: 2263 case ARM::VLD4d16_UPD: 2264 case ARM::VLD4d32_UPD: 2265 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2266 return MCDisassembler::Fail; 2267 break; 2268 case ARM::VLD3q8: 2269 case ARM::VLD3q16: 2270 case ARM::VLD3q32: 2271 case ARM::VLD3q8_UPD: 2272 case ARM::VLD3q16_UPD: 2273 case ARM::VLD3q32_UPD: 2274 case ARM::VLD4q8: 2275 case ARM::VLD4q16: 2276 case ARM::VLD4q32: 2277 case ARM::VLD4q8_UPD: 2278 case ARM::VLD4q16_UPD: 2279 case ARM::VLD4q32_UPD: 2280 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2281 return MCDisassembler::Fail; 2282 break; 2283 default: 2284 break; 2285 } 2286 2287 // Fourth output register 2288 switch (Inst.getOpcode()) { 2289 case ARM::VLD4d8: 2290 case ARM::VLD4d16: 2291 case ARM::VLD4d32: 2292 case ARM::VLD4d8_UPD: 2293 case ARM::VLD4d16_UPD: 2294 case ARM::VLD4d32_UPD: 2295 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2296 return MCDisassembler::Fail; 2297 break; 2298 case ARM::VLD4q8: 2299 case ARM::VLD4q16: 2300 case ARM::VLD4q32: 2301 case ARM::VLD4q8_UPD: 2302 case ARM::VLD4q16_UPD: 2303 case ARM::VLD4q32_UPD: 2304 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2305 return MCDisassembler::Fail; 2306 break; 2307 default: 2308 break; 2309 } 2310 2311 // Writeback operand 2312 switch (Inst.getOpcode()) { 2313 case ARM::VLD1d8wb_fixed: 2314 case ARM::VLD1d16wb_fixed: 2315 case ARM::VLD1d32wb_fixed: 2316 case ARM::VLD1d64wb_fixed: 2317 case ARM::VLD1d8wb_register: 2318 case ARM::VLD1d16wb_register: 2319 case ARM::VLD1d32wb_register: 2320 case ARM::VLD1d64wb_register: 2321 case ARM::VLD1q8wb_fixed: 2322 case ARM::VLD1q16wb_fixed: 2323 case ARM::VLD1q32wb_fixed: 2324 case ARM::VLD1q64wb_fixed: 2325 case ARM::VLD1q8wb_register: 2326 case ARM::VLD1q16wb_register: 2327 case ARM::VLD1q32wb_register: 2328 case ARM::VLD1q64wb_register: 2329 case ARM::VLD1d8Twb_fixed: 2330 case ARM::VLD1d8Twb_register: 2331 case ARM::VLD1d16Twb_fixed: 2332 case ARM::VLD1d16Twb_register: 2333 case ARM::VLD1d32Twb_fixed: 2334 case ARM::VLD1d32Twb_register: 2335 case ARM::VLD1d64Twb_fixed: 2336 case ARM::VLD1d64Twb_register: 2337 case ARM::VLD1d8Qwb_fixed: 2338 case ARM::VLD1d8Qwb_register: 2339 case ARM::VLD1d16Qwb_fixed: 2340 case ARM::VLD1d16Qwb_register: 2341 case ARM::VLD1d32Qwb_fixed: 2342 case ARM::VLD1d32Qwb_register: 2343 case ARM::VLD1d64Qwb_fixed: 2344 case ARM::VLD1d64Qwb_register: 2345 case ARM::VLD2d8wb_fixed: 2346 case ARM::VLD2d16wb_fixed: 2347 case ARM::VLD2d32wb_fixed: 2348 case ARM::VLD2q8wb_fixed: 2349 case ARM::VLD2q16wb_fixed: 2350 case ARM::VLD2q32wb_fixed: 2351 case ARM::VLD2d8wb_register: 2352 case ARM::VLD2d16wb_register: 2353 case ARM::VLD2d32wb_register: 2354 case ARM::VLD2q8wb_register: 2355 case ARM::VLD2q16wb_register: 2356 case ARM::VLD2q32wb_register: 2357 case ARM::VLD2b8wb_fixed: 2358 case ARM::VLD2b16wb_fixed: 2359 case ARM::VLD2b32wb_fixed: 2360 case ARM::VLD2b8wb_register: 2361 case ARM::VLD2b16wb_register: 2362 case ARM::VLD2b32wb_register: 2363 Inst.addOperand(MCOperand::CreateImm(0)); 2364 break; 2365 case ARM::VLD3d8_UPD: 2366 case ARM::VLD3d16_UPD: 2367 case ARM::VLD3d32_UPD: 2368 case ARM::VLD3q8_UPD: 2369 case ARM::VLD3q16_UPD: 2370 case ARM::VLD3q32_UPD: 2371 case ARM::VLD4d8_UPD: 2372 case ARM::VLD4d16_UPD: 2373 case ARM::VLD4d32_UPD: 2374 case ARM::VLD4q8_UPD: 2375 case ARM::VLD4q16_UPD: 2376 case ARM::VLD4q32_UPD: 2377 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2378 return MCDisassembler::Fail; 2379 break; 2380 default: 2381 break; 2382 } 2383 2384 // AddrMode6 Base (register+alignment) 2385 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2386 return MCDisassembler::Fail; 2387 2388 // AddrMode6 Offset (register) 2389 switch (Inst.getOpcode()) { 2390 default: 2391 // The below have been updated to have explicit am6offset split 2392 // between fixed and register offset. For those instructions not 2393 // yet updated, we need to add an additional reg0 operand for the 2394 // fixed variant. 2395 // 2396 // The fixed offset encodes as Rm == 0xd, so we check for that. 2397 if (Rm == 0xd) { 2398 Inst.addOperand(MCOperand::CreateReg(0)); 2399 break; 2400 } 2401 // Fall through to handle the register offset variant. 2402 case ARM::VLD1d8wb_fixed: 2403 case ARM::VLD1d16wb_fixed: 2404 case ARM::VLD1d32wb_fixed: 2405 case ARM::VLD1d64wb_fixed: 2406 case ARM::VLD1d8Twb_fixed: 2407 case ARM::VLD1d16Twb_fixed: 2408 case ARM::VLD1d32Twb_fixed: 2409 case ARM::VLD1d64Twb_fixed: 2410 case ARM::VLD1d8Qwb_fixed: 2411 case ARM::VLD1d16Qwb_fixed: 2412 case ARM::VLD1d32Qwb_fixed: 2413 case ARM::VLD1d64Qwb_fixed: 2414 case ARM::VLD1d8wb_register: 2415 case ARM::VLD1d16wb_register: 2416 case ARM::VLD1d32wb_register: 2417 case ARM::VLD1d64wb_register: 2418 case ARM::VLD1q8wb_fixed: 2419 case ARM::VLD1q16wb_fixed: 2420 case ARM::VLD1q32wb_fixed: 2421 case ARM::VLD1q64wb_fixed: 2422 case ARM::VLD1q8wb_register: 2423 case ARM::VLD1q16wb_register: 2424 case ARM::VLD1q32wb_register: 2425 case ARM::VLD1q64wb_register: 2426 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2427 // variant encodes Rm == 0xf. Anything else is a register offset post- 2428 // increment and we need to add the register operand to the instruction. 2429 if (Rm != 0xD && Rm != 0xF && 2430 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2431 return MCDisassembler::Fail; 2432 break; 2433 case ARM::VLD2d8wb_fixed: 2434 case ARM::VLD2d16wb_fixed: 2435 case ARM::VLD2d32wb_fixed: 2436 case ARM::VLD2b8wb_fixed: 2437 case ARM::VLD2b16wb_fixed: 2438 case ARM::VLD2b32wb_fixed: 2439 case ARM::VLD2q8wb_fixed: 2440 case ARM::VLD2q16wb_fixed: 2441 case ARM::VLD2q32wb_fixed: 2442 break; 2443 } 2444 2445 return S; 2446} 2447 2448static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2449 uint64_t Address, const void *Decoder) { 2450 unsigned type = fieldFromInstruction(Insn, 8, 4); 2451 unsigned align = fieldFromInstruction(Insn, 4, 2); 2452 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2453 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2454 if (type == 10 && align == 3) return MCDisassembler::Fail; 2455 2456 unsigned load = fieldFromInstruction(Insn, 21, 1); 2457 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2458 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2459} 2460 2461static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2462 uint64_t Address, const void *Decoder) { 2463 unsigned size = fieldFromInstruction(Insn, 6, 2); 2464 if (size == 3) return MCDisassembler::Fail; 2465 2466 unsigned type = fieldFromInstruction(Insn, 8, 4); 2467 unsigned align = fieldFromInstruction(Insn, 4, 2); 2468 if (type == 8 && align == 3) return MCDisassembler::Fail; 2469 if (type == 9 && align == 3) return MCDisassembler::Fail; 2470 2471 unsigned load = fieldFromInstruction(Insn, 21, 1); 2472 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2473 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2474} 2475 2476static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2477 uint64_t Address, const void *Decoder) { 2478 unsigned size = fieldFromInstruction(Insn, 6, 2); 2479 if (size == 3) return MCDisassembler::Fail; 2480 2481 unsigned align = fieldFromInstruction(Insn, 4, 2); 2482 if (align & 2) return MCDisassembler::Fail; 2483 2484 unsigned load = fieldFromInstruction(Insn, 21, 1); 2485 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2486 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2487} 2488 2489static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2490 uint64_t Address, const void *Decoder) { 2491 unsigned size = fieldFromInstruction(Insn, 6, 2); 2492 if (size == 3) return MCDisassembler::Fail; 2493 2494 unsigned load = fieldFromInstruction(Insn, 21, 1); 2495 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2496 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2497} 2498 2499static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2500 uint64_t Address, const void *Decoder) { 2501 DecodeStatus S = MCDisassembler::Success; 2502 2503 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2504 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2505 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2506 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2507 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2508 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2509 2510 // Writeback Operand 2511 switch (Inst.getOpcode()) { 2512 case ARM::VST1d8wb_fixed: 2513 case ARM::VST1d16wb_fixed: 2514 case ARM::VST1d32wb_fixed: 2515 case ARM::VST1d64wb_fixed: 2516 case ARM::VST1d8wb_register: 2517 case ARM::VST1d16wb_register: 2518 case ARM::VST1d32wb_register: 2519 case ARM::VST1d64wb_register: 2520 case ARM::VST1q8wb_fixed: 2521 case ARM::VST1q16wb_fixed: 2522 case ARM::VST1q32wb_fixed: 2523 case ARM::VST1q64wb_fixed: 2524 case ARM::VST1q8wb_register: 2525 case ARM::VST1q16wb_register: 2526 case ARM::VST1q32wb_register: 2527 case ARM::VST1q64wb_register: 2528 case ARM::VST1d8Twb_fixed: 2529 case ARM::VST1d16Twb_fixed: 2530 case ARM::VST1d32Twb_fixed: 2531 case ARM::VST1d64Twb_fixed: 2532 case ARM::VST1d8Twb_register: 2533 case ARM::VST1d16Twb_register: 2534 case ARM::VST1d32Twb_register: 2535 case ARM::VST1d64Twb_register: 2536 case ARM::VST1d8Qwb_fixed: 2537 case ARM::VST1d16Qwb_fixed: 2538 case ARM::VST1d32Qwb_fixed: 2539 case ARM::VST1d64Qwb_fixed: 2540 case ARM::VST1d8Qwb_register: 2541 case ARM::VST1d16Qwb_register: 2542 case ARM::VST1d32Qwb_register: 2543 case ARM::VST1d64Qwb_register: 2544 case ARM::VST2d8wb_fixed: 2545 case ARM::VST2d16wb_fixed: 2546 case ARM::VST2d32wb_fixed: 2547 case ARM::VST2d8wb_register: 2548 case ARM::VST2d16wb_register: 2549 case ARM::VST2d32wb_register: 2550 case ARM::VST2q8wb_fixed: 2551 case ARM::VST2q16wb_fixed: 2552 case ARM::VST2q32wb_fixed: 2553 case ARM::VST2q8wb_register: 2554 case ARM::VST2q16wb_register: 2555 case ARM::VST2q32wb_register: 2556 case ARM::VST2b8wb_fixed: 2557 case ARM::VST2b16wb_fixed: 2558 case ARM::VST2b32wb_fixed: 2559 case ARM::VST2b8wb_register: 2560 case ARM::VST2b16wb_register: 2561 case ARM::VST2b32wb_register: 2562 if (Rm == 0xF) 2563 return MCDisassembler::Fail; 2564 Inst.addOperand(MCOperand::CreateImm(0)); 2565 break; 2566 case ARM::VST3d8_UPD: 2567 case ARM::VST3d16_UPD: 2568 case ARM::VST3d32_UPD: 2569 case ARM::VST3q8_UPD: 2570 case ARM::VST3q16_UPD: 2571 case ARM::VST3q32_UPD: 2572 case ARM::VST4d8_UPD: 2573 case ARM::VST4d16_UPD: 2574 case ARM::VST4d32_UPD: 2575 case ARM::VST4q8_UPD: 2576 case ARM::VST4q16_UPD: 2577 case ARM::VST4q32_UPD: 2578 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2579 return MCDisassembler::Fail; 2580 break; 2581 default: 2582 break; 2583 } 2584 2585 // AddrMode6 Base (register+alignment) 2586 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2587 return MCDisassembler::Fail; 2588 2589 // AddrMode6 Offset (register) 2590 switch (Inst.getOpcode()) { 2591 default: 2592 if (Rm == 0xD) 2593 Inst.addOperand(MCOperand::CreateReg(0)); 2594 else if (Rm != 0xF) { 2595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2596 return MCDisassembler::Fail; 2597 } 2598 break; 2599 case ARM::VST1d8wb_fixed: 2600 case ARM::VST1d16wb_fixed: 2601 case ARM::VST1d32wb_fixed: 2602 case ARM::VST1d64wb_fixed: 2603 case ARM::VST1q8wb_fixed: 2604 case ARM::VST1q16wb_fixed: 2605 case ARM::VST1q32wb_fixed: 2606 case ARM::VST1q64wb_fixed: 2607 case ARM::VST1d8Twb_fixed: 2608 case ARM::VST1d16Twb_fixed: 2609 case ARM::VST1d32Twb_fixed: 2610 case ARM::VST1d64Twb_fixed: 2611 case ARM::VST1d8Qwb_fixed: 2612 case ARM::VST1d16Qwb_fixed: 2613 case ARM::VST1d32Qwb_fixed: 2614 case ARM::VST1d64Qwb_fixed: 2615 case ARM::VST2d8wb_fixed: 2616 case ARM::VST2d16wb_fixed: 2617 case ARM::VST2d32wb_fixed: 2618 case ARM::VST2q8wb_fixed: 2619 case ARM::VST2q16wb_fixed: 2620 case ARM::VST2q32wb_fixed: 2621 case ARM::VST2b8wb_fixed: 2622 case ARM::VST2b16wb_fixed: 2623 case ARM::VST2b32wb_fixed: 2624 break; 2625 } 2626 2627 2628 // First input register 2629 switch (Inst.getOpcode()) { 2630 case ARM::VST1q16: 2631 case ARM::VST1q32: 2632 case ARM::VST1q64: 2633 case ARM::VST1q8: 2634 case ARM::VST1q16wb_fixed: 2635 case ARM::VST1q16wb_register: 2636 case ARM::VST1q32wb_fixed: 2637 case ARM::VST1q32wb_register: 2638 case ARM::VST1q64wb_fixed: 2639 case ARM::VST1q64wb_register: 2640 case ARM::VST1q8wb_fixed: 2641 case ARM::VST1q8wb_register: 2642 case ARM::VST2d16: 2643 case ARM::VST2d32: 2644 case ARM::VST2d8: 2645 case ARM::VST2d16wb_fixed: 2646 case ARM::VST2d16wb_register: 2647 case ARM::VST2d32wb_fixed: 2648 case ARM::VST2d32wb_register: 2649 case ARM::VST2d8wb_fixed: 2650 case ARM::VST2d8wb_register: 2651 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2652 return MCDisassembler::Fail; 2653 break; 2654 case ARM::VST2b16: 2655 case ARM::VST2b32: 2656 case ARM::VST2b8: 2657 case ARM::VST2b16wb_fixed: 2658 case ARM::VST2b16wb_register: 2659 case ARM::VST2b32wb_fixed: 2660 case ARM::VST2b32wb_register: 2661 case ARM::VST2b8wb_fixed: 2662 case ARM::VST2b8wb_register: 2663 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2664 return MCDisassembler::Fail; 2665 break; 2666 default: 2667 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2668 return MCDisassembler::Fail; 2669 } 2670 2671 // Second input register 2672 switch (Inst.getOpcode()) { 2673 case ARM::VST3d8: 2674 case ARM::VST3d16: 2675 case ARM::VST3d32: 2676 case ARM::VST3d8_UPD: 2677 case ARM::VST3d16_UPD: 2678 case ARM::VST3d32_UPD: 2679 case ARM::VST4d8: 2680 case ARM::VST4d16: 2681 case ARM::VST4d32: 2682 case ARM::VST4d8_UPD: 2683 case ARM::VST4d16_UPD: 2684 case ARM::VST4d32_UPD: 2685 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2686 return MCDisassembler::Fail; 2687 break; 2688 case ARM::VST3q8: 2689 case ARM::VST3q16: 2690 case ARM::VST3q32: 2691 case ARM::VST3q8_UPD: 2692 case ARM::VST3q16_UPD: 2693 case ARM::VST3q32_UPD: 2694 case ARM::VST4q8: 2695 case ARM::VST4q16: 2696 case ARM::VST4q32: 2697 case ARM::VST4q8_UPD: 2698 case ARM::VST4q16_UPD: 2699 case ARM::VST4q32_UPD: 2700 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2701 return MCDisassembler::Fail; 2702 break; 2703 default: 2704 break; 2705 } 2706 2707 // Third input register 2708 switch (Inst.getOpcode()) { 2709 case ARM::VST3d8: 2710 case ARM::VST3d16: 2711 case ARM::VST3d32: 2712 case ARM::VST3d8_UPD: 2713 case ARM::VST3d16_UPD: 2714 case ARM::VST3d32_UPD: 2715 case ARM::VST4d8: 2716 case ARM::VST4d16: 2717 case ARM::VST4d32: 2718 case ARM::VST4d8_UPD: 2719 case ARM::VST4d16_UPD: 2720 case ARM::VST4d32_UPD: 2721 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 break; 2724 case ARM::VST3q8: 2725 case ARM::VST3q16: 2726 case ARM::VST3q32: 2727 case ARM::VST3q8_UPD: 2728 case ARM::VST3q16_UPD: 2729 case ARM::VST3q32_UPD: 2730 case ARM::VST4q8: 2731 case ARM::VST4q16: 2732 case ARM::VST4q32: 2733 case ARM::VST4q8_UPD: 2734 case ARM::VST4q16_UPD: 2735 case ARM::VST4q32_UPD: 2736 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2737 return MCDisassembler::Fail; 2738 break; 2739 default: 2740 break; 2741 } 2742 2743 // Fourth input register 2744 switch (Inst.getOpcode()) { 2745 case ARM::VST4d8: 2746 case ARM::VST4d16: 2747 case ARM::VST4d32: 2748 case ARM::VST4d8_UPD: 2749 case ARM::VST4d16_UPD: 2750 case ARM::VST4d32_UPD: 2751 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2752 return MCDisassembler::Fail; 2753 break; 2754 case ARM::VST4q8: 2755 case ARM::VST4q16: 2756 case ARM::VST4q32: 2757 case ARM::VST4q8_UPD: 2758 case ARM::VST4q16_UPD: 2759 case ARM::VST4q32_UPD: 2760 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2761 return MCDisassembler::Fail; 2762 break; 2763 default: 2764 break; 2765 } 2766 2767 return S; 2768} 2769 2770static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2771 uint64_t Address, const void *Decoder) { 2772 DecodeStatus S = MCDisassembler::Success; 2773 2774 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2775 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2776 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2777 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2778 unsigned align = fieldFromInstruction(Insn, 4, 1); 2779 unsigned size = fieldFromInstruction(Insn, 6, 2); 2780 2781 if (size == 0 && align == 1) 2782 return MCDisassembler::Fail; 2783 align *= (1 << size); 2784 2785 switch (Inst.getOpcode()) { 2786 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2787 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2788 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2789 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2790 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2791 return MCDisassembler::Fail; 2792 break; 2793 default: 2794 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2795 return MCDisassembler::Fail; 2796 break; 2797 } 2798 if (Rm != 0xF) { 2799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2800 return MCDisassembler::Fail; 2801 } 2802 2803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2804 return MCDisassembler::Fail; 2805 Inst.addOperand(MCOperand::CreateImm(align)); 2806 2807 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2808 // variant encodes Rm == 0xf. Anything else is a register offset post- 2809 // increment and we need to add the register operand to the instruction. 2810 if (Rm != 0xD && Rm != 0xF && 2811 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2812 return MCDisassembler::Fail; 2813 2814 return S; 2815} 2816 2817static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2818 uint64_t Address, const void *Decoder) { 2819 DecodeStatus S = MCDisassembler::Success; 2820 2821 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2822 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2823 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2824 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2825 unsigned align = fieldFromInstruction(Insn, 4, 1); 2826 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2827 align *= 2*size; 2828 2829 switch (Inst.getOpcode()) { 2830 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2831 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2832 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2833 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2834 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2835 return MCDisassembler::Fail; 2836 break; 2837 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2838 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2839 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2840 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2841 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2842 return MCDisassembler::Fail; 2843 break; 2844 default: 2845 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2846 return MCDisassembler::Fail; 2847 break; 2848 } 2849 2850 if (Rm != 0xF) 2851 Inst.addOperand(MCOperand::CreateImm(0)); 2852 2853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2854 return MCDisassembler::Fail; 2855 Inst.addOperand(MCOperand::CreateImm(align)); 2856 2857 if (Rm != 0xD && Rm != 0xF) { 2858 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2859 return MCDisassembler::Fail; 2860 } 2861 2862 return S; 2863} 2864 2865static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2866 uint64_t Address, const void *Decoder) { 2867 DecodeStatus S = MCDisassembler::Success; 2868 2869 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2870 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2871 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2872 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2873 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2874 2875 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2876 return MCDisassembler::Fail; 2877 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2878 return MCDisassembler::Fail; 2879 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2880 return MCDisassembler::Fail; 2881 if (Rm != 0xF) { 2882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2883 return MCDisassembler::Fail; 2884 } 2885 2886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2887 return MCDisassembler::Fail; 2888 Inst.addOperand(MCOperand::CreateImm(0)); 2889 2890 if (Rm == 0xD) 2891 Inst.addOperand(MCOperand::CreateReg(0)); 2892 else if (Rm != 0xF) { 2893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2894 return MCDisassembler::Fail; 2895 } 2896 2897 return S; 2898} 2899 2900static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2901 uint64_t Address, const void *Decoder) { 2902 DecodeStatus S = MCDisassembler::Success; 2903 2904 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2905 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2906 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2907 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2908 unsigned size = fieldFromInstruction(Insn, 6, 2); 2909 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2910 unsigned align = fieldFromInstruction(Insn, 4, 1); 2911 2912 if (size == 0x3) { 2913 if (align == 0) 2914 return MCDisassembler::Fail; 2915 size = 4; 2916 align = 16; 2917 } else { 2918 if (size == 2) { 2919 size = 1 << size; 2920 align *= 8; 2921 } else { 2922 size = 1 << size; 2923 align *= 4*size; 2924 } 2925 } 2926 2927 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2928 return MCDisassembler::Fail; 2929 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2930 return MCDisassembler::Fail; 2931 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2932 return MCDisassembler::Fail; 2933 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2934 return MCDisassembler::Fail; 2935 if (Rm != 0xF) { 2936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2937 return MCDisassembler::Fail; 2938 } 2939 2940 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2941 return MCDisassembler::Fail; 2942 Inst.addOperand(MCOperand::CreateImm(align)); 2943 2944 if (Rm == 0xD) 2945 Inst.addOperand(MCOperand::CreateReg(0)); 2946 else if (Rm != 0xF) { 2947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2948 return MCDisassembler::Fail; 2949 } 2950 2951 return S; 2952} 2953 2954static DecodeStatus 2955DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2956 uint64_t Address, const void *Decoder) { 2957 DecodeStatus S = MCDisassembler::Success; 2958 2959 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2960 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2961 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2962 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2963 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2964 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2965 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2966 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2967 2968 if (Q) { 2969 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2970 return MCDisassembler::Fail; 2971 } else { 2972 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2973 return MCDisassembler::Fail; 2974 } 2975 2976 Inst.addOperand(MCOperand::CreateImm(imm)); 2977 2978 switch (Inst.getOpcode()) { 2979 case ARM::VORRiv4i16: 2980 case ARM::VORRiv2i32: 2981 case ARM::VBICiv4i16: 2982 case ARM::VBICiv2i32: 2983 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 break; 2986 case ARM::VORRiv8i16: 2987 case ARM::VORRiv4i32: 2988 case ARM::VBICiv8i16: 2989 case ARM::VBICiv4i32: 2990 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2991 return MCDisassembler::Fail; 2992 break; 2993 default: 2994 break; 2995 } 2996 2997 return S; 2998} 2999 3000static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3001 uint64_t Address, const void *Decoder) { 3002 DecodeStatus S = MCDisassembler::Success; 3003 3004 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3005 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3006 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3007 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3008 unsigned size = fieldFromInstruction(Insn, 18, 2); 3009 3010 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3011 return MCDisassembler::Fail; 3012 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3013 return MCDisassembler::Fail; 3014 Inst.addOperand(MCOperand::CreateImm(8 << size)); 3015 3016 return S; 3017} 3018 3019static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3020 uint64_t Address, const void *Decoder) { 3021 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 3022 return MCDisassembler::Success; 3023} 3024 3025static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3026 uint64_t Address, const void *Decoder) { 3027 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3028 return MCDisassembler::Success; 3029} 3030 3031static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3032 uint64_t Address, const void *Decoder) { 3033 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3034 return MCDisassembler::Success; 3035} 3036 3037static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3038 uint64_t Address, const void *Decoder) { 3039 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3040 return MCDisassembler::Success; 3041} 3042 3043static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3044 uint64_t Address, const void *Decoder) { 3045 DecodeStatus S = MCDisassembler::Success; 3046 3047 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3048 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3049 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3050 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3051 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3052 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3053 unsigned op = fieldFromInstruction(Insn, 6, 1); 3054 3055 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3056 return MCDisassembler::Fail; 3057 if (op) { 3058 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3059 return MCDisassembler::Fail; // Writeback 3060 } 3061 3062 switch (Inst.getOpcode()) { 3063 case ARM::VTBL2: 3064 case ARM::VTBX2: 3065 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3066 return MCDisassembler::Fail; 3067 break; 3068 default: 3069 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3070 return MCDisassembler::Fail; 3071 } 3072 3073 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3074 return MCDisassembler::Fail; 3075 3076 return S; 3077} 3078 3079static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3080 uint64_t Address, const void *Decoder) { 3081 DecodeStatus S = MCDisassembler::Success; 3082 3083 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3084 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3085 3086 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3087 return MCDisassembler::Fail; 3088 3089 switch(Inst.getOpcode()) { 3090 default: 3091 return MCDisassembler::Fail; 3092 case ARM::tADR: 3093 break; // tADR does not explicitly represent the PC as an operand. 3094 case ARM::tADDrSPi: 3095 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3096 break; 3097 } 3098 3099 Inst.addOperand(MCOperand::CreateImm(imm)); 3100 return S; 3101} 3102 3103static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3104 uint64_t Address, const void *Decoder) { 3105 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3106 true, 2, Inst, Decoder)) 3107 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3108 return MCDisassembler::Success; 3109} 3110 3111static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3112 uint64_t Address, const void *Decoder) { 3113 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3114 true, 4, Inst, Decoder)) 3115 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3116 return MCDisassembler::Success; 3117} 3118 3119static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3120 uint64_t Address, const void *Decoder) { 3121 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3122 true, 2, Inst, Decoder)) 3123 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3124 return MCDisassembler::Success; 3125} 3126 3127static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3128 uint64_t Address, const void *Decoder) { 3129 DecodeStatus S = MCDisassembler::Success; 3130 3131 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3132 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3133 3134 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3135 return MCDisassembler::Fail; 3136 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3137 return MCDisassembler::Fail; 3138 3139 return S; 3140} 3141 3142static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3143 uint64_t Address, const void *Decoder) { 3144 DecodeStatus S = MCDisassembler::Success; 3145 3146 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3147 unsigned imm = fieldFromInstruction(Val, 3, 5); 3148 3149 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3150 return MCDisassembler::Fail; 3151 Inst.addOperand(MCOperand::CreateImm(imm)); 3152 3153 return S; 3154} 3155 3156static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3157 uint64_t Address, const void *Decoder) { 3158 unsigned imm = Val << 2; 3159 3160 Inst.addOperand(MCOperand::CreateImm(imm)); 3161 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3162 3163 return MCDisassembler::Success; 3164} 3165 3166static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3167 uint64_t Address, const void *Decoder) { 3168 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3169 Inst.addOperand(MCOperand::CreateImm(Val)); 3170 3171 return MCDisassembler::Success; 3172} 3173 3174static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3175 uint64_t Address, const void *Decoder) { 3176 DecodeStatus S = MCDisassembler::Success; 3177 3178 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3179 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3180 unsigned imm = fieldFromInstruction(Val, 0, 2); 3181 3182 // Thumb stores cannot use PC as dest register. 3183 switch (Inst.getOpcode()) { 3184 case ARM::t2STRHs: 3185 case ARM::t2STRBs: 3186 case ARM::t2STRs: 3187 if (Rn == 15) 3188 return MCDisassembler::Fail; 3189 default: 3190 break; 3191 } 3192 3193 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3194 return MCDisassembler::Fail; 3195 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3196 return MCDisassembler::Fail; 3197 Inst.addOperand(MCOperand::CreateImm(imm)); 3198 3199 return S; 3200} 3201 3202static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3203 uint64_t Address, const void *Decoder) { 3204 DecodeStatus S = MCDisassembler::Success; 3205 3206 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3207 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3208 3209 if (Rn == 15) { 3210 switch (Inst.getOpcode()) { 3211 case ARM::t2LDRBs: 3212 Inst.setOpcode(ARM::t2LDRBpci); 3213 break; 3214 case ARM::t2LDRHs: 3215 Inst.setOpcode(ARM::t2LDRHpci); 3216 break; 3217 case ARM::t2LDRSHs: 3218 Inst.setOpcode(ARM::t2LDRSHpci); 3219 break; 3220 case ARM::t2LDRSBs: 3221 Inst.setOpcode(ARM::t2LDRSBpci); 3222 break; 3223 case ARM::t2LDRs: 3224 Inst.setOpcode(ARM::t2LDRpci); 3225 break; 3226 case ARM::t2PLDs: 3227 Inst.setOpcode(ARM::t2PLDpci); 3228 break; 3229 case ARM::t2PLIs: 3230 Inst.setOpcode(ARM::t2PLIpci); 3231 break; 3232 default: 3233 return MCDisassembler::Fail; 3234 } 3235 3236 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3237 } 3238 3239 if (Rt == 15) { 3240 switch (Inst.getOpcode()) { 3241 case ARM::t2LDRSHs: 3242 return MCDisassembler::Fail; 3243 case ARM::t2LDRHs: 3244 // FIXME: this instruction is only available with MP extensions, 3245 // this should be checked first but we don't have access to the 3246 // feature bits here. 3247 Inst.setOpcode(ARM::t2PLDWs); 3248 break; 3249 default: 3250 break; 3251 } 3252 } 3253 3254 switch (Inst.getOpcode()) { 3255 case ARM::t2PLDs: 3256 case ARM::t2PLDWs: 3257 case ARM::t2PLIs: 3258 break; 3259 default: 3260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3261 return MCDisassembler::Fail; 3262 } 3263 3264 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3265 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3266 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3267 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3268 return MCDisassembler::Fail; 3269 3270 return S; 3271} 3272 3273static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3274 uint64_t Address, const void* Decoder) { 3275 DecodeStatus S = MCDisassembler::Success; 3276 3277 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3278 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3279 unsigned U = fieldFromInstruction(Insn, 9, 1); 3280 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3281 imm |= (U << 8); 3282 imm |= (Rn << 9); 3283 3284 if (Rn == 15) { 3285 switch (Inst.getOpcode()) { 3286 case ARM::t2LDRi8: 3287 Inst.setOpcode(ARM::t2LDRpci); 3288 break; 3289 case ARM::t2LDRBi8: 3290 Inst.setOpcode(ARM::t2LDRBpci); 3291 break; 3292 case ARM::t2LDRSBi8: 3293 Inst.setOpcode(ARM::t2LDRSBpci); 3294 break; 3295 case ARM::t2LDRHi8: 3296 Inst.setOpcode(ARM::t2LDRHpci); 3297 break; 3298 case ARM::t2LDRSHi8: 3299 Inst.setOpcode(ARM::t2LDRSHpci); 3300 break; 3301 case ARM::t2PLDi8: 3302 Inst.setOpcode(ARM::t2PLDpci); 3303 break; 3304 case ARM::t2PLIi8: 3305 Inst.setOpcode(ARM::t2PLIpci); 3306 break; 3307 default: 3308 return MCDisassembler::Fail; 3309 } 3310 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3311 } 3312 3313 if (Rt == 15) { 3314 switch (Inst.getOpcode()) { 3315 case ARM::t2LDRSHi8: 3316 return MCDisassembler::Fail; 3317 default: 3318 break; 3319 } 3320 } 3321 3322 switch (Inst.getOpcode()) { 3323 case ARM::t2PLDi8: 3324 case ARM::t2PLIi8: 3325 break; 3326 default: 3327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3328 return MCDisassembler::Fail; 3329 } 3330 3331 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3332 return MCDisassembler::Fail; 3333 return S; 3334} 3335 3336static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3337 uint64_t Address, const void* Decoder) { 3338 DecodeStatus S = MCDisassembler::Success; 3339 3340 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3341 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3342 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3343 imm |= (Rn << 13); 3344 3345 if (Rn == 15) { 3346 switch (Inst.getOpcode()) { 3347 case ARM::t2LDRi12: 3348 Inst.setOpcode(ARM::t2LDRpci); 3349 break; 3350 case ARM::t2LDRHi12: 3351 Inst.setOpcode(ARM::t2LDRHpci); 3352 break; 3353 case ARM::t2LDRSHi12: 3354 Inst.setOpcode(ARM::t2LDRSHpci); 3355 break; 3356 case ARM::t2LDRBi12: 3357 Inst.setOpcode(ARM::t2LDRBpci); 3358 break; 3359 case ARM::t2LDRSBi12: 3360 Inst.setOpcode(ARM::t2LDRSBpci); 3361 break; 3362 case ARM::t2PLDi12: 3363 Inst.setOpcode(ARM::t2PLDpci); 3364 break; 3365 case ARM::t2PLIi12: 3366 Inst.setOpcode(ARM::t2PLIpci); 3367 break; 3368 default: 3369 return MCDisassembler::Fail; 3370 } 3371 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3372 } 3373 3374 if (Rt == 15) { 3375 switch (Inst.getOpcode()) { 3376 case ARM::t2LDRSHi12: 3377 return MCDisassembler::Fail; 3378 case ARM::t2LDRHi12: 3379 Inst.setOpcode(ARM::t2PLDi12); 3380 break; 3381 default: 3382 break; 3383 } 3384 } 3385 3386 switch (Inst.getOpcode()) { 3387 case ARM::t2PLDi12: 3388 case ARM::t2PLIi12: 3389 break; 3390 default: 3391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3392 return MCDisassembler::Fail; 3393 } 3394 3395 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3396 return MCDisassembler::Fail; 3397 return S; 3398} 3399 3400static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3401 uint64_t Address, const void* Decoder) { 3402 DecodeStatus S = MCDisassembler::Success; 3403 3404 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3405 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3406 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3407 imm |= (Rn << 9); 3408 3409 if (Rn == 15) { 3410 switch (Inst.getOpcode()) { 3411 case ARM::t2LDRT: 3412 Inst.setOpcode(ARM::t2LDRpci); 3413 break; 3414 case ARM::t2LDRBT: 3415 Inst.setOpcode(ARM::t2LDRBpci); 3416 break; 3417 case ARM::t2LDRHT: 3418 Inst.setOpcode(ARM::t2LDRHpci); 3419 break; 3420 case ARM::t2LDRSBT: 3421 Inst.setOpcode(ARM::t2LDRSBpci); 3422 break; 3423 case ARM::t2LDRSHT: 3424 Inst.setOpcode(ARM::t2LDRSHpci); 3425 break; 3426 default: 3427 return MCDisassembler::Fail; 3428 } 3429 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3430 } 3431 3432 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3433 return MCDisassembler::Fail; 3434 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3435 return MCDisassembler::Fail; 3436 return S; 3437} 3438 3439static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3440 uint64_t Address, const void* Decoder) { 3441 DecodeStatus S = MCDisassembler::Success; 3442 3443 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3444 unsigned U = fieldFromInstruction(Insn, 23, 1); 3445 int imm = fieldFromInstruction(Insn, 0, 12); 3446 3447 if (Rt == 15) { 3448 switch (Inst.getOpcode()) { 3449 case ARM::t2LDRBpci: 3450 case ARM::t2LDRHpci: 3451 Inst.setOpcode(ARM::t2PLDpci); 3452 break; 3453 case ARM::t2LDRSBpci: 3454 Inst.setOpcode(ARM::t2PLIpci); 3455 break; 3456 case ARM::t2LDRSHpci: 3457 return MCDisassembler::Fail; 3458 default: 3459 break; 3460 } 3461 } 3462 3463 switch(Inst.getOpcode()) { 3464 case ARM::t2PLDpci: 3465 case ARM::t2PLIpci: 3466 break; 3467 default: 3468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3469 return MCDisassembler::Fail; 3470 } 3471 3472 if (!U) { 3473 // Special case for #-0. 3474 if (imm == 0) 3475 imm = INT32_MIN; 3476 else 3477 imm = -imm; 3478 } 3479 Inst.addOperand(MCOperand::CreateImm(imm)); 3480 3481 return S; 3482} 3483 3484static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3485 uint64_t Address, const void *Decoder) { 3486 if (Val == 0) 3487 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3488 else { 3489 int imm = Val & 0xFF; 3490 3491 if (!(Val & 0x100)) imm *= -1; 3492 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3493 } 3494 3495 return MCDisassembler::Success; 3496} 3497 3498static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3499 uint64_t Address, const void *Decoder) { 3500 DecodeStatus S = MCDisassembler::Success; 3501 3502 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3503 unsigned imm = fieldFromInstruction(Val, 0, 9); 3504 3505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3506 return MCDisassembler::Fail; 3507 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3508 return MCDisassembler::Fail; 3509 3510 return S; 3511} 3512 3513static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3514 uint64_t Address, const void *Decoder) { 3515 DecodeStatus S = MCDisassembler::Success; 3516 3517 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3518 unsigned imm = fieldFromInstruction(Val, 0, 8); 3519 3520 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3521 return MCDisassembler::Fail; 3522 3523 Inst.addOperand(MCOperand::CreateImm(imm)); 3524 3525 return S; 3526} 3527 3528static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3529 uint64_t Address, const void *Decoder) { 3530 int imm = Val & 0xFF; 3531 if (Val == 0) 3532 imm = INT32_MIN; 3533 else if (!(Val & 0x100)) 3534 imm *= -1; 3535 Inst.addOperand(MCOperand::CreateImm(imm)); 3536 3537 return MCDisassembler::Success; 3538} 3539 3540 3541static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3542 uint64_t Address, const void *Decoder) { 3543 DecodeStatus S = MCDisassembler::Success; 3544 3545 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3546 unsigned imm = fieldFromInstruction(Val, 0, 9); 3547 3548 // Thumb stores cannot use PC as dest register. 3549 switch (Inst.getOpcode()) { 3550 case ARM::t2STRT: 3551 case ARM::t2STRBT: 3552 case ARM::t2STRHT: 3553 case ARM::t2STRi8: 3554 case ARM::t2STRHi8: 3555 case ARM::t2STRBi8: 3556 if (Rn == 15) 3557 return MCDisassembler::Fail; 3558 break; 3559 default: 3560 break; 3561 } 3562 3563 // Some instructions always use an additive offset. 3564 switch (Inst.getOpcode()) { 3565 case ARM::t2LDRT: 3566 case ARM::t2LDRBT: 3567 case ARM::t2LDRHT: 3568 case ARM::t2LDRSBT: 3569 case ARM::t2LDRSHT: 3570 case ARM::t2STRT: 3571 case ARM::t2STRBT: 3572 case ARM::t2STRHT: 3573 imm |= 0x100; 3574 break; 3575 default: 3576 break; 3577 } 3578 3579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3580 return MCDisassembler::Fail; 3581 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3582 return MCDisassembler::Fail; 3583 3584 return S; 3585} 3586 3587static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3588 uint64_t Address, const void *Decoder) { 3589 DecodeStatus S = MCDisassembler::Success; 3590 3591 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3592 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3593 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3594 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3595 addr |= Rn << 9; 3596 unsigned load = fieldFromInstruction(Insn, 20, 1); 3597 3598 if (Rn == 15) { 3599 switch (Inst.getOpcode()) { 3600 case ARM::t2LDR_PRE: 3601 case ARM::t2LDR_POST: 3602 Inst.setOpcode(ARM::t2LDRpci); 3603 break; 3604 case ARM::t2LDRB_PRE: 3605 case ARM::t2LDRB_POST: 3606 Inst.setOpcode(ARM::t2LDRBpci); 3607 break; 3608 case ARM::t2LDRH_PRE: 3609 case ARM::t2LDRH_POST: 3610 Inst.setOpcode(ARM::t2LDRHpci); 3611 break; 3612 case ARM::t2LDRSB_PRE: 3613 case ARM::t2LDRSB_POST: 3614 if (Rt == 15) 3615 Inst.setOpcode(ARM::t2PLIpci); 3616 else 3617 Inst.setOpcode(ARM::t2LDRSBpci); 3618 break; 3619 case ARM::t2LDRSH_PRE: 3620 case ARM::t2LDRSH_POST: 3621 Inst.setOpcode(ARM::t2LDRSHpci); 3622 break; 3623 default: 3624 return MCDisassembler::Fail; 3625 } 3626 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3627 } 3628 3629 if (!load) { 3630 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3631 return MCDisassembler::Fail; 3632 } 3633 3634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 3637 if (load) { 3638 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3639 return MCDisassembler::Fail; 3640 } 3641 3642 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 3645 return S; 3646} 3647 3648static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3649 uint64_t Address, const void *Decoder) { 3650 DecodeStatus S = MCDisassembler::Success; 3651 3652 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3653 unsigned imm = fieldFromInstruction(Val, 0, 12); 3654 3655 // Thumb stores cannot use PC as dest register. 3656 switch (Inst.getOpcode()) { 3657 case ARM::t2STRi12: 3658 case ARM::t2STRBi12: 3659 case ARM::t2STRHi12: 3660 if (Rn == 15) 3661 return MCDisassembler::Fail; 3662 default: 3663 break; 3664 } 3665 3666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3667 return MCDisassembler::Fail; 3668 Inst.addOperand(MCOperand::CreateImm(imm)); 3669 3670 return S; 3671} 3672 3673 3674static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3675 uint64_t Address, const void *Decoder) { 3676 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3677 3678 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3679 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3680 Inst.addOperand(MCOperand::CreateImm(imm)); 3681 3682 return MCDisassembler::Success; 3683} 3684 3685static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3686 uint64_t Address, const void *Decoder) { 3687 DecodeStatus S = MCDisassembler::Success; 3688 3689 if (Inst.getOpcode() == ARM::tADDrSP) { 3690 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3691 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3692 3693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3694 return MCDisassembler::Fail; 3695 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3697 return MCDisassembler::Fail; 3698 } else if (Inst.getOpcode() == ARM::tADDspr) { 3699 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3700 3701 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3702 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3703 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3704 return MCDisassembler::Fail; 3705 } 3706 3707 return S; 3708} 3709 3710static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3711 uint64_t Address, const void *Decoder) { 3712 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3713 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3714 3715 Inst.addOperand(MCOperand::CreateImm(imod)); 3716 Inst.addOperand(MCOperand::CreateImm(flags)); 3717 3718 return MCDisassembler::Success; 3719} 3720 3721static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3722 uint64_t Address, const void *Decoder) { 3723 DecodeStatus S = MCDisassembler::Success; 3724 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3725 unsigned add = fieldFromInstruction(Insn, 4, 1); 3726 3727 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3728 return MCDisassembler::Fail; 3729 Inst.addOperand(MCOperand::CreateImm(add)); 3730 3731 return S; 3732} 3733 3734static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3735 uint64_t Address, const void *Decoder) { 3736 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3737 // Note only one trailing zero not two. Also the J1 and J2 values are from 3738 // the encoded instruction. So here change to I1 and I2 values via: 3739 // I1 = NOT(J1 EOR S); 3740 // I2 = NOT(J2 EOR S); 3741 // and build the imm32 with two trailing zeros as documented: 3742 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3743 unsigned S = (Val >> 23) & 1; 3744 unsigned J1 = (Val >> 22) & 1; 3745 unsigned J2 = (Val >> 21) & 1; 3746 unsigned I1 = !(J1 ^ S); 3747 unsigned I2 = !(J2 ^ S); 3748 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3749 int imm32 = SignExtend32<25>(tmp << 1); 3750 3751 if (!tryAddingSymbolicOperand(Address, 3752 (Address & ~2u) + imm32 + 4, 3753 true, 4, Inst, Decoder)) 3754 Inst.addOperand(MCOperand::CreateImm(imm32)); 3755 return MCDisassembler::Success; 3756} 3757 3758static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3759 uint64_t Address, const void *Decoder) { 3760 if (Val == 0xA || Val == 0xB) 3761 return MCDisassembler::Fail; 3762 3763 Inst.addOperand(MCOperand::CreateImm(Val)); 3764 return MCDisassembler::Success; 3765} 3766 3767static DecodeStatus 3768DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3769 uint64_t Address, const void *Decoder) { 3770 DecodeStatus S = MCDisassembler::Success; 3771 3772 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3773 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3774 3775 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3777 return MCDisassembler::Fail; 3778 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3779 return MCDisassembler::Fail; 3780 return S; 3781} 3782 3783static DecodeStatus 3784DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3785 uint64_t Address, const void *Decoder) { 3786 DecodeStatus S = MCDisassembler::Success; 3787 3788 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3789 if (pred == 0xE || pred == 0xF) { 3790 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3791 switch (opc) { 3792 default: 3793 return MCDisassembler::Fail; 3794 case 0xf3bf8f4: 3795 Inst.setOpcode(ARM::t2DSB); 3796 break; 3797 case 0xf3bf8f5: 3798 Inst.setOpcode(ARM::t2DMB); 3799 break; 3800 case 0xf3bf8f6: 3801 Inst.setOpcode(ARM::t2ISB); 3802 break; 3803 } 3804 3805 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3806 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3807 } 3808 3809 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3810 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3811 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3812 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3813 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3814 3815 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3816 return MCDisassembler::Fail; 3817 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3818 return MCDisassembler::Fail; 3819 3820 return S; 3821} 3822 3823// Decode a shifted immediate operand. These basically consist 3824// of an 8-bit value, and a 4-bit directive that specifies either 3825// a splat operation or a rotation. 3826static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3827 uint64_t Address, const void *Decoder) { 3828 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3829 if (ctrl == 0) { 3830 unsigned byte = fieldFromInstruction(Val, 8, 2); 3831 unsigned imm = fieldFromInstruction(Val, 0, 8); 3832 switch (byte) { 3833 case 0: 3834 Inst.addOperand(MCOperand::CreateImm(imm)); 3835 break; 3836 case 1: 3837 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3838 break; 3839 case 2: 3840 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3841 break; 3842 case 3: 3843 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3844 (imm << 8) | imm)); 3845 break; 3846 } 3847 } else { 3848 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3849 unsigned rot = fieldFromInstruction(Val, 7, 5); 3850 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3851 Inst.addOperand(MCOperand::CreateImm(imm)); 3852 } 3853 3854 return MCDisassembler::Success; 3855} 3856 3857static DecodeStatus 3858DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3859 uint64_t Address, const void *Decoder){ 3860 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3861 true, 2, Inst, Decoder)) 3862 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3863 return MCDisassembler::Success; 3864} 3865 3866static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3867 uint64_t Address, const void *Decoder){ 3868 // Val is passed in as S:J1:J2:imm10:imm11 3869 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3870 // the encoded instruction. So here change to I1 and I2 values via: 3871 // I1 = NOT(J1 EOR S); 3872 // I2 = NOT(J2 EOR S); 3873 // and build the imm32 with one trailing zero as documented: 3874 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3875 unsigned S = (Val >> 23) & 1; 3876 unsigned J1 = (Val >> 22) & 1; 3877 unsigned J2 = (Val >> 21) & 1; 3878 unsigned I1 = !(J1 ^ S); 3879 unsigned I2 = !(J2 ^ S); 3880 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3881 int imm32 = SignExtend32<25>(tmp << 1); 3882 3883 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3884 true, 4, Inst, Decoder)) 3885 Inst.addOperand(MCOperand::CreateImm(imm32)); 3886 return MCDisassembler::Success; 3887} 3888 3889static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3890 uint64_t Address, const void *Decoder) { 3891 if (Val & ~0xf) 3892 return MCDisassembler::Fail; 3893 3894 Inst.addOperand(MCOperand::CreateImm(Val)); 3895 return MCDisassembler::Success; 3896} 3897 3898static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 3899 uint64_t Address, const void *Decoder) { 3900 if (Val & ~0xf) 3901 return MCDisassembler::Fail; 3902 3903 Inst.addOperand(MCOperand::CreateImm(Val)); 3904 return MCDisassembler::Success; 3905} 3906 3907static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3908 uint64_t Address, const void *Decoder) { 3909 if (!Val) return MCDisassembler::Fail; 3910 Inst.addOperand(MCOperand::CreateImm(Val)); 3911 return MCDisassembler::Success; 3912} 3913 3914static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3915 uint64_t Address, const void *Decoder) { 3916 DecodeStatus S = MCDisassembler::Success; 3917 3918 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3919 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3920 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3921 3922 if (Rn == 0xF) 3923 S = MCDisassembler::SoftFail; 3924 3925 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3926 return MCDisassembler::Fail; 3927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3928 return MCDisassembler::Fail; 3929 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3930 return MCDisassembler::Fail; 3931 3932 return S; 3933} 3934 3935static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3936 uint64_t Address, const void *Decoder){ 3937 DecodeStatus S = MCDisassembler::Success; 3938 3939 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3940 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3941 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3942 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3943 3944 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3945 return MCDisassembler::Fail; 3946 3947 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 3948 S = MCDisassembler::SoftFail; 3949 3950 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3951 return MCDisassembler::Fail; 3952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3953 return MCDisassembler::Fail; 3954 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3955 return MCDisassembler::Fail; 3956 3957 return S; 3958} 3959 3960static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3961 uint64_t Address, const void *Decoder) { 3962 DecodeStatus S = MCDisassembler::Success; 3963 3964 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3965 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3966 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3967 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3968 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3969 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3970 3971 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3972 3973 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3974 return MCDisassembler::Fail; 3975 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3976 return MCDisassembler::Fail; 3977 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3978 return MCDisassembler::Fail; 3979 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3980 return MCDisassembler::Fail; 3981 3982 return S; 3983} 3984 3985static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3986 uint64_t Address, const void *Decoder) { 3987 DecodeStatus S = MCDisassembler::Success; 3988 3989 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3990 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3991 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3992 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3993 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3994 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3995 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3996 3997 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3998 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3999 4000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4001 return MCDisassembler::Fail; 4002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4003 return MCDisassembler::Fail; 4004 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4005 return MCDisassembler::Fail; 4006 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4007 return MCDisassembler::Fail; 4008 4009 return S; 4010} 4011 4012 4013static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4014 uint64_t Address, const void *Decoder) { 4015 DecodeStatus S = MCDisassembler::Success; 4016 4017 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4018 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4019 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4020 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4021 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4022 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4023 4024 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4025 4026 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4031 return MCDisassembler::Fail; 4032 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4033 return MCDisassembler::Fail; 4034 4035 return S; 4036} 4037 4038static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4039 uint64_t Address, const void *Decoder) { 4040 DecodeStatus S = MCDisassembler::Success; 4041 4042 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4043 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4044 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4045 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4046 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4047 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4048 4049 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4050 4051 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4052 return MCDisassembler::Fail; 4053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4054 return MCDisassembler::Fail; 4055 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4056 return MCDisassembler::Fail; 4057 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4058 return MCDisassembler::Fail; 4059 4060 return S; 4061} 4062 4063static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4064 uint64_t Address, const void *Decoder) { 4065 DecodeStatus S = MCDisassembler::Success; 4066 4067 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4068 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4069 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4070 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4071 unsigned size = fieldFromInstruction(Insn, 10, 2); 4072 4073 unsigned align = 0; 4074 unsigned index = 0; 4075 switch (size) { 4076 default: 4077 return MCDisassembler::Fail; 4078 case 0: 4079 if (fieldFromInstruction(Insn, 4, 1)) 4080 return MCDisassembler::Fail; // UNDEFINED 4081 index = fieldFromInstruction(Insn, 5, 3); 4082 break; 4083 case 1: 4084 if (fieldFromInstruction(Insn, 5, 1)) 4085 return MCDisassembler::Fail; // UNDEFINED 4086 index = fieldFromInstruction(Insn, 6, 2); 4087 if (fieldFromInstruction(Insn, 4, 1)) 4088 align = 2; 4089 break; 4090 case 2: 4091 if (fieldFromInstruction(Insn, 6, 1)) 4092 return MCDisassembler::Fail; // UNDEFINED 4093 index = fieldFromInstruction(Insn, 7, 1); 4094 4095 switch (fieldFromInstruction(Insn, 4, 2)) { 4096 case 0 : 4097 align = 0; break; 4098 case 3: 4099 align = 4; break; 4100 default: 4101 return MCDisassembler::Fail; 4102 } 4103 break; 4104 } 4105 4106 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4107 return MCDisassembler::Fail; 4108 if (Rm != 0xF) { // Writeback 4109 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4110 return MCDisassembler::Fail; 4111 } 4112 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4113 return MCDisassembler::Fail; 4114 Inst.addOperand(MCOperand::CreateImm(align)); 4115 if (Rm != 0xF) { 4116 if (Rm != 0xD) { 4117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4118 return MCDisassembler::Fail; 4119 } else 4120 Inst.addOperand(MCOperand::CreateReg(0)); 4121 } 4122 4123 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4124 return MCDisassembler::Fail; 4125 Inst.addOperand(MCOperand::CreateImm(index)); 4126 4127 return S; 4128} 4129 4130static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4131 uint64_t Address, const void *Decoder) { 4132 DecodeStatus S = MCDisassembler::Success; 4133 4134 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4135 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4136 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4137 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4138 unsigned size = fieldFromInstruction(Insn, 10, 2); 4139 4140 unsigned align = 0; 4141 unsigned index = 0; 4142 switch (size) { 4143 default: 4144 return MCDisassembler::Fail; 4145 case 0: 4146 if (fieldFromInstruction(Insn, 4, 1)) 4147 return MCDisassembler::Fail; // UNDEFINED 4148 index = fieldFromInstruction(Insn, 5, 3); 4149 break; 4150 case 1: 4151 if (fieldFromInstruction(Insn, 5, 1)) 4152 return MCDisassembler::Fail; // UNDEFINED 4153 index = fieldFromInstruction(Insn, 6, 2); 4154 if (fieldFromInstruction(Insn, 4, 1)) 4155 align = 2; 4156 break; 4157 case 2: 4158 if (fieldFromInstruction(Insn, 6, 1)) 4159 return MCDisassembler::Fail; // UNDEFINED 4160 index = fieldFromInstruction(Insn, 7, 1); 4161 4162 switch (fieldFromInstruction(Insn, 4, 2)) { 4163 case 0: 4164 align = 0; break; 4165 case 3: 4166 align = 4; break; 4167 default: 4168 return MCDisassembler::Fail; 4169 } 4170 break; 4171 } 4172 4173 if (Rm != 0xF) { // Writeback 4174 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4175 return MCDisassembler::Fail; 4176 } 4177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4178 return MCDisassembler::Fail; 4179 Inst.addOperand(MCOperand::CreateImm(align)); 4180 if (Rm != 0xF) { 4181 if (Rm != 0xD) { 4182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4183 return MCDisassembler::Fail; 4184 } else 4185 Inst.addOperand(MCOperand::CreateReg(0)); 4186 } 4187 4188 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4189 return MCDisassembler::Fail; 4190 Inst.addOperand(MCOperand::CreateImm(index)); 4191 4192 return S; 4193} 4194 4195 4196static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4197 uint64_t Address, const void *Decoder) { 4198 DecodeStatus S = MCDisassembler::Success; 4199 4200 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4201 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4202 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4203 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4204 unsigned size = fieldFromInstruction(Insn, 10, 2); 4205 4206 unsigned align = 0; 4207 unsigned index = 0; 4208 unsigned inc = 1; 4209 switch (size) { 4210 default: 4211 return MCDisassembler::Fail; 4212 case 0: 4213 index = fieldFromInstruction(Insn, 5, 3); 4214 if (fieldFromInstruction(Insn, 4, 1)) 4215 align = 2; 4216 break; 4217 case 1: 4218 index = fieldFromInstruction(Insn, 6, 2); 4219 if (fieldFromInstruction(Insn, 4, 1)) 4220 align = 4; 4221 if (fieldFromInstruction(Insn, 5, 1)) 4222 inc = 2; 4223 break; 4224 case 2: 4225 if (fieldFromInstruction(Insn, 5, 1)) 4226 return MCDisassembler::Fail; // UNDEFINED 4227 index = fieldFromInstruction(Insn, 7, 1); 4228 if (fieldFromInstruction(Insn, 4, 1) != 0) 4229 align = 8; 4230 if (fieldFromInstruction(Insn, 6, 1)) 4231 inc = 2; 4232 break; 4233 } 4234 4235 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4236 return MCDisassembler::Fail; 4237 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4238 return MCDisassembler::Fail; 4239 if (Rm != 0xF) { // Writeback 4240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4241 return MCDisassembler::Fail; 4242 } 4243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4244 return MCDisassembler::Fail; 4245 Inst.addOperand(MCOperand::CreateImm(align)); 4246 if (Rm != 0xF) { 4247 if (Rm != 0xD) { 4248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4249 return MCDisassembler::Fail; 4250 } else 4251 Inst.addOperand(MCOperand::CreateReg(0)); 4252 } 4253 4254 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4255 return MCDisassembler::Fail; 4256 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4257 return MCDisassembler::Fail; 4258 Inst.addOperand(MCOperand::CreateImm(index)); 4259 4260 return S; 4261} 4262 4263static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4264 uint64_t Address, const void *Decoder) { 4265 DecodeStatus S = MCDisassembler::Success; 4266 4267 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4268 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4269 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4270 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4271 unsigned size = fieldFromInstruction(Insn, 10, 2); 4272 4273 unsigned align = 0; 4274 unsigned index = 0; 4275 unsigned inc = 1; 4276 switch (size) { 4277 default: 4278 return MCDisassembler::Fail; 4279 case 0: 4280 index = fieldFromInstruction(Insn, 5, 3); 4281 if (fieldFromInstruction(Insn, 4, 1)) 4282 align = 2; 4283 break; 4284 case 1: 4285 index = fieldFromInstruction(Insn, 6, 2); 4286 if (fieldFromInstruction(Insn, 4, 1)) 4287 align = 4; 4288 if (fieldFromInstruction(Insn, 5, 1)) 4289 inc = 2; 4290 break; 4291 case 2: 4292 if (fieldFromInstruction(Insn, 5, 1)) 4293 return MCDisassembler::Fail; // UNDEFINED 4294 index = fieldFromInstruction(Insn, 7, 1); 4295 if (fieldFromInstruction(Insn, 4, 1) != 0) 4296 align = 8; 4297 if (fieldFromInstruction(Insn, 6, 1)) 4298 inc = 2; 4299 break; 4300 } 4301 4302 if (Rm != 0xF) { // Writeback 4303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4304 return MCDisassembler::Fail; 4305 } 4306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4307 return MCDisassembler::Fail; 4308 Inst.addOperand(MCOperand::CreateImm(align)); 4309 if (Rm != 0xF) { 4310 if (Rm != 0xD) { 4311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4312 return MCDisassembler::Fail; 4313 } else 4314 Inst.addOperand(MCOperand::CreateReg(0)); 4315 } 4316 4317 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4318 return MCDisassembler::Fail; 4319 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4320 return MCDisassembler::Fail; 4321 Inst.addOperand(MCOperand::CreateImm(index)); 4322 4323 return S; 4324} 4325 4326 4327static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4328 uint64_t Address, const void *Decoder) { 4329 DecodeStatus S = MCDisassembler::Success; 4330 4331 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4332 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4333 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4334 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4335 unsigned size = fieldFromInstruction(Insn, 10, 2); 4336 4337 unsigned align = 0; 4338 unsigned index = 0; 4339 unsigned inc = 1; 4340 switch (size) { 4341 default: 4342 return MCDisassembler::Fail; 4343 case 0: 4344 if (fieldFromInstruction(Insn, 4, 1)) 4345 return MCDisassembler::Fail; // UNDEFINED 4346 index = fieldFromInstruction(Insn, 5, 3); 4347 break; 4348 case 1: 4349 if (fieldFromInstruction(Insn, 4, 1)) 4350 return MCDisassembler::Fail; // UNDEFINED 4351 index = fieldFromInstruction(Insn, 6, 2); 4352 if (fieldFromInstruction(Insn, 5, 1)) 4353 inc = 2; 4354 break; 4355 case 2: 4356 if (fieldFromInstruction(Insn, 4, 2)) 4357 return MCDisassembler::Fail; // UNDEFINED 4358 index = fieldFromInstruction(Insn, 7, 1); 4359 if (fieldFromInstruction(Insn, 6, 1)) 4360 inc = 2; 4361 break; 4362 } 4363 4364 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4365 return MCDisassembler::Fail; 4366 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4367 return MCDisassembler::Fail; 4368 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4369 return MCDisassembler::Fail; 4370 4371 if (Rm != 0xF) { // Writeback 4372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4373 return MCDisassembler::Fail; 4374 } 4375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4376 return MCDisassembler::Fail; 4377 Inst.addOperand(MCOperand::CreateImm(align)); 4378 if (Rm != 0xF) { 4379 if (Rm != 0xD) { 4380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4381 return MCDisassembler::Fail; 4382 } else 4383 Inst.addOperand(MCOperand::CreateReg(0)); 4384 } 4385 4386 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4387 return MCDisassembler::Fail; 4388 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4389 return MCDisassembler::Fail; 4390 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4391 return MCDisassembler::Fail; 4392 Inst.addOperand(MCOperand::CreateImm(index)); 4393 4394 return S; 4395} 4396 4397static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4398 uint64_t Address, const void *Decoder) { 4399 DecodeStatus S = MCDisassembler::Success; 4400 4401 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4402 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4403 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4404 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4405 unsigned size = fieldFromInstruction(Insn, 10, 2); 4406 4407 unsigned align = 0; 4408 unsigned index = 0; 4409 unsigned inc = 1; 4410 switch (size) { 4411 default: 4412 return MCDisassembler::Fail; 4413 case 0: 4414 if (fieldFromInstruction(Insn, 4, 1)) 4415 return MCDisassembler::Fail; // UNDEFINED 4416 index = fieldFromInstruction(Insn, 5, 3); 4417 break; 4418 case 1: 4419 if (fieldFromInstruction(Insn, 4, 1)) 4420 return MCDisassembler::Fail; // UNDEFINED 4421 index = fieldFromInstruction(Insn, 6, 2); 4422 if (fieldFromInstruction(Insn, 5, 1)) 4423 inc = 2; 4424 break; 4425 case 2: 4426 if (fieldFromInstruction(Insn, 4, 2)) 4427 return MCDisassembler::Fail; // UNDEFINED 4428 index = fieldFromInstruction(Insn, 7, 1); 4429 if (fieldFromInstruction(Insn, 6, 1)) 4430 inc = 2; 4431 break; 4432 } 4433 4434 if (Rm != 0xF) { // Writeback 4435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4436 return MCDisassembler::Fail; 4437 } 4438 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4439 return MCDisassembler::Fail; 4440 Inst.addOperand(MCOperand::CreateImm(align)); 4441 if (Rm != 0xF) { 4442 if (Rm != 0xD) { 4443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4444 return MCDisassembler::Fail; 4445 } else 4446 Inst.addOperand(MCOperand::CreateReg(0)); 4447 } 4448 4449 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4450 return MCDisassembler::Fail; 4451 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4452 return MCDisassembler::Fail; 4453 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4454 return MCDisassembler::Fail; 4455 Inst.addOperand(MCOperand::CreateImm(index)); 4456 4457 return S; 4458} 4459 4460 4461static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4462 uint64_t Address, const void *Decoder) { 4463 DecodeStatus S = MCDisassembler::Success; 4464 4465 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4466 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4467 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4468 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4469 unsigned size = fieldFromInstruction(Insn, 10, 2); 4470 4471 unsigned align = 0; 4472 unsigned index = 0; 4473 unsigned inc = 1; 4474 switch (size) { 4475 default: 4476 return MCDisassembler::Fail; 4477 case 0: 4478 if (fieldFromInstruction(Insn, 4, 1)) 4479 align = 4; 4480 index = fieldFromInstruction(Insn, 5, 3); 4481 break; 4482 case 1: 4483 if (fieldFromInstruction(Insn, 4, 1)) 4484 align = 8; 4485 index = fieldFromInstruction(Insn, 6, 2); 4486 if (fieldFromInstruction(Insn, 5, 1)) 4487 inc = 2; 4488 break; 4489 case 2: 4490 switch (fieldFromInstruction(Insn, 4, 2)) { 4491 case 0: 4492 align = 0; break; 4493 case 3: 4494 return MCDisassembler::Fail; 4495 default: 4496 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4497 } 4498 4499 index = fieldFromInstruction(Insn, 7, 1); 4500 if (fieldFromInstruction(Insn, 6, 1)) 4501 inc = 2; 4502 break; 4503 } 4504 4505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4506 return MCDisassembler::Fail; 4507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4508 return MCDisassembler::Fail; 4509 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4510 return MCDisassembler::Fail; 4511 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4512 return MCDisassembler::Fail; 4513 4514 if (Rm != 0xF) { // Writeback 4515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4516 return MCDisassembler::Fail; 4517 } 4518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4519 return MCDisassembler::Fail; 4520 Inst.addOperand(MCOperand::CreateImm(align)); 4521 if (Rm != 0xF) { 4522 if (Rm != 0xD) { 4523 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4524 return MCDisassembler::Fail; 4525 } else 4526 Inst.addOperand(MCOperand::CreateReg(0)); 4527 } 4528 4529 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4530 return MCDisassembler::Fail; 4531 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4532 return MCDisassembler::Fail; 4533 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4534 return MCDisassembler::Fail; 4535 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4536 return MCDisassembler::Fail; 4537 Inst.addOperand(MCOperand::CreateImm(index)); 4538 4539 return S; 4540} 4541 4542static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4543 uint64_t Address, const void *Decoder) { 4544 DecodeStatus S = MCDisassembler::Success; 4545 4546 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4547 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4548 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4549 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4550 unsigned size = fieldFromInstruction(Insn, 10, 2); 4551 4552 unsigned align = 0; 4553 unsigned index = 0; 4554 unsigned inc = 1; 4555 switch (size) { 4556 default: 4557 return MCDisassembler::Fail; 4558 case 0: 4559 if (fieldFromInstruction(Insn, 4, 1)) 4560 align = 4; 4561 index = fieldFromInstruction(Insn, 5, 3); 4562 break; 4563 case 1: 4564 if (fieldFromInstruction(Insn, 4, 1)) 4565 align = 8; 4566 index = fieldFromInstruction(Insn, 6, 2); 4567 if (fieldFromInstruction(Insn, 5, 1)) 4568 inc = 2; 4569 break; 4570 case 2: 4571 switch (fieldFromInstruction(Insn, 4, 2)) { 4572 case 0: 4573 align = 0; break; 4574 case 3: 4575 return MCDisassembler::Fail; 4576 default: 4577 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4578 } 4579 4580 index = fieldFromInstruction(Insn, 7, 1); 4581 if (fieldFromInstruction(Insn, 6, 1)) 4582 inc = 2; 4583 break; 4584 } 4585 4586 if (Rm != 0xF) { // Writeback 4587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4588 return MCDisassembler::Fail; 4589 } 4590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4591 return MCDisassembler::Fail; 4592 Inst.addOperand(MCOperand::CreateImm(align)); 4593 if (Rm != 0xF) { 4594 if (Rm != 0xD) { 4595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4596 return MCDisassembler::Fail; 4597 } else 4598 Inst.addOperand(MCOperand::CreateReg(0)); 4599 } 4600 4601 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4602 return MCDisassembler::Fail; 4603 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4604 return MCDisassembler::Fail; 4605 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4606 return MCDisassembler::Fail; 4607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4608 return MCDisassembler::Fail; 4609 Inst.addOperand(MCOperand::CreateImm(index)); 4610 4611 return S; 4612} 4613 4614static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4615 uint64_t Address, const void *Decoder) { 4616 DecodeStatus S = MCDisassembler::Success; 4617 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4618 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4619 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4620 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4621 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4622 4623 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4624 S = MCDisassembler::SoftFail; 4625 4626 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4627 return MCDisassembler::Fail; 4628 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4629 return MCDisassembler::Fail; 4630 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4631 return MCDisassembler::Fail; 4632 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4633 return MCDisassembler::Fail; 4634 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4635 return MCDisassembler::Fail; 4636 4637 return S; 4638} 4639 4640static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4641 uint64_t Address, const void *Decoder) { 4642 DecodeStatus S = MCDisassembler::Success; 4643 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4644 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4645 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4646 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4647 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4648 4649 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4650 S = MCDisassembler::SoftFail; 4651 4652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4653 return MCDisassembler::Fail; 4654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4655 return MCDisassembler::Fail; 4656 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4657 return MCDisassembler::Fail; 4658 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4659 return MCDisassembler::Fail; 4660 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4661 return MCDisassembler::Fail; 4662 4663 return S; 4664} 4665 4666static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4667 uint64_t Address, const void *Decoder) { 4668 DecodeStatus S = MCDisassembler::Success; 4669 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4670 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4671 4672 if (pred == 0xF) { 4673 pred = 0xE; 4674 S = MCDisassembler::SoftFail; 4675 } 4676 4677 if (mask == 0x0) 4678 return MCDisassembler::Fail; 4679 4680 Inst.addOperand(MCOperand::CreateImm(pred)); 4681 Inst.addOperand(MCOperand::CreateImm(mask)); 4682 return S; 4683} 4684 4685static DecodeStatus 4686DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4687 uint64_t Address, const void *Decoder) { 4688 DecodeStatus S = MCDisassembler::Success; 4689 4690 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4691 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4692 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4693 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4694 unsigned W = fieldFromInstruction(Insn, 21, 1); 4695 unsigned U = fieldFromInstruction(Insn, 23, 1); 4696 unsigned P = fieldFromInstruction(Insn, 24, 1); 4697 bool writeback = (W == 1) | (P == 0); 4698 4699 addr |= (U << 8) | (Rn << 9); 4700 4701 if (writeback && (Rn == Rt || Rn == Rt2)) 4702 Check(S, MCDisassembler::SoftFail); 4703 if (Rt == Rt2) 4704 Check(S, MCDisassembler::SoftFail); 4705 4706 // Rt 4707 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4708 return MCDisassembler::Fail; 4709 // Rt2 4710 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4711 return MCDisassembler::Fail; 4712 // Writeback operand 4713 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4714 return MCDisassembler::Fail; 4715 // addr 4716 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4717 return MCDisassembler::Fail; 4718 4719 return S; 4720} 4721 4722static DecodeStatus 4723DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4724 uint64_t Address, const void *Decoder) { 4725 DecodeStatus S = MCDisassembler::Success; 4726 4727 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4728 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4729 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4730 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4731 unsigned W = fieldFromInstruction(Insn, 21, 1); 4732 unsigned U = fieldFromInstruction(Insn, 23, 1); 4733 unsigned P = fieldFromInstruction(Insn, 24, 1); 4734 bool writeback = (W == 1) | (P == 0); 4735 4736 addr |= (U << 8) | (Rn << 9); 4737 4738 if (writeback && (Rn == Rt || Rn == Rt2)) 4739 Check(S, MCDisassembler::SoftFail); 4740 4741 // Writeback operand 4742 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4743 return MCDisassembler::Fail; 4744 // Rt 4745 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4746 return MCDisassembler::Fail; 4747 // Rt2 4748 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4749 return MCDisassembler::Fail; 4750 // addr 4751 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4752 return MCDisassembler::Fail; 4753 4754 return S; 4755} 4756 4757static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4758 uint64_t Address, const void *Decoder) { 4759 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4760 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4761 if (sign1 != sign2) return MCDisassembler::Fail; 4762 4763 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4764 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4765 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4766 Val |= sign1 << 12; 4767 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4768 4769 return MCDisassembler::Success; 4770} 4771 4772static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4773 uint64_t Address, 4774 const void *Decoder) { 4775 DecodeStatus S = MCDisassembler::Success; 4776 4777 // Shift of "asr #32" is not allowed in Thumb2 mode. 4778 if (Val == 0x20) S = MCDisassembler::SoftFail; 4779 Inst.addOperand(MCOperand::CreateImm(Val)); 4780 return S; 4781} 4782 4783static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4784 uint64_t Address, const void *Decoder) { 4785 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4786 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4787 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4788 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4789 4790 if (pred == 0xF) 4791 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4792 4793 DecodeStatus S = MCDisassembler::Success; 4794 4795 if (Rt == Rn || Rn == Rt2) 4796 S = MCDisassembler::SoftFail; 4797 4798 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4799 return MCDisassembler::Fail; 4800 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4801 return MCDisassembler::Fail; 4802 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4803 return MCDisassembler::Fail; 4804 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4805 return MCDisassembler::Fail; 4806 4807 return S; 4808} 4809 4810static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4811 uint64_t Address, const void *Decoder) { 4812 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4813 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4814 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4815 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4816 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4817 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4818 unsigned op = fieldFromInstruction(Insn, 5, 1); 4819 4820 DecodeStatus S = MCDisassembler::Success; 4821 4822 // VMOVv2f32 is ambiguous with these decodings. 4823 if (!(imm & 0x38) && cmode == 0xF) { 4824 if (op == 1) return MCDisassembler::Fail; 4825 Inst.setOpcode(ARM::VMOVv2f32); 4826 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4827 } 4828 4829 if (!(imm & 0x20)) return MCDisassembler::Fail; 4830 4831 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4832 return MCDisassembler::Fail; 4833 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4834 return MCDisassembler::Fail; 4835 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4836 4837 return S; 4838} 4839 4840static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4841 uint64_t Address, const void *Decoder) { 4842 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4843 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4844 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4845 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4846 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4847 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4848 unsigned op = fieldFromInstruction(Insn, 5, 1); 4849 4850 DecodeStatus S = MCDisassembler::Success; 4851 4852 // VMOVv4f32 is ambiguous with these decodings. 4853 if (!(imm & 0x38) && cmode == 0xF) { 4854 if (op == 1) return MCDisassembler::Fail; 4855 Inst.setOpcode(ARM::VMOVv4f32); 4856 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4857 } 4858 4859 if (!(imm & 0x20)) return MCDisassembler::Fail; 4860 4861 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4862 return MCDisassembler::Fail; 4863 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4864 return MCDisassembler::Fail; 4865 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4866 4867 return S; 4868} 4869 4870static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, 4871 const void *Decoder) 4872{ 4873 unsigned Imm = fieldFromInstruction(Insn, 0, 3); 4874 if (Imm > 4) return MCDisassembler::Fail; 4875 Inst.addOperand(MCOperand::CreateImm(Imm)); 4876 return MCDisassembler::Success; 4877} 4878 4879static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4880 uint64_t Address, const void *Decoder) { 4881 DecodeStatus S = MCDisassembler::Success; 4882 4883 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4884 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4885 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4886 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4887 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4888 4889 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4890 S = MCDisassembler::SoftFail; 4891 4892 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4893 return MCDisassembler::Fail; 4894 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4895 return MCDisassembler::Fail; 4896 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4897 return MCDisassembler::Fail; 4898 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4899 return MCDisassembler::Fail; 4900 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4901 return MCDisassembler::Fail; 4902 4903 return S; 4904} 4905 4906static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4907 uint64_t Address, const void *Decoder) { 4908 4909 DecodeStatus S = MCDisassembler::Success; 4910 4911 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4912 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4913 unsigned cop = fieldFromInstruction(Val, 8, 4); 4914 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4915 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4916 4917 if ((cop & ~0x1) == 0xa) 4918 return MCDisassembler::Fail; 4919 4920 if (Rt == Rt2) 4921 S = MCDisassembler::SoftFail; 4922 4923 Inst.addOperand(MCOperand::CreateImm(cop)); 4924 Inst.addOperand(MCOperand::CreateImm(opc1)); 4925 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4926 return MCDisassembler::Fail; 4927 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4928 return MCDisassembler::Fail; 4929 Inst.addOperand(MCOperand::CreateImm(CRm)); 4930 4931 return S; 4932} 4933 4934