ARMAsmBackend.cpp revision 9363c58dc2473a6470d3e7037afe8a215bee7e3e
1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/ARMMCTargetDesc.h" 11#include "MCTargetDesc/ARMBaseInfo.h" 12#include "MCTargetDesc/ARMFixupKinds.h" 13#include "MCTargetDesc/ARMAddressingModes.h" 14#include "llvm/ADT/Twine.h" 15#include "llvm/MC/MCAssembler.h" 16#include "llvm/MC/MCDirectives.h" 17#include "llvm/MC/MCELFObjectWriter.h" 18#include "llvm/MC/MCExpr.h" 19#include "llvm/MC/MCMachObjectWriter.h" 20#include "llvm/MC/MCObjectWriter.h" 21#include "llvm/MC/MCSectionELF.h" 22#include "llvm/MC/MCSectionMachO.h" 23#include "llvm/MC/MCAsmBackend.h" 24#include "llvm/MC/MCSubtargetInfo.h" 25#include "llvm/MC/MCValue.h" 26#include "llvm/Object/MachOFormat.h" 27#include "llvm/Support/ELF.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/raw_ostream.h" 30using namespace llvm; 31 32namespace { 33class ARMELFObjectWriter : public MCELFObjectTargetWriter { 34public: 35 ARMELFObjectWriter(uint8_t OSABI) 36 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 37 /*HasRelocationAddend*/ false) {} 38}; 39 40class ARMAsmBackend : public MCAsmBackend { 41 const MCSubtargetInfo* STI; 42 bool isThumbMode; // Currently emitting Thumb code. 43public: 44 ARMAsmBackend(const Target &T, const StringRef TT) 45 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), 46 isThumbMode(TT.startswith("thumb")) {} 47 48 ~ARMAsmBackend() { 49 delete STI; 50 } 51 52 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } 53 54 bool hasNOP() const { 55 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; 56 } 57 58 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 59 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = { 60// This table *must* be in the order that the fixup_* kinds are defined in 61// ARMFixupKinds.h. 62// 63// Name Offset (bits) Size (bits) Flags 64{ "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 65{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 66 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 67{ "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 68{ "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 69{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 71{ "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel | 72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 73{ "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 74{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 75 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 76{ "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 77{ "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 78{ "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 79{ "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 80{ "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 81{ "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 82{ "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 83{ "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 84{ "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 85{ "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 86// movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. 87{ "fixup_arm_movt_hi16", 0, 20, 0 }, 88{ "fixup_arm_movw_lo16", 0, 20, 0 }, 89{ "fixup_t2_movt_hi16", 0, 20, 0 }, 90{ "fixup_t2_movw_lo16", 0, 20, 0 }, 91{ "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 92{ "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 93{ "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 94{ "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 95 }; 96 97 if (Kind < FirstTargetFixupKind) 98 return MCAsmBackend::getFixupKindInfo(Kind); 99 100 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 101 "Invalid kind!"); 102 return Infos[Kind - FirstTargetFixupKind]; 103 } 104 105 /// processFixupValue - Target hook to process the literal value of a fixup 106 /// if necessary. 107 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, 108 const MCFixup &Fixup, const MCFragment *DF, 109 MCValue &Target, uint64_t &Value) { 110 // Some fixups to thumb function symbols need the low bit (thumb bit) 111 // twiddled. 112 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 113 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 114 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 115 if (const MCSymbolRefExpr *A = Target.getSymA()) { 116 const MCSymbol &Sym = A->getSymbol().AliasedSymbol(); 117 if (Asm.isThumbFunc(&Sym)) 118 Value |= 1; 119 } 120 } 121 } 122 123 bool mayNeedRelaxation(const MCInst &Inst) const; 124 125 bool fixupNeedsRelaxation(const MCFixup &Fixup, 126 uint64_t Value, 127 const MCInstFragment *DF, 128 const MCAsmLayout &Layout) const; 129 130 void relaxInstruction(const MCInst &Inst, MCInst &Res) const; 131 132 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const; 133 134 void handleAssemblerFlag(MCAssemblerFlag Flag) { 135 switch (Flag) { 136 default: break; 137 case MCAF_Code16: 138 setIsThumb(true); 139 break; 140 case MCAF_Code32: 141 setIsThumb(false); 142 break; 143 } 144 } 145 146 unsigned getPointerSize() const { return 4; } 147 bool isThumb() const { return isThumbMode; } 148 void setIsThumb(bool it) { isThumbMode = it; } 149}; 150} // end anonymous namespace 151 152static unsigned getRelaxedOpcode(unsigned Op) { 153 switch (Op) { 154 default: return Op; 155 case ARM::tBcc: return ARM::t2Bcc; 156 case ARM::tLDRpciASM: return ARM::t2LDRpci; 157 case ARM::tADR: return ARM::t2ADR; 158 } 159} 160 161bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 162 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 163 return true; 164 return false; 165} 166 167bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 168 uint64_t Value, 169 const MCInstFragment *DF, 170 const MCAsmLayout &Layout) const { 171 switch (Fixup.getKind()) { 172 default: assert(0 && "Unexpected fixup kind in fixupNeedsRelaxation()!"); 173 case ARM::fixup_arm_thumb_bcc: { 174 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 175 // low bit being an implied zero. There's an implied +4 offset for the 176 // branch, so we adjust the other way here to determine what's 177 // encodable. 178 // 179 // Relax if the value is too big for a (signed) i8. 180 int64_t Offset = int64_t(Value) - 4; 181 return Offset > 254 || Offset < -256; 182 } 183 case ARM::fixup_thumb_adr_pcrel_10: 184 case ARM::fixup_arm_thumb_cp: { 185 // If the immediate is negative, greater than 1020, or not a multiple 186 // of four, the wide version of the instruction must be used. 187 int64_t Offset = int64_t(Value) - 4; 188 return Offset > 1020 || Offset < 0 || Offset & 3; 189 } 190 } 191 llvm_unreachable("Invalid switch/cash!?"); 192} 193 194void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 195 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 196 197 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 198 if (RelaxedOp == Inst.getOpcode()) { 199 SmallString<256> Tmp; 200 raw_svector_ostream OS(Tmp); 201 Inst.dump_pretty(OS); 202 OS << "\n"; 203 report_fatal_error("unexpected instruction to relax: " + OS.str()); 204 } 205 206 // The instructions we're relaxing have (so far) the same operands. 207 // We just need to update to the proper opcode. 208 Res = Inst; 209 Res.setOpcode(RelaxedOp); 210} 211 212bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 213 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 214 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 215 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0 216 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 217 if (isThumb()) { 218 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding 219 : Thumb1_16bitNopEncoding; 220 uint64_t NumNops = Count / 2; 221 for (uint64_t i = 0; i != NumNops; ++i) 222 OW->Write16(nopEncoding); 223 if (Count & 1) 224 OW->Write8(0); 225 return true; 226 } 227 // ARM mode 228 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding 229 : ARMv4_NopEncoding; 230 uint64_t NumNops = Count / 4; 231 for (uint64_t i = 0; i != NumNops; ++i) 232 OW->Write32(nopEncoding); 233 // FIXME: should this function return false when unable to write exactly 234 // 'Count' bytes with NOP encodings? 235 switch (Count % 4) { 236 default: break; // No leftover bytes to write 237 case 1: OW->Write8(0); break; 238 case 2: OW->Write16(0); break; 239 case 3: OW->Write16(0); OW->Write8(0xa0); break; 240 } 241 242 return true; 243} 244 245static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 246 switch (Kind) { 247 default: 248 llvm_unreachable("Unknown fixup kind!"); 249 case FK_Data_1: 250 case FK_Data_2: 251 case FK_Data_4: 252 return Value; 253 case ARM::fixup_arm_movt_hi16: 254 Value >>= 16; 255 // Fallthrough 256 case ARM::fixup_arm_movw_lo16: 257 case ARM::fixup_arm_movt_hi16_pcrel: 258 case ARM::fixup_arm_movw_lo16_pcrel: { 259 unsigned Hi4 = (Value & 0xF000) >> 12; 260 unsigned Lo12 = Value & 0x0FFF; 261 // inst{19-16} = Hi4; 262 // inst{11-0} = Lo12; 263 Value = (Hi4 << 16) | (Lo12); 264 return Value; 265 } 266 case ARM::fixup_t2_movt_hi16: 267 Value >>= 16; 268 // Fallthrough 269 case ARM::fixup_t2_movw_lo16: 270 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like 271 // the other hi16 fixup? 272 case ARM::fixup_t2_movw_lo16_pcrel: { 273 unsigned Hi4 = (Value & 0xF000) >> 12; 274 unsigned i = (Value & 0x800) >> 11; 275 unsigned Mid3 = (Value & 0x700) >> 8; 276 unsigned Lo8 = Value & 0x0FF; 277 // inst{19-16} = Hi4; 278 // inst{26} = i; 279 // inst{14-12} = Mid3; 280 // inst{7-0} = Lo8; 281 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 282 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 283 swapped |= (Value & 0x0000FFFF) << 16; 284 return swapped; 285 } 286 case ARM::fixup_arm_ldst_pcrel_12: 287 // ARM PC-relative values are offset by 8. 288 Value -= 4; 289 // FALLTHROUGH 290 case ARM::fixup_t2_ldst_pcrel_12: { 291 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 292 Value -= 4; 293 bool isAdd = true; 294 if ((int64_t)Value < 0) { 295 Value = -Value; 296 isAdd = false; 297 } 298 assert ((Value < 4096) && "Out of range pc-relative fixup value!"); 299 Value |= isAdd << 23; 300 301 // Same addressing mode as fixup_arm_pcrel_10, 302 // but with 16-bit halfwords swapped. 303 if (Kind == ARM::fixup_t2_ldst_pcrel_12) { 304 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 305 swapped |= (Value & 0x0000FFFF) << 16; 306 return swapped; 307 } 308 309 return Value; 310 } 311 case ARM::fixup_thumb_adr_pcrel_10: 312 return ((Value - 4) >> 2) & 0xff; 313 case ARM::fixup_arm_adr_pcrel_12: { 314 // ARM PC-relative values are offset by 8. 315 Value -= 8; 316 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 317 if ((int64_t)Value < 0) { 318 Value = -Value; 319 opc = 2; // 0b0010 320 } 321 assert(ARM_AM::getSOImmVal(Value) != -1 && 322 "Out of range pc-relative fixup value!"); 323 // Encode the immediate and shift the opcode into place. 324 return ARM_AM::getSOImmVal(Value) | (opc << 21); 325 } 326 327 case ARM::fixup_t2_adr_pcrel_12: { 328 Value -= 4; 329 unsigned opc = 0; 330 if ((int64_t)Value < 0) { 331 Value = -Value; 332 opc = 5; 333 } 334 335 uint32_t out = (opc << 21); 336 out |= (Value & 0x800) << 15; 337 out |= (Value & 0x700) << 4; 338 out |= (Value & 0x0FF); 339 340 uint64_t swapped = (out & 0xFFFF0000) >> 16; 341 swapped |= (out & 0x0000FFFF) << 16; 342 return swapped; 343 } 344 345 case ARM::fixup_arm_condbranch: 346 case ARM::fixup_arm_uncondbranch: 347 // These values don't encode the low two bits since they're always zero. 348 // Offset by 8 just as above. 349 return 0xffffff & ((Value - 8) >> 2); 350 case ARM::fixup_t2_uncondbranch: { 351 Value = Value - 4; 352 Value >>= 1; // Low bit is not encoded. 353 354 uint32_t out = 0; 355 bool I = Value & 0x800000; 356 bool J1 = Value & 0x400000; 357 bool J2 = Value & 0x200000; 358 J1 ^= I; 359 J2 ^= I; 360 361 out |= I << 26; // S bit 362 out |= !J1 << 13; // J1 bit 363 out |= !J2 << 11; // J2 bit 364 out |= (Value & 0x1FF800) << 5; // imm6 field 365 out |= (Value & 0x0007FF); // imm11 field 366 367 uint64_t swapped = (out & 0xFFFF0000) >> 16; 368 swapped |= (out & 0x0000FFFF) << 16; 369 return swapped; 370 } 371 case ARM::fixup_t2_condbranch: { 372 Value = Value - 4; 373 Value >>= 1; // Low bit is not encoded. 374 375 uint64_t out = 0; 376 out |= (Value & 0x80000) << 7; // S bit 377 out |= (Value & 0x40000) >> 7; // J2 bit 378 out |= (Value & 0x20000) >> 4; // J1 bit 379 out |= (Value & 0x1F800) << 5; // imm6 field 380 out |= (Value & 0x007FF); // imm11 field 381 382 uint32_t swapped = (out & 0xFFFF0000) >> 16; 383 swapped |= (out & 0x0000FFFF) << 16; 384 return swapped; 385 } 386 case ARM::fixup_arm_thumb_bl: { 387 // The value doesn't encode the low bit (always zero) and is offset by 388 // four. The value is encoded into disjoint bit positions in the destination 389 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit 390 // 391 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII 392 // 393 // Note that the halfwords are stored high first, low second; so we need 394 // to transpose the fixup value here to map properly. 395 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0; 396 uint32_t Binary = 0; 397 Value = 0x3fffff & ((Value - 4) >> 1); 398 Binary = (Value & 0x7ff) << 16; // Low imm11 value. 399 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value. 400 Binary |= isNeg << 10; // Sign bit. 401 return Binary; 402 } 403 case ARM::fixup_arm_thumb_blx: { 404 // The value doesn't encode the low two bits (always zero) and is offset by 405 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit 406 // positions in the destination opcode. x = unchanged, I = immediate value 407 // bit, S = sign extension bit, 0 = zero. 408 // 409 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0 410 // 411 // Note that the halfwords are stored high first, low second; so we need 412 // to transpose the fixup value here to map properly. 413 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0; 414 uint32_t Binary = 0; 415 Value = 0xfffff & ((Value - 2) >> 2); 416 Binary = (Value & 0x3ff) << 17; // Low imm10L value. 417 Binary |= (Value & 0xffc00) >> 10; // High imm10H value. 418 Binary |= isNeg << 10; // Sign bit. 419 return Binary; 420 } 421 case ARM::fixup_arm_thumb_cp: 422 // Offset by 4, and don't encode the low two bits. Two bytes of that 423 // 'off by 4' is implicitly handled by the half-word ordering of the 424 // Thumb encoding, so we only need to adjust by 2 here. 425 return ((Value - 2) >> 2) & 0xff; 426 case ARM::fixup_arm_thumb_cb: { 427 // Offset by 4 and don't encode the lower bit, which is always 0. 428 uint32_t Binary = (Value - 4) >> 1; 429 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 430 } 431 case ARM::fixup_arm_thumb_br: 432 // Offset by 4 and don't encode the lower bit, which is always 0. 433 return ((Value - 4) >> 1) & 0x7ff; 434 case ARM::fixup_arm_thumb_bcc: 435 // Offset by 4 and don't encode the lower bit, which is always 0. 436 return ((Value - 4) >> 1) & 0xff; 437 case ARM::fixup_arm_pcrel_10_unscaled: { 438 Value = Value - 8; // ARM fixups offset by an additional word and don't 439 // need to adjust for the half-word ordering. 440 bool isAdd = true; 441 if ((int64_t)Value < 0) { 442 Value = -Value; 443 isAdd = false; 444 } 445 assert ((Value < 256) && "Out of range pc-relative fixup value!"); 446 return Value | (isAdd << 23); 447 } 448 case ARM::fixup_arm_pcrel_10: 449 Value = Value - 4; // ARM fixups offset by an additional word and don't 450 // need to adjust for the half-word ordering. 451 // Fall through. 452 case ARM::fixup_t2_pcrel_10: { 453 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 454 Value = Value - 4; 455 bool isAdd = true; 456 if ((int64_t)Value < 0) { 457 Value = -Value; 458 isAdd = false; 459 } 460 // These values don't encode the low two bits since they're always zero. 461 Value >>= 2; 462 assert ((Value < 256) && "Out of range pc-relative fixup value!"); 463 Value |= isAdd << 23; 464 465 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 466 // swapped. 467 if (Kind == ARM::fixup_t2_pcrel_10) { 468 uint32_t swapped = (Value & 0xFFFF0000) >> 16; 469 swapped |= (Value & 0x0000FFFF) << 16; 470 return swapped; 471 } 472 473 return Value; 474 } 475 } 476} 477 478namespace { 479 480// FIXME: This should be in a separate file. 481// ELF is an ELF of course... 482class ELFARMAsmBackend : public ARMAsmBackend { 483public: 484 uint8_t OSABI; 485 ELFARMAsmBackend(const Target &T, const StringRef TT, 486 uint8_t _OSABI) 487 : ARMAsmBackend(T, TT), OSABI(_OSABI) { } 488 489 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 490 uint64_t Value) const; 491 492 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 493 return createARMELFObjectWriter(OS, OSABI); 494 } 495}; 496 497// FIXME: Raise this to share code between Darwin and ELF. 498void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 499 unsigned DataSize, uint64_t Value) const { 500 unsigned NumBytes = 4; // FIXME: 2 for Thumb 501 Value = adjustFixupValue(Fixup.getKind(), Value); 502 if (!Value) return; // Doesn't change encoding. 503 504 unsigned Offset = Fixup.getOffset(); 505 506 // For each byte of the fragment that the fixup touches, mask in the bits from 507 // the fixup value. The Value has been "split up" into the appropriate 508 // bitfields above. 509 for (unsigned i = 0; i != NumBytes; ++i) 510 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 511} 512 513// FIXME: This should be in a separate file. 514class DarwinARMAsmBackend : public ARMAsmBackend { 515public: 516 const object::mach::CPUSubtypeARM Subtype; 517 DarwinARMAsmBackend(const Target &T, const StringRef TT, 518 object::mach::CPUSubtypeARM st) 519 : ARMAsmBackend(T, TT), Subtype(st) { } 520 521 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 522 return createARMMachObjectWriter(OS, /*Is64Bit=*/false, 523 object::mach::CTM_ARM, 524 Subtype); 525 } 526 527 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 528 uint64_t Value) const; 529 530 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 531 return false; 532 } 533}; 534 535/// getFixupKindNumBytes - The number of bytes the fixup may change. 536static unsigned getFixupKindNumBytes(unsigned Kind) { 537 switch (Kind) { 538 default: 539 llvm_unreachable("Unknown fixup kind!"); 540 541 case FK_Data_1: 542 case ARM::fixup_arm_thumb_bcc: 543 case ARM::fixup_arm_thumb_cp: 544 case ARM::fixup_thumb_adr_pcrel_10: 545 return 1; 546 547 case FK_Data_2: 548 case ARM::fixup_arm_thumb_br: 549 case ARM::fixup_arm_thumb_cb: 550 return 2; 551 552 case ARM::fixup_arm_pcrel_10_unscaled: 553 case ARM::fixup_arm_ldst_pcrel_12: 554 case ARM::fixup_arm_pcrel_10: 555 case ARM::fixup_arm_adr_pcrel_12: 556 case ARM::fixup_arm_condbranch: 557 case ARM::fixup_arm_uncondbranch: 558 return 3; 559 560 case FK_Data_4: 561 case ARM::fixup_t2_ldst_pcrel_12: 562 case ARM::fixup_t2_condbranch: 563 case ARM::fixup_t2_uncondbranch: 564 case ARM::fixup_t2_pcrel_10: 565 case ARM::fixup_t2_adr_pcrel_12: 566 case ARM::fixup_arm_thumb_bl: 567 case ARM::fixup_arm_thumb_blx: 568 case ARM::fixup_arm_movt_hi16: 569 case ARM::fixup_arm_movw_lo16: 570 case ARM::fixup_arm_movt_hi16_pcrel: 571 case ARM::fixup_arm_movw_lo16_pcrel: 572 case ARM::fixup_t2_movt_hi16: 573 case ARM::fixup_t2_movw_lo16: 574 case ARM::fixup_t2_movt_hi16_pcrel: 575 case ARM::fixup_t2_movw_lo16_pcrel: 576 return 4; 577 } 578} 579 580void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 581 unsigned DataSize, uint64_t Value) const { 582 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 583 Value = adjustFixupValue(Fixup.getKind(), Value); 584 if (!Value) return; // Doesn't change encoding. 585 586 unsigned Offset = Fixup.getOffset(); 587 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 588 589 // For each byte of the fragment that the fixup touches, mask in the 590 // bits from the fixup value. 591 for (unsigned i = 0; i != NumBytes; ++i) 592 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 593} 594 595} // end anonymous namespace 596 597MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) { 598 Triple TheTriple(TT); 599 600 if (TheTriple.isOSDarwin()) { 601 if (TheTriple.getArchName() == "armv4t" || 602 TheTriple.getArchName() == "thumbv4t") 603 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T); 604 else if (TheTriple.getArchName() == "armv5e" || 605 TheTriple.getArchName() == "thumbv5e") 606 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ); 607 else if (TheTriple.getArchName() == "armv6" || 608 TheTriple.getArchName() == "thumbv6") 609 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6); 610 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7); 611 } 612 613 if (TheTriple.isOSWindows()) 614 assert(0 && "Windows not supported on ARM"); 615 616 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); 617 return new ELFARMAsmBackend(T, TT, OSABI); 618} 619