1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARMMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/ARMMCTargetDesc.h"
16#include "MCTargetDesc/ARMAddressingModes.h"
17#include "MCTargetDesc/ARMBaseInfo.h"
18#include "MCTargetDesc/ARMFixupKinds.h"
19#include "MCTargetDesc/ARMMCExpr.h"
20#include "llvm/ADT/APFloat.h"
21#include "llvm/ADT/Statistic.h"
22#include "llvm/MC/MCCodeEmitter.h"
23#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrInfo.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/Support/raw_ostream.h"
30
31using namespace llvm;
32
33STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
34STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
35
36namespace {
37class ARMMCCodeEmitter : public MCCodeEmitter {
38  ARMMCCodeEmitter(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
39  void operator=(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION;
40  const MCInstrInfo &MCII;
41  const MCSubtargetInfo &STI;
42  const MCContext &CTX;
43
44public:
45  ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
46                   MCContext &ctx)
47    : MCII(mcii), STI(sti), CTX(ctx) {
48  }
49
50  ~ARMMCCodeEmitter() {}
51
52  bool isThumb() const {
53    // FIXME: Can tablegen auto-generate this?
54    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
55  }
56  bool isThumb2() const {
57    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
58  }
59  bool isTargetDarwin() const {
60    Triple TT(STI.getTargetTriple());
61    Triple::OSType OS = TT.getOS();
62    return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
63  }
64
65  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
66
67  // getBinaryCodeForInstr - TableGen'erated function for getting the
68  // binary encoding for an instruction.
69  uint64_t getBinaryCodeForInstr(const MCInst &MI,
70                                 SmallVectorImpl<MCFixup> &Fixups) const;
71
72  /// getMachineOpValue - Return binary encoding of operand. If the machine
73  /// operand requires relocation, record the relocation and return zero.
74  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
75                             SmallVectorImpl<MCFixup> &Fixups) const;
76
77  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
78  /// the specified operand. This is used for operands with :lower16: and
79  /// :upper16: prefixes.
80  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81                               SmallVectorImpl<MCFixup> &Fixups) const;
82
83  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
84                              unsigned &Reg, unsigned &Imm,
85                              SmallVectorImpl<MCFixup> &Fixups) const;
86
87  /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
88  /// BL branch target.
89  uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
90                                   SmallVectorImpl<MCFixup> &Fixups) const;
91
92  /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
93  /// BLX branch target.
94  uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
95                                    SmallVectorImpl<MCFixup> &Fixups) const;
96
97  /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
98  uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
99                                   SmallVectorImpl<MCFixup> &Fixups) const;
100
101  /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
102  uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
103                                    SmallVectorImpl<MCFixup> &Fixups) const;
104
105  /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
106  uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
107                                   SmallVectorImpl<MCFixup> &Fixups) const;
108
109  /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
110  /// branch target.
111  uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
112                                  SmallVectorImpl<MCFixup> &Fixups) const;
113
114  /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
115  /// immediate Thumb2 direct branch target.
116  uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
117                                  SmallVectorImpl<MCFixup> &Fixups) const;
118
119  /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
120  /// branch target.
121  uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
122                                     SmallVectorImpl<MCFixup> &Fixups) const;
123  uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
124                                 SmallVectorImpl<MCFixup> &Fixups) const;
125  uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
126                                  SmallVectorImpl<MCFixup> &Fixups) const;
127
128  /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
129  /// ADR label target.
130  uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131                              SmallVectorImpl<MCFixup> &Fixups) const;
132  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
133                              SmallVectorImpl<MCFixup> &Fixups) const;
134  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
135                              SmallVectorImpl<MCFixup> &Fixups) const;
136
137
138  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
139  /// operand.
140  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
141                                   SmallVectorImpl<MCFixup> &Fixups) const;
142
143  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
144  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
145                                         SmallVectorImpl<MCFixup> &Fixups)const;
146
147  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
148  /// operand.
149  uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
150                                   SmallVectorImpl<MCFixup> &Fixups) const;
151
152  /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
153  /// operand.
154  uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
155                                   SmallVectorImpl<MCFixup> &Fixups) const;
156
157  /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
158  /// operand.
159  uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
160                              SmallVectorImpl<MCFixup> &Fixups) const;
161
162
163  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
164  /// operand as needed by load/store instructions.
165  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
166                               SmallVectorImpl<MCFixup> &Fixups) const;
167
168  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
169  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
170                               SmallVectorImpl<MCFixup> &Fixups) const {
171    ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
172    switch (Mode) {
173    default: llvm_unreachable("Unknown addressing sub-mode!");
174    case ARM_AM::da: return 0;
175    case ARM_AM::ia: return 1;
176    case ARM_AM::db: return 2;
177    case ARM_AM::ib: return 3;
178    }
179  }
180  /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
181  ///
182  unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
183    switch (ShOpc) {
184    case ARM_AM::no_shift:
185    case ARM_AM::lsl: return 0;
186    case ARM_AM::lsr: return 1;
187    case ARM_AM::asr: return 2;
188    case ARM_AM::ror:
189    case ARM_AM::rrx: return 3;
190    }
191    llvm_unreachable("Invalid ShiftOpc!");
192  }
193
194  /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
195  uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
196                               SmallVectorImpl<MCFixup> &Fixups) const;
197
198  /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
199  uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
200                                     SmallVectorImpl<MCFixup> &Fixups) const;
201
202  /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
203  uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
204                                SmallVectorImpl<MCFixup> &Fixups) const;
205
206  /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
207  uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
208                                     SmallVectorImpl<MCFixup> &Fixups) const;
209
210  /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
211  uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
212                               SmallVectorImpl<MCFixup> &Fixups) const;
213
214  /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
215  /// operand.
216  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
217                                     SmallVectorImpl<MCFixup> &Fixups) const;
218
219  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
220  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
221                                SmallVectorImpl<MCFixup> &Fixups) const;
222
223  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
224  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
225                                SmallVectorImpl<MCFixup> &Fixups) const;
226
227  /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
228  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
229                               SmallVectorImpl<MCFixup> &Fixups) const;
230
231  /// getCCOutOpValue - Return encoding of the 's' bit.
232  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
233                           SmallVectorImpl<MCFixup> &Fixups) const {
234    // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
235    // '1' respectively.
236    return MI.getOperand(Op).getReg() == ARM::CPSR;
237  }
238
239  /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
240  unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
241                           SmallVectorImpl<MCFixup> &Fixups) const {
242    unsigned SoImm = MI.getOperand(Op).getImm();
243    int SoImmVal = ARM_AM::getSOImmVal(SoImm);
244    assert(SoImmVal != -1 && "Not a valid so_imm value!");
245
246    // Encode rotate_imm.
247    unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
248      << ARMII::SoRotImmShift;
249
250    // Encode immed_8.
251    Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
252    return Binary;
253  }
254
255  /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
256  unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
257                           SmallVectorImpl<MCFixup> &Fixups) const {
258    unsigned SoImm = MI.getOperand(Op).getImm();
259    unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
260    assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
261    return Encoded;
262  }
263
264  unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
265    SmallVectorImpl<MCFixup> &Fixups) const;
266  unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
267    SmallVectorImpl<MCFixup> &Fixups) const;
268  unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
269    SmallVectorImpl<MCFixup> &Fixups) const;
270  unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
271    SmallVectorImpl<MCFixup> &Fixups) const;
272
273  /// getSORegOpValue - Return an encoded so_reg shifted register value.
274  unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
275                           SmallVectorImpl<MCFixup> &Fixups) const;
276  unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
277                           SmallVectorImpl<MCFixup> &Fixups) const;
278  unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
279                             SmallVectorImpl<MCFixup> &Fixups) const;
280
281  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
282                                   SmallVectorImpl<MCFixup> &Fixups) const {
283    return 64 - MI.getOperand(Op).getImm();
284  }
285
286  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
287                                      SmallVectorImpl<MCFixup> &Fixups) const;
288
289  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
290                                  SmallVectorImpl<MCFixup> &Fixups) const;
291  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
292                                      SmallVectorImpl<MCFixup> &Fixups) const;
293  unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
294                                        SmallVectorImpl<MCFixup> &Fixups) const;
295  unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
296                                        SmallVectorImpl<MCFixup> &Fixups) const;
297  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
298                                     SmallVectorImpl<MCFixup> &Fixups) const;
299
300  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
301                             SmallVectorImpl<MCFixup> &Fixups) const;
302  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
303                              SmallVectorImpl<MCFixup> &Fixups) const;
304  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
305                              SmallVectorImpl<MCFixup> &Fixups) const;
306  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
307                              SmallVectorImpl<MCFixup> &Fixups) const;
308
309  unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
310                                 SmallVectorImpl<MCFixup> &Fixups) const;
311
312  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
313                                      unsigned EncodedValue) const;
314  unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
315                                          unsigned EncodedValue) const;
316  unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
317                                    unsigned EncodedValue) const;
318  unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
319                                   unsigned EncodedValue) const;
320
321  unsigned VFPThumb2PostEncoder(const MCInst &MI,
322                                unsigned EncodedValue) const;
323
324  void EmitByte(unsigned char C, raw_ostream &OS) const {
325    OS << (char)C;
326  }
327
328  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
329    // Output the constant in little endian byte order.
330    for (unsigned i = 0; i != Size; ++i) {
331      EmitByte(Val & 255, OS);
332      Val >>= 8;
333    }
334  }
335
336  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
337                         SmallVectorImpl<MCFixup> &Fixups) const;
338};
339
340} // end anonymous namespace
341
342MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
343                                            const MCRegisterInfo &MRI,
344                                            const MCSubtargetInfo &STI,
345                                            MCContext &Ctx) {
346  return new ARMMCCodeEmitter(MCII, STI, Ctx);
347}
348
349/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
350/// instructions, and rewrite them to their Thumb2 form if we are currently in
351/// Thumb2 mode.
352unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
353                                                 unsigned EncodedValue) const {
354  if (isThumb2()) {
355    // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
356    // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
357    // set to 1111.
358    unsigned Bit24 = EncodedValue & 0x01000000;
359    unsigned Bit28 = Bit24 << 4;
360    EncodedValue &= 0xEFFFFFFF;
361    EncodedValue |= Bit28;
362    EncodedValue |= 0x0F000000;
363  }
364
365  return EncodedValue;
366}
367
368/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
369/// instructions, and rewrite them to their Thumb2 form if we are currently in
370/// Thumb2 mode.
371unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
372                                                 unsigned EncodedValue) const {
373  if (isThumb2()) {
374    EncodedValue &= 0xF0FFFFFF;
375    EncodedValue |= 0x09000000;
376  }
377
378  return EncodedValue;
379}
380
381/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
382/// instructions, and rewrite them to their Thumb2 form if we are currently in
383/// Thumb2 mode.
384unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
385                                                 unsigned EncodedValue) const {
386  if (isThumb2()) {
387    EncodedValue &= 0x00FFFFFF;
388    EncodedValue |= 0xEE000000;
389  }
390
391  return EncodedValue;
392}
393
394/// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
395/// if we are in Thumb2.
396unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
397                                                 unsigned EncodedValue) const {
398  if (isThumb2()) {
399    EncodedValue |= 0xC000000; // Set bits 27-26
400  }
401
402  return EncodedValue;
403}
404
405/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
406/// them to their Thumb2 form if we are currently in Thumb2 mode.
407unsigned ARMMCCodeEmitter::
408VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
409  if (isThumb2()) {
410    EncodedValue &= 0x0FFFFFFF;
411    EncodedValue |= 0xE0000000;
412  }
413  return EncodedValue;
414}
415
416/// getMachineOpValue - Return binary encoding of operand. If the machine
417/// operand requires relocation, record the relocation and return zero.
418unsigned ARMMCCodeEmitter::
419getMachineOpValue(const MCInst &MI, const MCOperand &MO,
420                  SmallVectorImpl<MCFixup> &Fixups) const {
421  if (MO.isReg()) {
422    unsigned Reg = MO.getReg();
423    unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
424
425    // Q registers are encoded as 2x their register number.
426    switch (Reg) {
427    default:
428      return RegNo;
429    case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
430    case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
431    case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
432    case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
433      return 2 * RegNo;
434    }
435  } else if (MO.isImm()) {
436    return static_cast<unsigned>(MO.getImm());
437  } else if (MO.isFPImm()) {
438    return static_cast<unsigned>(APFloat(MO.getFPImm())
439                     .bitcastToAPInt().getHiBits(32).getLimitedValue());
440  }
441
442  llvm_unreachable("Unable to encode MCOperand!");
443}
444
445/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
446bool ARMMCCodeEmitter::
447EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
448                       unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
449  const MCOperand &MO  = MI.getOperand(OpIdx);
450  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
451
452  Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
453
454  int32_t SImm = MO1.getImm();
455  bool isAdd = true;
456
457  // Special value for #-0
458  if (SImm == INT32_MIN) {
459    SImm = 0;
460    isAdd = false;
461  }
462
463  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
464  if (SImm < 0) {
465    SImm = -SImm;
466    isAdd = false;
467  }
468
469  Imm = SImm;
470  return isAdd;
471}
472
473/// getBranchTargetOpValue - Helper function to get the branch target operand,
474/// which is either an immediate or requires a fixup.
475static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
476                                       unsigned FixupKind,
477                                       SmallVectorImpl<MCFixup> &Fixups) {
478  const MCOperand &MO = MI.getOperand(OpIdx);
479
480  // If the destination is an immediate, we have nothing to do.
481  if (MO.isImm()) return MO.getImm();
482  assert(MO.isExpr() && "Unexpected branch target type!");
483  const MCExpr *Expr = MO.getExpr();
484  MCFixupKind Kind = MCFixupKind(FixupKind);
485  Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
486
487  // All of the information is in the fixup.
488  return 0;
489}
490
491// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
492// determined by negating them and XOR'ing them with bit 23.
493static int32_t encodeThumbBLOffset(int32_t offset) {
494  offset >>= 1;
495  uint32_t S  = (offset & 0x800000) >> 23;
496  uint32_t J1 = (offset & 0x400000) >> 22;
497  uint32_t J2 = (offset & 0x200000) >> 21;
498  J1 = (~J1 & 0x1);
499  J2 = (~J2 & 0x1);
500  J1 ^= S;
501  J2 ^= S;
502
503  offset &= ~0x600000;
504  offset |= J1 << 22;
505  offset |= J2 << 21;
506
507  return offset;
508}
509
510/// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
511uint32_t ARMMCCodeEmitter::
512getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
513                        SmallVectorImpl<MCFixup> &Fixups) const {
514  const MCOperand MO = MI.getOperand(OpIdx);
515  if (MO.isExpr())
516    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
517                                    Fixups);
518  return encodeThumbBLOffset(MO.getImm());
519}
520
521/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
522/// BLX branch target.
523uint32_t ARMMCCodeEmitter::
524getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
525                         SmallVectorImpl<MCFixup> &Fixups) const {
526  const MCOperand MO = MI.getOperand(OpIdx);
527  if (MO.isExpr())
528    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
529                                    Fixups);
530  return encodeThumbBLOffset(MO.getImm());
531}
532
533/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
534uint32_t ARMMCCodeEmitter::
535getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
536                        SmallVectorImpl<MCFixup> &Fixups) const {
537  const MCOperand MO = MI.getOperand(OpIdx);
538  if (MO.isExpr())
539    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
540                                    Fixups);
541  return (MO.getImm() >> 1);
542}
543
544/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
545uint32_t ARMMCCodeEmitter::
546getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
547                         SmallVectorImpl<MCFixup> &Fixups) const {
548  const MCOperand MO = MI.getOperand(OpIdx);
549  if (MO.isExpr())
550    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
551                                    Fixups);
552  return (MO.getImm() >> 1);
553}
554
555/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
556uint32_t ARMMCCodeEmitter::
557getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
558                        SmallVectorImpl<MCFixup> &Fixups) const {
559  const MCOperand MO = MI.getOperand(OpIdx);
560  if (MO.isExpr())
561    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
562  return (MO.getImm() >> 1);
563}
564
565/// Return true if this branch has a non-always predication
566static bool HasConditionalBranch(const MCInst &MI) {
567  int NumOp = MI.getNumOperands();
568  if (NumOp >= 2) {
569    for (int i = 0; i < NumOp-1; ++i) {
570      const MCOperand &MCOp1 = MI.getOperand(i);
571      const MCOperand &MCOp2 = MI.getOperand(i + 1);
572      if (MCOp1.isImm() && MCOp2.isReg() &&
573          (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
574        if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
575          return true;
576      }
577    }
578  }
579  return false;
580}
581
582/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
583/// target.
584uint32_t ARMMCCodeEmitter::
585getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
586                       SmallVectorImpl<MCFixup> &Fixups) const {
587  // FIXME: This really, really shouldn't use TargetMachine. We don't want
588  // coupling between MC and TM anywhere we can help it.
589  if (isThumb2())
590    return
591      ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
592  return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
593}
594
595/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
596/// target.
597uint32_t ARMMCCodeEmitter::
598getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
599                          SmallVectorImpl<MCFixup> &Fixups) const {
600  const MCOperand MO = MI.getOperand(OpIdx);
601  if (MO.isExpr()) {
602    if (HasConditionalBranch(MI))
603      return ::getBranchTargetOpValue(MI, OpIdx,
604                                      ARM::fixup_arm_condbranch, Fixups);
605    return ::getBranchTargetOpValue(MI, OpIdx,
606                                    ARM::fixup_arm_uncondbranch, Fixups);
607  }
608
609  return MO.getImm() >> 2;
610}
611
612uint32_t ARMMCCodeEmitter::
613getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
614                          SmallVectorImpl<MCFixup> &Fixups) const {
615  const MCOperand MO = MI.getOperand(OpIdx);
616  if (MO.isExpr()) {
617    if (HasConditionalBranch(MI))
618      return ::getBranchTargetOpValue(MI, OpIdx,
619                                      ARM::fixup_arm_condbl, Fixups);
620    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups);
621  }
622
623  return MO.getImm() >> 2;
624}
625
626uint32_t ARMMCCodeEmitter::
627getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
628                          SmallVectorImpl<MCFixup> &Fixups) const {
629  const MCOperand MO = MI.getOperand(OpIdx);
630  if (MO.isExpr())
631    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups);
632
633  return MO.getImm() >> 1;
634}
635
636/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
637/// immediate branch target.
638uint32_t ARMMCCodeEmitter::
639getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
640                       SmallVectorImpl<MCFixup> &Fixups) const {
641  unsigned Val =
642    ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
643  bool I  = (Val & 0x800000);
644  bool J1 = (Val & 0x400000);
645  bool J2 = (Val & 0x200000);
646  if (I ^ J1)
647    Val &= ~0x400000;
648  else
649    Val |= 0x400000;
650
651  if (I ^ J2)
652    Val &= ~0x200000;
653  else
654    Val |= 0x200000;
655
656  return Val;
657}
658
659/// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
660/// ADR label target.
661uint32_t ARMMCCodeEmitter::
662getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
663                   SmallVectorImpl<MCFixup> &Fixups) const {
664  const MCOperand MO = MI.getOperand(OpIdx);
665  if (MO.isExpr())
666    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
667                                    Fixups);
668  int32_t offset = MO.getImm();
669  uint32_t Val = 0x2000;
670
671  int SoImmVal;
672  if (offset == INT32_MIN) {
673    Val = 0x1000;
674    SoImmVal = 0;
675  } else if (offset < 0) {
676    Val = 0x1000;
677    offset *= -1;
678    SoImmVal = ARM_AM::getSOImmVal(offset);
679    if(SoImmVal == -1) {
680      Val = 0x2000;
681      offset *= -1;
682      SoImmVal = ARM_AM::getSOImmVal(offset);
683    }
684  } else {
685    SoImmVal = ARM_AM::getSOImmVal(offset);
686    if(SoImmVal == -1) {
687      Val = 0x1000;
688      offset *= -1;
689      SoImmVal = ARM_AM::getSOImmVal(offset);
690    }
691  }
692
693  assert(SoImmVal != -1 && "Not a valid so_imm value!");
694
695  Val |= SoImmVal;
696  return Val;
697}
698
699/// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
700/// target.
701uint32_t ARMMCCodeEmitter::
702getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
703                   SmallVectorImpl<MCFixup> &Fixups) const {
704  const MCOperand MO = MI.getOperand(OpIdx);
705  if (MO.isExpr())
706    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
707                                    Fixups);
708  int32_t Val = MO.getImm();
709  if (Val == INT32_MIN)
710    Val = 0x1000;
711  else if (Val < 0) {
712    Val *= -1;
713    Val |= 0x1000;
714  }
715  return Val;
716}
717
718/// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
719/// target.
720uint32_t ARMMCCodeEmitter::
721getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
722                   SmallVectorImpl<MCFixup> &Fixups) const {
723  const MCOperand MO = MI.getOperand(OpIdx);
724  if (MO.isExpr())
725    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
726                                    Fixups);
727  return MO.getImm();
728}
729
730/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
731/// operand.
732uint32_t ARMMCCodeEmitter::
733getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
734                              SmallVectorImpl<MCFixup> &) const {
735  // [Rn, Rm]
736  //   {5-3} = Rm
737  //   {2-0} = Rn
738  const MCOperand &MO1 = MI.getOperand(OpIdx);
739  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
740  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
741  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
742  return (Rm << 3) | Rn;
743}
744
745/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
746uint32_t ARMMCCodeEmitter::
747getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
748                        SmallVectorImpl<MCFixup> &Fixups) const {
749  // {17-13} = reg
750  // {12}    = (U)nsigned (add == '1', sub == '0')
751  // {11-0}  = imm12
752  unsigned Reg, Imm12;
753  bool isAdd = true;
754  // If The first operand isn't a register, we have a label reference.
755  const MCOperand &MO = MI.getOperand(OpIdx);
756  if (!MO.isReg()) {
757    Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
758    Imm12 = 0;
759
760    if (MO.isExpr()) {
761      const MCExpr *Expr = MO.getExpr();
762      isAdd = false ; // 'U' bit is set as part of the fixup.
763
764      MCFixupKind Kind;
765      if (isThumb2())
766        Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
767      else
768        Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
769      Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
770
771      ++MCNumCPRelocations;
772    } else {
773      Reg = ARM::PC;
774      int32_t Offset = MO.getImm();
775      // FIXME: Handle #-0.
776      if (Offset < 0) {
777        Offset *= -1;
778        isAdd = false;
779      }
780      Imm12 = Offset;
781    }
782  } else
783    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
784
785  uint32_t Binary = Imm12 & 0xfff;
786  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
787  if (isAdd)
788    Binary |= (1 << 12);
789  Binary |= (Reg << 13);
790  return Binary;
791}
792
793/// getT2Imm8s4OpValue - Return encoding info for
794/// '+/- imm8<<2' operand.
795uint32_t ARMMCCodeEmitter::
796getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
797                   SmallVectorImpl<MCFixup> &Fixups) const {
798  // FIXME: The immediate operand should have already been encoded like this
799  // before ever getting here. The encoder method should just need to combine
800  // the MI operands for the register and the offset into a single
801  // representation for the complex operand in the .td file. This isn't just
802  // style, unfortunately. As-is, we can't represent the distinct encoding
803  // for #-0.
804
805  // {8}    = (U)nsigned (add == '1', sub == '0')
806  // {7-0}  = imm8
807  int32_t Imm8 = MI.getOperand(OpIdx).getImm();
808  bool isAdd = Imm8 >= 0;
809
810  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
811  if (Imm8 < 0)
812    Imm8 = -(uint32_t)Imm8;
813
814  // Scaled by 4.
815  Imm8 /= 4;
816
817  uint32_t Binary = Imm8 & 0xff;
818  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
819  if (isAdd)
820    Binary |= (1 << 8);
821  return Binary;
822}
823
824/// getT2AddrModeImm8s4OpValue - Return encoding info for
825/// 'reg +/- imm8<<2' operand.
826uint32_t ARMMCCodeEmitter::
827getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
828                        SmallVectorImpl<MCFixup> &Fixups) const {
829  // {12-9} = reg
830  // {8}    = (U)nsigned (add == '1', sub == '0')
831  // {7-0}  = imm8
832  unsigned Reg, Imm8;
833  bool isAdd = true;
834  // If The first operand isn't a register, we have a label reference.
835  const MCOperand &MO = MI.getOperand(OpIdx);
836  if (!MO.isReg()) {
837    Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
838    Imm8 = 0;
839    isAdd = false ; // 'U' bit is set as part of the fixup.
840
841    assert(MO.isExpr() && "Unexpected machine operand type!");
842    const MCExpr *Expr = MO.getExpr();
843    MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
844    Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
845
846    ++MCNumCPRelocations;
847  } else
848    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
849
850  // FIXME: The immediate operand should have already been encoded like this
851  // before ever getting here. The encoder method should just need to combine
852  // the MI operands for the register and the offset into a single
853  // representation for the complex operand in the .td file. This isn't just
854  // style, unfortunately. As-is, we can't represent the distinct encoding
855  // for #-0.
856  uint32_t Binary = (Imm8 >> 2) & 0xff;
857  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
858  if (isAdd)
859    Binary |= (1 << 8);
860  Binary |= (Reg << 9);
861  return Binary;
862}
863
864/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
865/// 'reg + imm8<<2' operand.
866uint32_t ARMMCCodeEmitter::
867getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
868                        SmallVectorImpl<MCFixup> &Fixups) const {
869  // {11-8} = reg
870  // {7-0}  = imm8
871  const MCOperand &MO = MI.getOperand(OpIdx);
872  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
873  unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
874  unsigned Imm8 = MO1.getImm();
875  return (Reg << 8) | Imm8;
876}
877
878// FIXME: This routine assumes that a binary
879// expression will always result in a PCRel expression
880// In reality, its only true if one or more subexpressions
881// is itself a PCRel (i.e. "." in asm or some other pcrel construct)
882// but this is good enough for now.
883static bool EvaluateAsPCRel(const MCExpr *Expr) {
884  switch (Expr->getKind()) {
885  default: llvm_unreachable("Unexpected expression type");
886  case MCExpr::SymbolRef: return false;
887  case MCExpr::Binary: return true;
888  }
889}
890
891uint32_t
892ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
893                                      SmallVectorImpl<MCFixup> &Fixups) const {
894  // {20-16} = imm{15-12}
895  // {11-0}  = imm{11-0}
896  const MCOperand &MO = MI.getOperand(OpIdx);
897  if (MO.isImm())
898    // Hi / lo 16 bits already extracted during earlier passes.
899    return static_cast<unsigned>(MO.getImm());
900
901  // Handle :upper16: and :lower16: assembly prefixes.
902  const MCExpr *E = MO.getExpr();
903  MCFixupKind Kind;
904  if (E->getKind() == MCExpr::Target) {
905    const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
906    E = ARM16Expr->getSubExpr();
907
908    switch (ARM16Expr->getKind()) {
909    default: llvm_unreachable("Unsupported ARMFixup");
910    case ARMMCExpr::VK_ARM_HI16:
911      if (!isTargetDarwin() && EvaluateAsPCRel(E))
912        Kind = MCFixupKind(isThumb2()
913                           ? ARM::fixup_t2_movt_hi16_pcrel
914                           : ARM::fixup_arm_movt_hi16_pcrel);
915      else
916        Kind = MCFixupKind(isThumb2()
917                           ? ARM::fixup_t2_movt_hi16
918                           : ARM::fixup_arm_movt_hi16);
919      break;
920    case ARMMCExpr::VK_ARM_LO16:
921      if (!isTargetDarwin() && EvaluateAsPCRel(E))
922        Kind = MCFixupKind(isThumb2()
923                           ? ARM::fixup_t2_movw_lo16_pcrel
924                           : ARM::fixup_arm_movw_lo16_pcrel);
925      else
926        Kind = MCFixupKind(isThumb2()
927                           ? ARM::fixup_t2_movw_lo16
928                           : ARM::fixup_arm_movw_lo16);
929      break;
930    }
931    Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
932    return 0;
933  }
934  // If the expression doesn't have :upper16: or :lower16: on it,
935  // it's just a plain immediate expression, and those evaluate to
936  // the lower 16 bits of the expression regardless of whether
937  // we have a movt or a movw.
938  if (!isTargetDarwin() && EvaluateAsPCRel(E))
939    Kind = MCFixupKind(isThumb2()
940                       ? ARM::fixup_t2_movw_lo16_pcrel
941                       : ARM::fixup_arm_movw_lo16_pcrel);
942  else
943    Kind = MCFixupKind(isThumb2()
944                       ? ARM::fixup_t2_movw_lo16
945                       : ARM::fixup_arm_movw_lo16);
946  Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
947  return 0;
948}
949
950uint32_t ARMMCCodeEmitter::
951getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
952                    SmallVectorImpl<MCFixup> &Fixups) const {
953  const MCOperand &MO = MI.getOperand(OpIdx);
954  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
955  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
956  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
957  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
958  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
959  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
960  ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
961  unsigned SBits = getShiftOp(ShOp);
962
963  // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
964  // amount. However, it would be an easy mistake to make so check here.
965  assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
966
967  // {16-13} = Rn
968  // {12}    = isAdd
969  // {11-0}  = shifter
970  //  {3-0}  = Rm
971  //  {4}    = 0
972  //  {6-5}  = type
973  //  {11-7} = imm
974  uint32_t Binary = Rm;
975  Binary |= Rn << 13;
976  Binary |= SBits << 5;
977  Binary |= ShImm << 7;
978  if (isAdd)
979    Binary |= 1 << 12;
980  return Binary;
981}
982
983uint32_t ARMMCCodeEmitter::
984getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
985                    SmallVectorImpl<MCFixup> &Fixups) const {
986  // {17-14}  Rn
987  // {13}     1 == imm12, 0 == Rm
988  // {12}     isAdd
989  // {11-0}   imm12/Rm
990  const MCOperand &MO = MI.getOperand(OpIdx);
991  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
992  uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
993  Binary |= Rn << 14;
994  return Binary;
995}
996
997uint32_t ARMMCCodeEmitter::
998getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
999                          SmallVectorImpl<MCFixup> &Fixups) const {
1000  // {13}     1 == imm12, 0 == Rm
1001  // {12}     isAdd
1002  // {11-0}   imm12/Rm
1003  const MCOperand &MO = MI.getOperand(OpIdx);
1004  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1005  unsigned Imm = MO1.getImm();
1006  bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1007  bool isReg = MO.getReg() != 0;
1008  uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1009  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1010  if (isReg) {
1011    ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1012    Binary <<= 7;                    // Shift amount is bits [11:7]
1013    Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1014    Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1015  }
1016  return Binary | (isAdd << 12) | (isReg << 13);
1017}
1018
1019uint32_t ARMMCCodeEmitter::
1020getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1021                     SmallVectorImpl<MCFixup> &Fixups) const {
1022  // {4}      isAdd
1023  // {3-0}    Rm
1024  const MCOperand &MO = MI.getOperand(OpIdx);
1025  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1026  bool isAdd = MO1.getImm() != 0;
1027  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1028}
1029
1030uint32_t ARMMCCodeEmitter::
1031getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1032                          SmallVectorImpl<MCFixup> &Fixups) const {
1033  // {9}      1 == imm8, 0 == Rm
1034  // {8}      isAdd
1035  // {7-4}    imm7_4/zero
1036  // {3-0}    imm3_0/Rm
1037  const MCOperand &MO = MI.getOperand(OpIdx);
1038  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1039  unsigned Imm = MO1.getImm();
1040  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1041  bool isImm = MO.getReg() == 0;
1042  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1043  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1044  if (!isImm)
1045    Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1046  return Imm8 | (isAdd << 8) | (isImm << 9);
1047}
1048
1049uint32_t ARMMCCodeEmitter::
1050getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1051                    SmallVectorImpl<MCFixup> &Fixups) const {
1052  // {13}     1 == imm8, 0 == Rm
1053  // {12-9}   Rn
1054  // {8}      isAdd
1055  // {7-4}    imm7_4/zero
1056  // {3-0}    imm3_0/Rm
1057  const MCOperand &MO = MI.getOperand(OpIdx);
1058  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1059  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1060
1061  // If The first operand isn't a register, we have a label reference.
1062  if (!MO.isReg()) {
1063    unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1064
1065    assert(MO.isExpr() && "Unexpected machine operand type!");
1066    const MCExpr *Expr = MO.getExpr();
1067    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1068    Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1069
1070    ++MCNumCPRelocations;
1071    return (Rn << 9) | (1 << 13);
1072  }
1073  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1074  unsigned Imm = MO2.getImm();
1075  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1076  bool isImm = MO1.getReg() == 0;
1077  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1078  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1079  if (!isImm)
1080    Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1081  return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1082}
1083
1084/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1085uint32_t ARMMCCodeEmitter::
1086getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1087                          SmallVectorImpl<MCFixup> &Fixups) const {
1088  // [SP, #imm]
1089  //   {7-0} = imm8
1090  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1091  assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1092         "Unexpected base register!");
1093
1094  // The immediate is already shifted for the implicit zeroes, so no change
1095  // here.
1096  return MO1.getImm() & 0xff;
1097}
1098
1099/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1100uint32_t ARMMCCodeEmitter::
1101getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1102                     SmallVectorImpl<MCFixup> &Fixups) const {
1103  // [Rn, #imm]
1104  //   {7-3} = imm5
1105  //   {2-0} = Rn
1106  const MCOperand &MO = MI.getOperand(OpIdx);
1107  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1108  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1109  unsigned Imm5 = MO1.getImm();
1110  return ((Imm5 & 0x1f) << 3) | Rn;
1111}
1112
1113/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1114uint32_t ARMMCCodeEmitter::
1115getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1116                     SmallVectorImpl<MCFixup> &Fixups) const {
1117  const MCOperand MO = MI.getOperand(OpIdx);
1118  if (MO.isExpr())
1119    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1120  return (MO.getImm() >> 2);
1121}
1122
1123/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1124uint32_t ARMMCCodeEmitter::
1125getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1126                    SmallVectorImpl<MCFixup> &Fixups) const {
1127  // {12-9} = reg
1128  // {8}    = (U)nsigned (add == '1', sub == '0')
1129  // {7-0}  = imm8
1130  unsigned Reg, Imm8;
1131  bool isAdd;
1132  // If The first operand isn't a register, we have a label reference.
1133  const MCOperand &MO = MI.getOperand(OpIdx);
1134  if (!MO.isReg()) {
1135    Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1136    Imm8 = 0;
1137    isAdd = false; // 'U' bit is handled as part of the fixup.
1138
1139    assert(MO.isExpr() && "Unexpected machine operand type!");
1140    const MCExpr *Expr = MO.getExpr();
1141    MCFixupKind Kind;
1142    if (isThumb2())
1143      Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1144    else
1145      Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1146    Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1147
1148    ++MCNumCPRelocations;
1149  } else {
1150    EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1151    isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1152  }
1153
1154  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1155  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1156  if (isAdd)
1157    Binary |= (1 << 8);
1158  Binary |= (Reg << 9);
1159  return Binary;
1160}
1161
1162unsigned ARMMCCodeEmitter::
1163getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1164                SmallVectorImpl<MCFixup> &Fixups) const {
1165  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1166  // shifted. The second is Rs, the amount to shift by, and the third specifies
1167  // the type of the shift.
1168  //
1169  // {3-0} = Rm.
1170  // {4}   = 1
1171  // {6-5} = type
1172  // {11-8} = Rs
1173  // {7}    = 0
1174
1175  const MCOperand &MO  = MI.getOperand(OpIdx);
1176  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1177  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1178  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1179
1180  // Encode Rm.
1181  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1182
1183  // Encode the shift opcode.
1184  unsigned SBits = 0;
1185  unsigned Rs = MO1.getReg();
1186  if (Rs) {
1187    // Set shift operand (bit[7:4]).
1188    // LSL - 0001
1189    // LSR - 0011
1190    // ASR - 0101
1191    // ROR - 0111
1192    switch (SOpc) {
1193    default: llvm_unreachable("Unknown shift opc!");
1194    case ARM_AM::lsl: SBits = 0x1; break;
1195    case ARM_AM::lsr: SBits = 0x3; break;
1196    case ARM_AM::asr: SBits = 0x5; break;
1197    case ARM_AM::ror: SBits = 0x7; break;
1198    }
1199  }
1200
1201  Binary |= SBits << 4;
1202
1203  // Encode the shift operation Rs.
1204  // Encode Rs bit[11:8].
1205  assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1206  return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1207}
1208
1209unsigned ARMMCCodeEmitter::
1210getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1211                SmallVectorImpl<MCFixup> &Fixups) const {
1212  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1213  // shifted. The second is the amount to shift by.
1214  //
1215  // {3-0} = Rm.
1216  // {4}   = 0
1217  // {6-5} = type
1218  // {11-7} = imm
1219
1220  const MCOperand &MO  = MI.getOperand(OpIdx);
1221  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1222  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1223
1224  // Encode Rm.
1225  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1226
1227  // Encode the shift opcode.
1228  unsigned SBits = 0;
1229
1230  // Set shift operand (bit[6:4]).
1231  // LSL - 000
1232  // LSR - 010
1233  // ASR - 100
1234  // ROR - 110
1235  // RRX - 110 and bit[11:8] clear.
1236  switch (SOpc) {
1237  default: llvm_unreachable("Unknown shift opc!");
1238  case ARM_AM::lsl: SBits = 0x0; break;
1239  case ARM_AM::lsr: SBits = 0x2; break;
1240  case ARM_AM::asr: SBits = 0x4; break;
1241  case ARM_AM::ror: SBits = 0x6; break;
1242  case ARM_AM::rrx:
1243    Binary |= 0x60;
1244    return Binary;
1245  }
1246
1247  // Encode shift_imm bit[11:7].
1248  Binary |= SBits << 4;
1249  unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1250  assert(Offset < 32 && "Offset must be in range 0-31!");
1251  return Binary | (Offset << 7);
1252}
1253
1254
1255unsigned ARMMCCodeEmitter::
1256getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1257                SmallVectorImpl<MCFixup> &Fixups) const {
1258  const MCOperand &MO1 = MI.getOperand(OpNum);
1259  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1260  const MCOperand &MO3 = MI.getOperand(OpNum+2);
1261
1262  // Encoded as [Rn, Rm, imm].
1263  // FIXME: Needs fixup support.
1264  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1265  Value <<= 4;
1266  Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1267  Value <<= 2;
1268  Value |= MO3.getImm();
1269
1270  return Value;
1271}
1272
1273unsigned ARMMCCodeEmitter::
1274getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1275                         SmallVectorImpl<MCFixup> &Fixups) const {
1276  const MCOperand &MO1 = MI.getOperand(OpNum);
1277  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1278
1279  // FIXME: Needs fixup support.
1280  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1281
1282  // Even though the immediate is 8 bits long, we need 9 bits in order
1283  // to represent the (inverse of the) sign bit.
1284  Value <<= 9;
1285  int32_t tmp = (int32_t)MO2.getImm();
1286  if (tmp < 0)
1287    tmp = abs(tmp);
1288  else
1289    Value |= 256; // Set the ADD bit
1290  Value |= tmp & 255;
1291  return Value;
1292}
1293
1294unsigned ARMMCCodeEmitter::
1295getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1296                         SmallVectorImpl<MCFixup> &Fixups) const {
1297  const MCOperand &MO1 = MI.getOperand(OpNum);
1298
1299  // FIXME: Needs fixup support.
1300  unsigned Value = 0;
1301  int32_t tmp = (int32_t)MO1.getImm();
1302  if (tmp < 0)
1303    tmp = abs(tmp);
1304  else
1305    Value |= 256; // Set the ADD bit
1306  Value |= tmp & 255;
1307  return Value;
1308}
1309
1310unsigned ARMMCCodeEmitter::
1311getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1312                         SmallVectorImpl<MCFixup> &Fixups) const {
1313  const MCOperand &MO1 = MI.getOperand(OpNum);
1314
1315  // FIXME: Needs fixup support.
1316  unsigned Value = 0;
1317  int32_t tmp = (int32_t)MO1.getImm();
1318  if (tmp < 0)
1319    tmp = abs(tmp);
1320  else
1321    Value |= 4096; // Set the ADD bit
1322  Value |= tmp & 4095;
1323  return Value;
1324}
1325
1326unsigned ARMMCCodeEmitter::
1327getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1328                SmallVectorImpl<MCFixup> &Fixups) const {
1329  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1330  // shifted. The second is the amount to shift by.
1331  //
1332  // {3-0} = Rm.
1333  // {4}   = 0
1334  // {6-5} = type
1335  // {11-7} = imm
1336
1337  const MCOperand &MO  = MI.getOperand(OpIdx);
1338  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1339  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1340
1341  // Encode Rm.
1342  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1343
1344  // Encode the shift opcode.
1345  unsigned SBits = 0;
1346  // Set shift operand (bit[6:4]).
1347  // LSL - 000
1348  // LSR - 010
1349  // ASR - 100
1350  // ROR - 110
1351  switch (SOpc) {
1352  default: llvm_unreachable("Unknown shift opc!");
1353  case ARM_AM::lsl: SBits = 0x0; break;
1354  case ARM_AM::lsr: SBits = 0x2; break;
1355  case ARM_AM::asr: SBits = 0x4; break;
1356  case ARM_AM::rrx: // FALLTHROUGH
1357  case ARM_AM::ror: SBits = 0x6; break;
1358  }
1359
1360  Binary |= SBits << 4;
1361  if (SOpc == ARM_AM::rrx)
1362    return Binary;
1363
1364  // Encode shift_imm bit[11:7].
1365  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1366}
1367
1368unsigned ARMMCCodeEmitter::
1369getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1370                               SmallVectorImpl<MCFixup> &Fixups) const {
1371  // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1372  // msb of the mask.
1373  const MCOperand &MO = MI.getOperand(Op);
1374  uint32_t v = ~MO.getImm();
1375  uint32_t lsb = countTrailingZeros(v);
1376  uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1377  assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1378  return lsb | (msb << 5);
1379}
1380
1381unsigned ARMMCCodeEmitter::
1382getRegisterListOpValue(const MCInst &MI, unsigned Op,
1383                       SmallVectorImpl<MCFixup> &Fixups) const {
1384  // VLDM/VSTM:
1385  //   {12-8} = Vd
1386  //   {7-0}  = Number of registers
1387  //
1388  // LDM/STM:
1389  //   {15-0}  = Bitfield of GPRs.
1390  unsigned Reg = MI.getOperand(Op).getReg();
1391  bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1392  bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1393
1394  unsigned Binary = 0;
1395
1396  if (SPRRegs || DPRRegs) {
1397    // VLDM/VSTM
1398    unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1399    unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1400    Binary |= (RegNo & 0x1f) << 8;
1401    if (SPRRegs)
1402      Binary |= NumRegs;
1403    else
1404      Binary |= NumRegs * 2;
1405  } else {
1406    for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1407      unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
1408      Binary |= 1 << RegNo;
1409    }
1410  }
1411
1412  return Binary;
1413}
1414
1415/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1416/// with the alignment operand.
1417unsigned ARMMCCodeEmitter::
1418getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1419                           SmallVectorImpl<MCFixup> &Fixups) const {
1420  const MCOperand &Reg = MI.getOperand(Op);
1421  const MCOperand &Imm = MI.getOperand(Op + 1);
1422
1423  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1424  unsigned Align = 0;
1425
1426  switch (Imm.getImm()) {
1427  default: break;
1428  case 2:
1429  case 4:
1430  case 8:  Align = 0x01; break;
1431  case 16: Align = 0x02; break;
1432  case 32: Align = 0x03; break;
1433  }
1434
1435  return RegNo | (Align << 4);
1436}
1437
1438/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1439/// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1440unsigned ARMMCCodeEmitter::
1441getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1442                                    SmallVectorImpl<MCFixup> &Fixups) const {
1443  const MCOperand &Reg = MI.getOperand(Op);
1444  const MCOperand &Imm = MI.getOperand(Op + 1);
1445
1446  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1447  unsigned Align = 0;
1448
1449  switch (Imm.getImm()) {
1450  default: break;
1451  case 8:
1452  case 16:
1453  case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1454  case 2: Align = 0x00; break;
1455  case 4: Align = 0x03; break;
1456  }
1457
1458  return RegNo | (Align << 4);
1459}
1460
1461
1462/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1463/// alignment operand for use in VLD-dup instructions.  This is the same as
1464/// getAddrMode6AddressOpValue except for the alignment encoding, which is
1465/// different for VLD4-dup.
1466unsigned ARMMCCodeEmitter::
1467getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1468                              SmallVectorImpl<MCFixup> &Fixups) const {
1469  const MCOperand &Reg = MI.getOperand(Op);
1470  const MCOperand &Imm = MI.getOperand(Op + 1);
1471
1472  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1473  unsigned Align = 0;
1474
1475  switch (Imm.getImm()) {
1476  default: break;
1477  case 2:
1478  case 4:
1479  case 8:  Align = 0x01; break;
1480  case 16: Align = 0x03; break;
1481  }
1482
1483  return RegNo | (Align << 4);
1484}
1485
1486unsigned ARMMCCodeEmitter::
1487getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1488                          SmallVectorImpl<MCFixup> &Fixups) const {
1489  const MCOperand &MO = MI.getOperand(Op);
1490  if (MO.getReg() == 0) return 0x0D;
1491  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1492}
1493
1494unsigned ARMMCCodeEmitter::
1495getShiftRight8Imm(const MCInst &MI, unsigned Op,
1496                  SmallVectorImpl<MCFixup> &Fixups) const {
1497  return 8 - MI.getOperand(Op).getImm();
1498}
1499
1500unsigned ARMMCCodeEmitter::
1501getShiftRight16Imm(const MCInst &MI, unsigned Op,
1502                   SmallVectorImpl<MCFixup> &Fixups) const {
1503  return 16 - MI.getOperand(Op).getImm();
1504}
1505
1506unsigned ARMMCCodeEmitter::
1507getShiftRight32Imm(const MCInst &MI, unsigned Op,
1508                   SmallVectorImpl<MCFixup> &Fixups) const {
1509  return 32 - MI.getOperand(Op).getImm();
1510}
1511
1512unsigned ARMMCCodeEmitter::
1513getShiftRight64Imm(const MCInst &MI, unsigned Op,
1514                   SmallVectorImpl<MCFixup> &Fixups) const {
1515  return 64 - MI.getOperand(Op).getImm();
1516}
1517
1518void ARMMCCodeEmitter::
1519EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1520                  SmallVectorImpl<MCFixup> &Fixups) const {
1521  // Pseudo instructions don't get encoded.
1522  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1523  uint64_t TSFlags = Desc.TSFlags;
1524  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1525    return;
1526
1527  int Size;
1528  if (Desc.getSize() == 2 || Desc.getSize() == 4)
1529    Size = Desc.getSize();
1530  else
1531    llvm_unreachable("Unexpected instruction size!");
1532
1533  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1534  // Thumb 32-bit wide instructions need to emit the high order halfword
1535  // first.
1536  if (isThumb() && Size == 4) {
1537    EmitConstant(Binary >> 16, 2, OS);
1538    EmitConstant(Binary & 0xffff, 2, OS);
1539  } else
1540    EmitConstant(Binary, Size, OS);
1541  ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1542}
1543
1544#include "ARMGenMCCodeEmitter.inc"
1545