ARMMCCodeEmitter.cpp revision 16578b50889329eb62774148091ba0f38b681a09 
1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARMMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "MCTargetDesc/ARMFixupKinds.h"
18#include "MCTargetDesc/ARMMCExpr.h"
19#include "MCTargetDesc/ARMMCTargetDesc.h"
20#include "llvm/MC/MCCodeEmitter.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/Support/raw_ostream.h"
29
30using namespace llvm;
31
32STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
34
35namespace {
36class ARMMCCodeEmitter : public MCCodeEmitter {
37  ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38  void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39  const MCInstrInfo &MCII;
40  const MCSubtargetInfo &STI;
41
42public:
43  ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
44                   MCContext &ctx)
45    : MCII(mcii), STI(sti) {
46  }
47
48  ~ARMMCCodeEmitter() {}
49
50  bool isThumb() const {
51    // FIXME: Can tablegen auto-generate this?
52    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
53  }
54  bool isThumb2() const {
55    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
56  }
57  bool isTargetDarwin() const {
58    Triple TT(STI.getTargetTriple());
59    Triple::OSType OS = TT.getOS();
60    return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
61  }
62
63  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
64
65  // getBinaryCodeForInstr - TableGen'erated function for getting the
66  // binary encoding for an instruction.
67  unsigned getBinaryCodeForInstr(const MCInst &MI,
68                                 SmallVectorImpl<MCFixup> &Fixups) const;
69
70  /// getMachineOpValue - Return binary encoding of operand. If the machine
71  /// operand requires relocation, record the relocation and return zero.
72  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73                             SmallVectorImpl<MCFixup> &Fixups) const;
74
75  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76  /// the specified operand. This is used for operands with :lower16: and
77  /// :upper16: prefixes.
78  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79                               SmallVectorImpl<MCFixup> &Fixups) const;
80
81  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82                              unsigned &Reg, unsigned &Imm,
83                              SmallVectorImpl<MCFixup> &Fixups) const;
84
85  /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
86  /// BL branch target.
87  uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88                                   SmallVectorImpl<MCFixup> &Fixups) const;
89
90  /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91  /// BLX branch target.
92  uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93                                    SmallVectorImpl<MCFixup> &Fixups) const;
94
95  /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96  uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97                                   SmallVectorImpl<MCFixup> &Fixups) const;
98
99  /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100  uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101                                    SmallVectorImpl<MCFixup> &Fixups) const;
102
103  /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104  uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105                                   SmallVectorImpl<MCFixup> &Fixups) const;
106
107  /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
108  /// branch target.
109  uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110                                  SmallVectorImpl<MCFixup> &Fixups) const;
111
112  /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113  /// immediate Thumb2 direct branch target.
114  uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115                                  SmallVectorImpl<MCFixup> &Fixups) const;
116
117  /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
118  /// branch target.
119  uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120                                     SmallVectorImpl<MCFixup> &Fixups) const;
121
122  /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
123  /// ADR label target.
124  uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
125                              SmallVectorImpl<MCFixup> &Fixups) const;
126  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
127                              SmallVectorImpl<MCFixup> &Fixups) const;
128  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129                              SmallVectorImpl<MCFixup> &Fixups) const;
130
131
132  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
133  /// operand.
134  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
135                                   SmallVectorImpl<MCFixup> &Fixups) const;
136
137  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
138  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
139                                         SmallVectorImpl<MCFixup> &Fixups)const;
140
141  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
142  /// operand.
143  uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
144                                   SmallVectorImpl<MCFixup> &Fixups) const;
145
146
147  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
148  /// operand as needed by load/store instructions.
149  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
150                               SmallVectorImpl<MCFixup> &Fixups) const;
151
152  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
153  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
154                               SmallVectorImpl<MCFixup> &Fixups) const {
155    ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
156    switch (Mode) {
157    default: assert(0 && "Unknown addressing sub-mode!");
158    case ARM_AM::da: return 0;
159    case ARM_AM::ia: return 1;
160    case ARM_AM::db: return 2;
161    case ARM_AM::ib: return 3;
162    }
163  }
164  /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
165  ///
166  unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
167    switch (ShOpc) {
168    default: llvm_unreachable("Unknown shift opc!");
169    case ARM_AM::no_shift:
170    case ARM_AM::lsl: return 0;
171    case ARM_AM::lsr: return 1;
172    case ARM_AM::asr: return 2;
173    case ARM_AM::ror:
174    case ARM_AM::rrx: return 3;
175    }
176    return 0;
177  }
178
179  /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
180  uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
181                               SmallVectorImpl<MCFixup> &Fixups) const;
182
183  /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
184  uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
185                                     SmallVectorImpl<MCFixup> &Fixups) const;
186
187  /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
188  uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
189                                SmallVectorImpl<MCFixup> &Fixups) const;
190
191  /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
192  uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
193                                     SmallVectorImpl<MCFixup> &Fixups) const;
194
195  /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
196  uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
197                               SmallVectorImpl<MCFixup> &Fixups) const;
198
199  /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
200  /// operand.
201  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
202                                     SmallVectorImpl<MCFixup> &Fixups) const;
203
204  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
205  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
206                                SmallVectorImpl<MCFixup> &Fixups) const;
207
208  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
209  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
210                                SmallVectorImpl<MCFixup> &Fixups) const;
211
212  /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
213  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
214                               SmallVectorImpl<MCFixup> &Fixups) const;
215
216  /// getCCOutOpValue - Return encoding of the 's' bit.
217  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
218                           SmallVectorImpl<MCFixup> &Fixups) const {
219    // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
220    // '1' respectively.
221    return MI.getOperand(Op).getReg() == ARM::CPSR;
222  }
223
224  /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
225  unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
226                           SmallVectorImpl<MCFixup> &Fixups) const {
227    unsigned SoImm = MI.getOperand(Op).getImm();
228    int SoImmVal = ARM_AM::getSOImmVal(SoImm);
229    assert(SoImmVal != -1 && "Not a valid so_imm value!");
230
231    // Encode rotate_imm.
232    unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
233      << ARMII::SoRotImmShift;
234
235    // Encode immed_8.
236    Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
237    return Binary;
238  }
239
240  /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
241  unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
242                           SmallVectorImpl<MCFixup> &Fixups) const {
243    unsigned SoImm = MI.getOperand(Op).getImm();
244    unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
245    assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
246    return Encoded;
247  }
248
249  unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
250    SmallVectorImpl<MCFixup> &Fixups) const;
251  unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
252    SmallVectorImpl<MCFixup> &Fixups) const;
253  unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
254    SmallVectorImpl<MCFixup> &Fixups) const;
255  unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
256    SmallVectorImpl<MCFixup> &Fixups) const;
257
258  /// getSORegOpValue - Return an encoded so_reg shifted register value.
259  unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
260                           SmallVectorImpl<MCFixup> &Fixups) const;
261  unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
262                           SmallVectorImpl<MCFixup> &Fixups) const;
263  unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
264                             SmallVectorImpl<MCFixup> &Fixups) const;
265
266  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
267                                   SmallVectorImpl<MCFixup> &Fixups) const {
268    return 64 - MI.getOperand(Op).getImm();
269  }
270
271  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
272                                      SmallVectorImpl<MCFixup> &Fixups) const;
273
274  unsigned getMsbOpValue(const MCInst &MI, unsigned Op,
275                         SmallVectorImpl<MCFixup> &Fixups) const;
276
277  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
278                                  SmallVectorImpl<MCFixup> &Fixups) const;
279  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
280                                      SmallVectorImpl<MCFixup> &Fixups) const;
281  unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
282                                        SmallVectorImpl<MCFixup> &Fixups) const;
283  unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
284                                        SmallVectorImpl<MCFixup> &Fixups) const;
285  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
286                                     SmallVectorImpl<MCFixup> &Fixups) const;
287
288  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
289                             SmallVectorImpl<MCFixup> &Fixups) const;
290  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
291                              SmallVectorImpl<MCFixup> &Fixups) const;
292  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
293                              SmallVectorImpl<MCFixup> &Fixups) const;
294  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
295                              SmallVectorImpl<MCFixup> &Fixups) const;
296
297  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
298                                      unsigned EncodedValue) const;
299  unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
300                                          unsigned EncodedValue) const;
301  unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
302                                    unsigned EncodedValue) const;
303
304  unsigned VFPThumb2PostEncoder(const MCInst &MI,
305                                unsigned EncodedValue) const;
306
307  void EmitByte(unsigned char C, raw_ostream &OS) const {
308    OS << (char)C;
309  }
310
311  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
312    // Output the constant in little endian byte order.
313    for (unsigned i = 0; i != Size; ++i) {
314      EmitByte(Val & 255, OS);
315      Val >>= 8;
316    }
317  }
318
319  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
320                         SmallVectorImpl<MCFixup> &Fixups) const;
321};
322
323} // end anonymous namespace
324
325MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
326                                            const MCSubtargetInfo &STI,
327                                            MCContext &Ctx) {
328  return new ARMMCCodeEmitter(MCII, STI, Ctx);
329}
330
331/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
332/// instructions, and rewrite them to their Thumb2 form if we are currently in
333/// Thumb2 mode.
334unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
335                                                 unsigned EncodedValue) const {
336  if (isThumb2()) {
337    // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
338    // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
339    // set to 1111.
340    unsigned Bit24 = EncodedValue & 0x01000000;
341    unsigned Bit28 = Bit24 << 4;
342    EncodedValue &= 0xEFFFFFFF;
343    EncodedValue |= Bit28;
344    EncodedValue |= 0x0F000000;
345  }
346
347  return EncodedValue;
348}
349
350/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
351/// instructions, and rewrite them to their Thumb2 form if we are currently in
352/// Thumb2 mode.
353unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
354                                                 unsigned EncodedValue) const {
355  if (isThumb2()) {
356    EncodedValue &= 0xF0FFFFFF;
357    EncodedValue |= 0x09000000;
358  }
359
360  return EncodedValue;
361}
362
363/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
364/// instructions, and rewrite them to their Thumb2 form if we are currently in
365/// Thumb2 mode.
366unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
367                                                 unsigned EncodedValue) const {
368  if (isThumb2()) {
369    EncodedValue &= 0x00FFFFFF;
370    EncodedValue |= 0xEE000000;
371  }
372
373  return EncodedValue;
374}
375
376/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
377/// them to their Thumb2 form if we are currently in Thumb2 mode.
378unsigned ARMMCCodeEmitter::
379VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
380  if (isThumb2()) {
381    EncodedValue &= 0x0FFFFFFF;
382    EncodedValue |= 0xE0000000;
383  }
384  return EncodedValue;
385}
386
387/// getMachineOpValue - Return binary encoding of operand. If the machine
388/// operand requires relocation, record the relocation and return zero.
389unsigned ARMMCCodeEmitter::
390getMachineOpValue(const MCInst &MI, const MCOperand &MO,
391                  SmallVectorImpl<MCFixup> &Fixups) const {
392  if (MO.isReg()) {
393    unsigned Reg = MO.getReg();
394    unsigned RegNo = getARMRegisterNumbering(Reg);
395
396    // Q registers are encoded as 2x their register number.
397    switch (Reg) {
398    default:
399      return RegNo;
400    case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
401    case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
402    case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
403    case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
404      return 2 * RegNo;
405    }
406  } else if (MO.isImm()) {
407    return static_cast<unsigned>(MO.getImm());
408  } else if (MO.isFPImm()) {
409    return static_cast<unsigned>(APFloat(MO.getFPImm())
410                     .bitcastToAPInt().getHiBits(32).getLimitedValue());
411  }
412
413  llvm_unreachable("Unable to encode MCOperand!");
414  return 0;
415}
416
417/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
418bool ARMMCCodeEmitter::
419EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
420                       unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
421  const MCOperand &MO  = MI.getOperand(OpIdx);
422  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
423
424  Reg = getARMRegisterNumbering(MO.getReg());
425
426  int32_t SImm = MO1.getImm();
427  bool isAdd = true;
428
429  // Special value for #-0
430  if (SImm == INT32_MIN)
431    SImm = 0;
432
433  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
434  if (SImm < 0) {
435    SImm = -SImm;
436    isAdd = false;
437  }
438
439  Imm = SImm;
440  return isAdd;
441}
442
443/// getBranchTargetOpValue - Helper function to get the branch target operand,
444/// which is either an immediate or requires a fixup.
445static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
446                                       unsigned FixupKind,
447                                       SmallVectorImpl<MCFixup> &Fixups) {
448  const MCOperand &MO = MI.getOperand(OpIdx);
449
450  // If the destination is an immediate, we have nothing to do.
451  if (MO.isImm()) return MO.getImm();
452  assert(MO.isExpr() && "Unexpected branch target type!");
453  const MCExpr *Expr = MO.getExpr();
454  MCFixupKind Kind = MCFixupKind(FixupKind);
455  Fixups.push_back(MCFixup::Create(0, Expr, Kind));
456
457  // All of the information is in the fixup.
458  return 0;
459}
460
461/// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
462uint32_t ARMMCCodeEmitter::
463getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
464                        SmallVectorImpl<MCFixup> &Fixups) const {
465  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
466}
467
468/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
469/// BLX branch target.
470uint32_t ARMMCCodeEmitter::
471getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
472                         SmallVectorImpl<MCFixup> &Fixups) const {
473  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
474}
475
476/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
477uint32_t ARMMCCodeEmitter::
478getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
479                        SmallVectorImpl<MCFixup> &Fixups) const {
480  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
481}
482
483/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
484uint32_t ARMMCCodeEmitter::
485getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
486                         SmallVectorImpl<MCFixup> &Fixups) const {
487  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
488}
489
490/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
491uint32_t ARMMCCodeEmitter::
492getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
493                        SmallVectorImpl<MCFixup> &Fixups) const {
494  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
495}
496
497/// Return true if this branch has a non-always predication
498static bool HasConditionalBranch(const MCInst &MI) {
499  int NumOp = MI.getNumOperands();
500  if (NumOp >= 2) {
501    for (int i = 0; i < NumOp-1; ++i) {
502      const MCOperand &MCOp1 = MI.getOperand(i);
503      const MCOperand &MCOp2 = MI.getOperand(i + 1);
504      if (MCOp1.isImm() && MCOp2.isReg() &&
505          (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
506        if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
507          return true;
508      }
509    }
510  }
511  return false;
512}
513
514/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
515/// target.
516uint32_t ARMMCCodeEmitter::
517getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
518                       SmallVectorImpl<MCFixup> &Fixups) const {
519  // FIXME: This really, really shouldn't use TargetMachine. We don't want
520  // coupling between MC and TM anywhere we can help it.
521  if (isThumb2())
522    return
523      ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
524  return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
525}
526
527/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
528/// target.
529uint32_t ARMMCCodeEmitter::
530getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
531                          SmallVectorImpl<MCFixup> &Fixups) const {
532  if (HasConditionalBranch(MI))
533    return ::getBranchTargetOpValue(MI, OpIdx,
534                                    ARM::fixup_arm_condbranch, Fixups);
535  return ::getBranchTargetOpValue(MI, OpIdx,
536                                  ARM::fixup_arm_uncondbranch, Fixups);
537}
538
539
540
541
542/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
543/// immediate branch target.
544uint32_t ARMMCCodeEmitter::
545getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
546                       SmallVectorImpl<MCFixup> &Fixups) const {
547  unsigned Val =
548    ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
549  bool I  = (Val & 0x800000);
550  bool J1 = (Val & 0x400000);
551  bool J2 = (Val & 0x200000);
552  if (I ^ J1)
553    Val &= ~0x400000;
554  else
555    Val |= 0x400000;
556
557  if (I ^ J2)
558    Val &= ~0x200000;
559  else
560    Val |= 0x200000;
561
562  return Val;
563}
564
565/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
566/// target.
567uint32_t ARMMCCodeEmitter::
568getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
569                   SmallVectorImpl<MCFixup> &Fixups) const {
570  assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
571  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
572                                  Fixups);
573}
574
575/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
576/// target.
577uint32_t ARMMCCodeEmitter::
578getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
579                   SmallVectorImpl<MCFixup> &Fixups) const {
580  assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
581  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
582                                  Fixups);
583}
584
585/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
586/// target.
587uint32_t ARMMCCodeEmitter::
588getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
589                   SmallVectorImpl<MCFixup> &Fixups) const {
590  assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
591  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
592                                  Fixups);
593}
594
595/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
596/// operand.
597uint32_t ARMMCCodeEmitter::
598getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
599                              SmallVectorImpl<MCFixup> &) const {
600  // [Rn, Rm]
601  //   {5-3} = Rm
602  //   {2-0} = Rn
603  const MCOperand &MO1 = MI.getOperand(OpIdx);
604  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
605  unsigned Rn = getARMRegisterNumbering(MO1.getReg());
606  unsigned Rm = getARMRegisterNumbering(MO2.getReg());
607  return (Rm << 3) | Rn;
608}
609
610/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
611uint32_t ARMMCCodeEmitter::
612getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
613                        SmallVectorImpl<MCFixup> &Fixups) const {
614  // {17-13} = reg
615  // {12}    = (U)nsigned (add == '1', sub == '0')
616  // {11-0}  = imm12
617  unsigned Reg, Imm12;
618  bool isAdd = true;
619  // If The first operand isn't a register, we have a label reference.
620  const MCOperand &MO = MI.getOperand(OpIdx);
621  if (!MO.isReg()) {
622    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
623    Imm12 = 0;
624    isAdd = false ; // 'U' bit is set as part of the fixup.
625
626    assert(MO.isExpr() && "Unexpected machine operand type!");
627    const MCExpr *Expr = MO.getExpr();
628
629    MCFixupKind Kind;
630    if (isThumb2())
631      Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
632    else
633      Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
634    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
635
636    ++MCNumCPRelocations;
637  } else
638    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
639
640  uint32_t Binary = Imm12 & 0xfff;
641  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
642  if (isAdd)
643    Binary |= (1 << 12);
644  Binary |= (Reg << 13);
645  return Binary;
646}
647
648/// getT2AddrModeImm8s4OpValue - Return encoding info for
649/// 'reg +/- imm8<<2' operand.
650uint32_t ARMMCCodeEmitter::
651getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
652                        SmallVectorImpl<MCFixup> &Fixups) const {
653  // {12-9} = reg
654  // {8}    = (U)nsigned (add == '1', sub == '0')
655  // {7-0}  = imm8
656  unsigned Reg, Imm8;
657  bool isAdd = true;
658  // If The first operand isn't a register, we have a label reference.
659  const MCOperand &MO = MI.getOperand(OpIdx);
660  if (!MO.isReg()) {
661    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
662    Imm8 = 0;
663    isAdd = false ; // 'U' bit is set as part of the fixup.
664
665    assert(MO.isExpr() && "Unexpected machine operand type!");
666    const MCExpr *Expr = MO.getExpr();
667    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
668    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
669
670    ++MCNumCPRelocations;
671  } else
672    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
673
674  uint32_t Binary = (Imm8 >> 2) & 0xff;
675  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
676  if (isAdd)
677    Binary |= (1 << 8);
678  Binary |= (Reg << 9);
679  return Binary;
680}
681
682// FIXME: This routine assumes that a binary
683// expression will always result in a PCRel expression
684// In reality, its only true if one or more subexpressions
685// is itself a PCRel (i.e. "." in asm or some other pcrel construct)
686// but this is good enough for now.
687static bool EvaluateAsPCRel(const MCExpr *Expr) {
688  switch (Expr->getKind()) {
689  default: assert(0 && "Unexpected expression type");
690  case MCExpr::SymbolRef: return false;
691  case MCExpr::Binary: return true;
692  }
693}
694
695uint32_t
696ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
697                                      SmallVectorImpl<MCFixup> &Fixups) const {
698  // {20-16} = imm{15-12}
699  // {11-0}  = imm{11-0}
700  const MCOperand &MO = MI.getOperand(OpIdx);
701  if (MO.isImm())
702    // Hi / lo 16 bits already extracted during earlier passes.
703    return static_cast<unsigned>(MO.getImm());
704
705  // Handle :upper16: and :lower16: assembly prefixes.
706  const MCExpr *E = MO.getExpr();
707  if (E->getKind() == MCExpr::Target) {
708    const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
709    E = ARM16Expr->getSubExpr();
710
711    MCFixupKind Kind;
712    switch (ARM16Expr->getKind()) {
713    default: assert(0 && "Unsupported ARMFixup");
714    case ARMMCExpr::VK_ARM_HI16:
715      if (!isTargetDarwin() && EvaluateAsPCRel(E))
716        Kind = MCFixupKind(isThumb2()
717                           ? ARM::fixup_t2_movt_hi16_pcrel
718                           : ARM::fixup_arm_movt_hi16_pcrel);
719      else
720        Kind = MCFixupKind(isThumb2()
721                           ? ARM::fixup_t2_movt_hi16
722                           : ARM::fixup_arm_movt_hi16);
723      break;
724    case ARMMCExpr::VK_ARM_LO16:
725      if (!isTargetDarwin() && EvaluateAsPCRel(E))
726        Kind = MCFixupKind(isThumb2()
727                           ? ARM::fixup_t2_movw_lo16_pcrel
728                           : ARM::fixup_arm_movw_lo16_pcrel);
729      else
730        Kind = MCFixupKind(isThumb2()
731                           ? ARM::fixup_t2_movw_lo16
732                           : ARM::fixup_arm_movw_lo16);
733      break;
734    }
735    Fixups.push_back(MCFixup::Create(0, E, Kind));
736    return 0;
737  };
738
739  llvm_unreachable("Unsupported MCExpr type in MCOperand!");
740  return 0;
741}
742
743uint32_t ARMMCCodeEmitter::
744getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
745                    SmallVectorImpl<MCFixup> &Fixups) const {
746  const MCOperand &MO = MI.getOperand(OpIdx);
747  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
748  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
749  unsigned Rn = getARMRegisterNumbering(MO.getReg());
750  unsigned Rm = getARMRegisterNumbering(MO1.getReg());
751  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
752  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
753  ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
754  unsigned SBits = getShiftOp(ShOp);
755
756  // {16-13} = Rn
757  // {12}    = isAdd
758  // {11-0}  = shifter
759  //  {3-0}  = Rm
760  //  {4}    = 0
761  //  {6-5}  = type
762  //  {11-7} = imm
763  uint32_t Binary = Rm;
764  Binary |= Rn << 13;
765  Binary |= SBits << 5;
766  Binary |= ShImm << 7;
767  if (isAdd)
768    Binary |= 1 << 12;
769  return Binary;
770}
771
772uint32_t ARMMCCodeEmitter::
773getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
774                    SmallVectorImpl<MCFixup> &Fixups) const {
775  // {17-14}  Rn
776  // {13}     1 == imm12, 0 == Rm
777  // {12}     isAdd
778  // {11-0}   imm12/Rm
779  const MCOperand &MO = MI.getOperand(OpIdx);
780  unsigned Rn = getARMRegisterNumbering(MO.getReg());
781  uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
782  Binary |= Rn << 14;
783  return Binary;
784}
785
786uint32_t ARMMCCodeEmitter::
787getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
788                          SmallVectorImpl<MCFixup> &Fixups) const {
789  // {13}     1 == imm12, 0 == Rm
790  // {12}     isAdd
791  // {11-0}   imm12/Rm
792  const MCOperand &MO = MI.getOperand(OpIdx);
793  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
794  unsigned Imm = MO1.getImm();
795  bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
796  bool isReg = MO.getReg() != 0;
797  uint32_t Binary = ARM_AM::getAM2Offset(Imm);
798  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
799  if (isReg) {
800    ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
801    Binary <<= 7;                    // Shift amount is bits [11:7]
802    Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
803    Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
804  }
805  return Binary | (isAdd << 12) | (isReg << 13);
806}
807
808uint32_t ARMMCCodeEmitter::
809getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
810                     SmallVectorImpl<MCFixup> &Fixups) const {
811  // {4}      isAdd
812  // {3-0}    Rm
813  const MCOperand &MO = MI.getOperand(OpIdx);
814  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
815  bool isAdd = MO1.getImm() != 0;
816  return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
817}
818
819uint32_t ARMMCCodeEmitter::
820getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
821                          SmallVectorImpl<MCFixup> &Fixups) const {
822  // {9}      1 == imm8, 0 == Rm
823  // {8}      isAdd
824  // {7-4}    imm7_4/zero
825  // {3-0}    imm3_0/Rm
826  const MCOperand &MO = MI.getOperand(OpIdx);
827  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
828  unsigned Imm = MO1.getImm();
829  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
830  bool isImm = MO.getReg() == 0;
831  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
832  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
833  if (!isImm)
834    Imm8 = getARMRegisterNumbering(MO.getReg());
835  return Imm8 | (isAdd << 8) | (isImm << 9);
836}
837
838uint32_t ARMMCCodeEmitter::
839getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
840                    SmallVectorImpl<MCFixup> &Fixups) const {
841  // {13}     1 == imm8, 0 == Rm
842  // {12-9}   Rn
843  // {8}      isAdd
844  // {7-4}    imm7_4/zero
845  // {3-0}    imm3_0/Rm
846  const MCOperand &MO = MI.getOperand(OpIdx);
847  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
848  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
849  unsigned Rn = getARMRegisterNumbering(MO.getReg());
850  unsigned Imm = MO2.getImm();
851  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
852  bool isImm = MO1.getReg() == 0;
853  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
854  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
855  if (!isImm)
856    Imm8 = getARMRegisterNumbering(MO1.getReg());
857  return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
858}
859
860/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
861uint32_t ARMMCCodeEmitter::
862getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
863                          SmallVectorImpl<MCFixup> &Fixups) const {
864  // [SP, #imm]
865  //   {7-0} = imm8
866  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
867  assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
868         "Unexpected base register!");
869
870  // The immediate is already shifted for the implicit zeroes, so no change
871  // here.
872  return MO1.getImm() & 0xff;
873}
874
875/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
876uint32_t ARMMCCodeEmitter::
877getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
878                     SmallVectorImpl<MCFixup> &Fixups) const {
879  // [Rn, #imm]
880  //   {7-3} = imm5
881  //   {2-0} = Rn
882  const MCOperand &MO = MI.getOperand(OpIdx);
883  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
884  unsigned Rn = getARMRegisterNumbering(MO.getReg());
885  unsigned Imm5 = MO1.getImm();
886  return ((Imm5 & 0x1f) << 3) | Rn;
887}
888
889/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
890uint32_t ARMMCCodeEmitter::
891getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
892                     SmallVectorImpl<MCFixup> &Fixups) const {
893  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
894}
895
896/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
897uint32_t ARMMCCodeEmitter::
898getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
899                    SmallVectorImpl<MCFixup> &Fixups) const {
900  // {12-9} = reg
901  // {8}    = (U)nsigned (add == '1', sub == '0')
902  // {7-0}  = imm8
903  unsigned Reg, Imm8;
904  bool isAdd;
905  // If The first operand isn't a register, we have a label reference.
906  const MCOperand &MO = MI.getOperand(OpIdx);
907  if (!MO.isReg()) {
908    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
909    Imm8 = 0;
910    isAdd = false; // 'U' bit is handled as part of the fixup.
911
912    assert(MO.isExpr() && "Unexpected machine operand type!");
913    const MCExpr *Expr = MO.getExpr();
914    MCFixupKind Kind;
915    if (isThumb2())
916      Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
917    else
918      Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
919    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
920
921    ++MCNumCPRelocations;
922  } else {
923    EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
924    isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
925  }
926
927  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
928  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
929  if (isAdd)
930    Binary |= (1 << 8);
931  Binary |= (Reg << 9);
932  return Binary;
933}
934
935unsigned ARMMCCodeEmitter::
936getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
937                SmallVectorImpl<MCFixup> &Fixups) const {
938  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
939  // shifted. The second is Rs, the amount to shift by, and the third specifies
940  // the type of the shift.
941  //
942  // {3-0} = Rm.
943  // {4}   = 1
944  // {6-5} = type
945  // {11-8} = Rs
946  // {7}    = 0
947
948  const MCOperand &MO  = MI.getOperand(OpIdx);
949  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
950  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
951  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
952
953  // Encode Rm.
954  unsigned Binary = getARMRegisterNumbering(MO.getReg());
955
956  // Encode the shift opcode.
957  unsigned SBits = 0;
958  unsigned Rs = MO1.getReg();
959  if (Rs) {
960    // Set shift operand (bit[7:4]).
961    // LSL - 0001
962    // LSR - 0011
963    // ASR - 0101
964    // ROR - 0111
965    switch (SOpc) {
966    default: llvm_unreachable("Unknown shift opc!");
967    case ARM_AM::lsl: SBits = 0x1; break;
968    case ARM_AM::lsr: SBits = 0x3; break;
969    case ARM_AM::asr: SBits = 0x5; break;
970    case ARM_AM::ror: SBits = 0x7; break;
971    }
972  }
973
974  Binary |= SBits << 4;
975
976  // Encode the shift operation Rs.
977  // Encode Rs bit[11:8].
978  assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
979  return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
980}
981
982unsigned ARMMCCodeEmitter::
983getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
984                SmallVectorImpl<MCFixup> &Fixups) const {
985  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
986  // shifted. The second is the amount to shift by.
987  //
988  // {3-0} = Rm.
989  // {4}   = 0
990  // {6-5} = type
991  // {11-7} = imm
992
993  const MCOperand &MO  = MI.getOperand(OpIdx);
994  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
995  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
996
997  // Encode Rm.
998  unsigned Binary = getARMRegisterNumbering(MO.getReg());
999
1000  // Encode the shift opcode.
1001  unsigned SBits = 0;
1002
1003  // Set shift operand (bit[6:4]).
1004  // LSL - 000
1005  // LSR - 010
1006  // ASR - 100
1007  // ROR - 110
1008  // RRX - 110 and bit[11:8] clear.
1009  switch (SOpc) {
1010  default: llvm_unreachable("Unknown shift opc!");
1011  case ARM_AM::lsl: SBits = 0x0; break;
1012  case ARM_AM::lsr: SBits = 0x2; break;
1013  case ARM_AM::asr: SBits = 0x4; break;
1014  case ARM_AM::ror: SBits = 0x6; break;
1015  case ARM_AM::rrx:
1016    Binary |= 0x60;
1017    return Binary;
1018  }
1019
1020  // Encode shift_imm bit[11:7].
1021  Binary |= SBits << 4;
1022  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1023}
1024
1025
1026unsigned ARMMCCodeEmitter::
1027getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1028                SmallVectorImpl<MCFixup> &Fixups) const {
1029  const MCOperand &MO1 = MI.getOperand(OpNum);
1030  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1031  const MCOperand &MO3 = MI.getOperand(OpNum+2);
1032
1033  // Encoded as [Rn, Rm, imm].
1034  // FIXME: Needs fixup support.
1035  unsigned Value = getARMRegisterNumbering(MO1.getReg());
1036  Value <<= 4;
1037  Value |= getARMRegisterNumbering(MO2.getReg());
1038  Value <<= 2;
1039  Value |= MO3.getImm();
1040
1041  return Value;
1042}
1043
1044unsigned ARMMCCodeEmitter::
1045getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1046                         SmallVectorImpl<MCFixup> &Fixups) const {
1047  const MCOperand &MO1 = MI.getOperand(OpNum);
1048  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1049
1050  // FIXME: Needs fixup support.
1051  unsigned Value = getARMRegisterNumbering(MO1.getReg());
1052
1053  // Even though the immediate is 8 bits long, we need 9 bits in order
1054  // to represent the (inverse of the) sign bit.
1055  Value <<= 9;
1056  int32_t tmp = (int32_t)MO2.getImm();
1057  if (tmp < 0)
1058    tmp = abs(tmp);
1059  else
1060    Value |= 256; // Set the ADD bit
1061  Value |= tmp & 255;
1062  return Value;
1063}
1064
1065unsigned ARMMCCodeEmitter::
1066getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1067                         SmallVectorImpl<MCFixup> &Fixups) const {
1068  const MCOperand &MO1 = MI.getOperand(OpNum);
1069
1070  // FIXME: Needs fixup support.
1071  unsigned Value = 0;
1072  int32_t tmp = (int32_t)MO1.getImm();
1073  if (tmp < 0)
1074    tmp = abs(tmp);
1075  else
1076    Value |= 256; // Set the ADD bit
1077  Value |= tmp & 255;
1078  return Value;
1079}
1080
1081unsigned ARMMCCodeEmitter::
1082getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1083                         SmallVectorImpl<MCFixup> &Fixups) const {
1084  const MCOperand &MO1 = MI.getOperand(OpNum);
1085
1086  // FIXME: Needs fixup support.
1087  unsigned Value = 0;
1088  int32_t tmp = (int32_t)MO1.getImm();
1089  if (tmp < 0)
1090    tmp = abs(tmp);
1091  else
1092    Value |= 4096; // Set the ADD bit
1093  Value |= tmp & 4095;
1094  return Value;
1095}
1096
1097unsigned ARMMCCodeEmitter::
1098getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1099                SmallVectorImpl<MCFixup> &Fixups) const {
1100  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1101  // shifted. The second is the amount to shift by.
1102  //
1103  // {3-0} = Rm.
1104  // {4}   = 0
1105  // {6-5} = type
1106  // {11-7} = imm
1107
1108  const MCOperand &MO  = MI.getOperand(OpIdx);
1109  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1110  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1111
1112  // Encode Rm.
1113  unsigned Binary = getARMRegisterNumbering(MO.getReg());
1114
1115  // Encode the shift opcode.
1116  unsigned SBits = 0;
1117  // Set shift operand (bit[6:4]).
1118  // LSL - 000
1119  // LSR - 010
1120  // ASR - 100
1121  // ROR - 110
1122  switch (SOpc) {
1123  default: llvm_unreachable("Unknown shift opc!");
1124  case ARM_AM::lsl: SBits = 0x0; break;
1125  case ARM_AM::lsr: SBits = 0x2; break;
1126  case ARM_AM::asr: SBits = 0x4; break;
1127  case ARM_AM::ror: SBits = 0x6; break;
1128  }
1129
1130  Binary |= SBits << 4;
1131  if (SOpc == ARM_AM::rrx)
1132    return Binary;
1133
1134  // Encode shift_imm bit[11:7].
1135  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1136}
1137
1138unsigned ARMMCCodeEmitter::
1139getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1140                               SmallVectorImpl<MCFixup> &Fixups) const {
1141  // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1142  // msb of the mask.
1143  const MCOperand &MO = MI.getOperand(Op);
1144  uint32_t v = ~MO.getImm();
1145  uint32_t lsb = CountTrailingZeros_32(v);
1146  uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1147  assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1148  return lsb | (msb << 5);
1149}
1150
1151unsigned ARMMCCodeEmitter::
1152getMsbOpValue(const MCInst &MI, unsigned Op,
1153              SmallVectorImpl<MCFixup> &Fixups) const {
1154  // MSB - 5 bits.
1155  uint32_t lsb = MI.getOperand(Op-1).getImm();
1156  uint32_t width = MI.getOperand(Op).getImm();
1157  uint32_t msb = lsb+width-1;
1158  assert (width != 0 && msb < 32 && "Illegal bit width!");
1159  return msb;
1160}
1161
1162unsigned ARMMCCodeEmitter::
1163getRegisterListOpValue(const MCInst &MI, unsigned Op,
1164                       SmallVectorImpl<MCFixup> &Fixups) const {
1165  // VLDM/VSTM:
1166  //   {12-8} = Vd
1167  //   {7-0}  = Number of registers
1168  //
1169  // LDM/STM:
1170  //   {15-0}  = Bitfield of GPRs.
1171  unsigned Reg = MI.getOperand(Op).getReg();
1172  bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1173  bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1174
1175  unsigned Binary = 0;
1176
1177  if (SPRRegs || DPRRegs) {
1178    // VLDM/VSTM
1179    unsigned RegNo = getARMRegisterNumbering(Reg);
1180    unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1181    Binary |= (RegNo & 0x1f) << 8;
1182    if (SPRRegs)
1183      Binary |= NumRegs;
1184    else
1185      Binary |= NumRegs * 2;
1186  } else {
1187    for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1188      unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1189      Binary |= 1 << RegNo;
1190    }
1191  }
1192
1193  return Binary;
1194}
1195
1196/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1197/// with the alignment operand.
1198unsigned ARMMCCodeEmitter::
1199getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1200                           SmallVectorImpl<MCFixup> &Fixups) const {
1201  const MCOperand &Reg = MI.getOperand(Op);
1202  const MCOperand &Imm = MI.getOperand(Op + 1);
1203
1204  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1205  unsigned Align = 0;
1206
1207  switch (Imm.getImm()) {
1208  default: break;
1209  case 2:
1210  case 4:
1211  case 8:  Align = 0x01; break;
1212  case 16: Align = 0x02; break;
1213  case 32: Align = 0x03; break;
1214  }
1215
1216  return RegNo | (Align << 4);
1217}
1218
1219/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1220/// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1221unsigned ARMMCCodeEmitter::
1222getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1223                                    SmallVectorImpl<MCFixup> &Fixups) const {
1224  const MCOperand &Reg = MI.getOperand(Op);
1225  const MCOperand &Imm = MI.getOperand(Op + 1);
1226
1227  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1228  unsigned Align = 0;
1229
1230  switch (Imm.getImm()) {
1231  default: break;
1232  case 2:
1233  case 4:
1234  case 8:
1235  case 16: Align = 0x00; break;
1236  case 32: Align = 0x03; break;
1237  }
1238
1239  return RegNo | (Align << 4);
1240}
1241
1242
1243/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1244/// alignment operand for use in VLD-dup instructions.  This is the same as
1245/// getAddrMode6AddressOpValue except for the alignment encoding, which is
1246/// different for VLD4-dup.
1247unsigned ARMMCCodeEmitter::
1248getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1249                              SmallVectorImpl<MCFixup> &Fixups) const {
1250  const MCOperand &Reg = MI.getOperand(Op);
1251  const MCOperand &Imm = MI.getOperand(Op + 1);
1252
1253  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1254  unsigned Align = 0;
1255
1256  switch (Imm.getImm()) {
1257  default: break;
1258  case 2:
1259  case 4:
1260  case 8:  Align = 0x01; break;
1261  case 16: Align = 0x03; break;
1262  }
1263
1264  return RegNo | (Align << 4);
1265}
1266
1267unsigned ARMMCCodeEmitter::
1268getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1269                          SmallVectorImpl<MCFixup> &Fixups) const {
1270  const MCOperand &MO = MI.getOperand(Op);
1271  if (MO.getReg() == 0) return 0x0D;
1272  return MO.getReg();
1273}
1274
1275unsigned ARMMCCodeEmitter::
1276getShiftRight8Imm(const MCInst &MI, unsigned Op,
1277                  SmallVectorImpl<MCFixup> &Fixups) const {
1278  return 8 - MI.getOperand(Op).getImm();
1279}
1280
1281unsigned ARMMCCodeEmitter::
1282getShiftRight16Imm(const MCInst &MI, unsigned Op,
1283                   SmallVectorImpl<MCFixup> &Fixups) const {
1284  return 16 - MI.getOperand(Op).getImm();
1285}
1286
1287unsigned ARMMCCodeEmitter::
1288getShiftRight32Imm(const MCInst &MI, unsigned Op,
1289                   SmallVectorImpl<MCFixup> &Fixups) const {
1290  return 32 - MI.getOperand(Op).getImm();
1291}
1292
1293unsigned ARMMCCodeEmitter::
1294getShiftRight64Imm(const MCInst &MI, unsigned Op,
1295                   SmallVectorImpl<MCFixup> &Fixups) const {
1296  return 64 - MI.getOperand(Op).getImm();
1297}
1298
1299void ARMMCCodeEmitter::
1300EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1301                  SmallVectorImpl<MCFixup> &Fixups) const {
1302  // Pseudo instructions don't get encoded.
1303  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1304  uint64_t TSFlags = Desc.TSFlags;
1305  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1306    return;
1307
1308  int Size;
1309  if (Desc.getSize() == 2 || Desc.getSize() == 4)
1310    Size = Desc.getSize();
1311  else
1312    llvm_unreachable("Unexpected instruction size!");
1313
1314  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1315  // Thumb 32-bit wide instructions need to emit the high order halfword
1316  // first.
1317  if (isThumb() && Size == 4) {
1318    EmitConstant(Binary >> 16, 2, OS);
1319    EmitConstant(Binary & 0xffff, 2, OS);
1320  } else
1321    EmitConstant(Binary, Size, OS);
1322  ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1323}
1324
1325#include "ARMGenMCCodeEmitter.inc"
1326