ARMMCCodeEmitter.cpp revision 354712c5a506449676e6fcac6b623af4092e7100 
1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARMMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "MCTargetDesc/ARMFixupKinds.h"
18#include "MCTargetDesc/ARMMCExpr.h"
19#include "MCTargetDesc/ARMMCTargetDesc.h"
20#include "llvm/MC/MCCodeEmitter.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/Support/raw_ostream.h"
29
30using namespace llvm;
31
32STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
34
35namespace {
36class ARMMCCodeEmitter : public MCCodeEmitter {
37  ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38  void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39  const MCInstrInfo &MCII;
40  const MCSubtargetInfo &STI;
41
42public:
43  ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
44                   MCContext &ctx)
45    : MCII(mcii), STI(sti) {
46  }
47
48  ~ARMMCCodeEmitter() {}
49
50  bool isThumb() const {
51    // FIXME: Can tablegen auto-generate this?
52    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
53  }
54  bool isThumb2() const {
55    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
56  }
57  bool isTargetDarwin() const {
58    Triple TT(STI.getTargetTriple());
59    Triple::OSType OS = TT.getOS();
60    return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
61  }
62
63  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
64
65  // getBinaryCodeForInstr - TableGen'erated function for getting the
66  // binary encoding for an instruction.
67  unsigned getBinaryCodeForInstr(const MCInst &MI,
68                                 SmallVectorImpl<MCFixup> &Fixups) const;
69
70  /// getMachineOpValue - Return binary encoding of operand. If the machine
71  /// operand requires relocation, record the relocation and return zero.
72  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73                             SmallVectorImpl<MCFixup> &Fixups) const;
74
75  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76  /// the specified operand. This is used for operands with :lower16: and
77  /// :upper16: prefixes.
78  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79                               SmallVectorImpl<MCFixup> &Fixups) const;
80
81  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82                              unsigned &Reg, unsigned &Imm,
83                              SmallVectorImpl<MCFixup> &Fixups) const;
84
85  /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
86  /// BL branch target.
87  uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88                                   SmallVectorImpl<MCFixup> &Fixups) const;
89
90  /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91  /// BLX branch target.
92  uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93                                    SmallVectorImpl<MCFixup> &Fixups) const;
94
95  /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96  uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97                                   SmallVectorImpl<MCFixup> &Fixups) const;
98
99  /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100  uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101                                    SmallVectorImpl<MCFixup> &Fixups) const;
102
103  /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104  uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105                                   SmallVectorImpl<MCFixup> &Fixups) const;
106
107  /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
108  /// branch target.
109  uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110                                  SmallVectorImpl<MCFixup> &Fixups) const;
111
112  /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113  /// immediate Thumb2 direct branch target.
114  uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115                                  SmallVectorImpl<MCFixup> &Fixups) const;
116
117  /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
118  /// branch target.
119  uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120                                     SmallVectorImpl<MCFixup> &Fixups) const;
121
122  /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
123  /// ADR label target.
124  uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
125                              SmallVectorImpl<MCFixup> &Fixups) const;
126  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
127                              SmallVectorImpl<MCFixup> &Fixups) const;
128  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129                              SmallVectorImpl<MCFixup> &Fixups) const;
130
131
132  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
133  /// operand.
134  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
135                                   SmallVectorImpl<MCFixup> &Fixups) const;
136
137  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
138  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
139                                         SmallVectorImpl<MCFixup> &Fixups)const;
140
141  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
142  /// operand.
143  uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
144                                   SmallVectorImpl<MCFixup> &Fixups) const;
145
146
147  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
148  /// operand as needed by load/store instructions.
149  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
150                               SmallVectorImpl<MCFixup> &Fixups) const;
151
152  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
153  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
154                               SmallVectorImpl<MCFixup> &Fixups) const {
155    ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
156    switch (Mode) {
157    default: assert(0 && "Unknown addressing sub-mode!");
158    case ARM_AM::da: return 0;
159    case ARM_AM::ia: return 1;
160    case ARM_AM::db: return 2;
161    case ARM_AM::ib: return 3;
162    }
163  }
164  /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
165  ///
166  unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
167    switch (ShOpc) {
168    default: llvm_unreachable("Unknown shift opc!");
169    case ARM_AM::no_shift:
170    case ARM_AM::lsl: return 0;
171    case ARM_AM::lsr: return 1;
172    case ARM_AM::asr: return 2;
173    case ARM_AM::ror:
174    case ARM_AM::rrx: return 3;
175    }
176    return 0;
177  }
178
179  /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
180  uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
181                               SmallVectorImpl<MCFixup> &Fixups) const;
182
183  /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
184  uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
185                                     SmallVectorImpl<MCFixup> &Fixups) const;
186
187  /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
188  uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
189                                     SmallVectorImpl<MCFixup> &Fixups) const;
190
191  /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
192  uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
193                               SmallVectorImpl<MCFixup> &Fixups) const;
194
195  /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
196  /// operand.
197  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
198                                     SmallVectorImpl<MCFixup> &Fixups) const;
199
200  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
201  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
202                                SmallVectorImpl<MCFixup> &Fixups) const;
203
204  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
205  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
206                                SmallVectorImpl<MCFixup> &Fixups) const;
207
208  /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
209  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
210                               SmallVectorImpl<MCFixup> &Fixups) const;
211
212  /// getCCOutOpValue - Return encoding of the 's' bit.
213  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
214                           SmallVectorImpl<MCFixup> &Fixups) const {
215    // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
216    // '1' respectively.
217    return MI.getOperand(Op).getReg() == ARM::CPSR;
218  }
219
220  /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
221  unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
222                           SmallVectorImpl<MCFixup> &Fixups) const {
223    unsigned SoImm = MI.getOperand(Op).getImm();
224    int SoImmVal = ARM_AM::getSOImmVal(SoImm);
225    assert(SoImmVal != -1 && "Not a valid so_imm value!");
226
227    // Encode rotate_imm.
228    unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
229      << ARMII::SoRotImmShift;
230
231    // Encode immed_8.
232    Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
233    return Binary;
234  }
235
236  /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
237  unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
238                           SmallVectorImpl<MCFixup> &Fixups) const {
239    unsigned SoImm = MI.getOperand(Op).getImm();
240    unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
241    assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
242    return Encoded;
243  }
244
245  unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
246    SmallVectorImpl<MCFixup> &Fixups) const;
247  unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
248    SmallVectorImpl<MCFixup> &Fixups) const;
249  unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
250    SmallVectorImpl<MCFixup> &Fixups) const;
251  unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
252    SmallVectorImpl<MCFixup> &Fixups) const;
253
254  /// getSORegOpValue - Return an encoded so_reg shifted register value.
255  unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
256                           SmallVectorImpl<MCFixup> &Fixups) const;
257  unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
258                           SmallVectorImpl<MCFixup> &Fixups) const;
259  unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
260                             SmallVectorImpl<MCFixup> &Fixups) const;
261
262  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
263                                   SmallVectorImpl<MCFixup> &Fixups) const {
264    return 64 - MI.getOperand(Op).getImm();
265  }
266
267  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
268                                      SmallVectorImpl<MCFixup> &Fixups) const;
269
270  unsigned getMsbOpValue(const MCInst &MI, unsigned Op,
271                         SmallVectorImpl<MCFixup> &Fixups) const;
272
273  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
274                                  SmallVectorImpl<MCFixup> &Fixups) const;
275  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
276                                      SmallVectorImpl<MCFixup> &Fixups) const;
277  unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
278                                        SmallVectorImpl<MCFixup> &Fixups) const;
279  unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
280                                        SmallVectorImpl<MCFixup> &Fixups) const;
281  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
282                                     SmallVectorImpl<MCFixup> &Fixups) const;
283
284  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
285                             SmallVectorImpl<MCFixup> &Fixups) const;
286  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
287                              SmallVectorImpl<MCFixup> &Fixups) const;
288  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
289                              SmallVectorImpl<MCFixup> &Fixups) const;
290  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
291                              SmallVectorImpl<MCFixup> &Fixups) const;
292
293  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
294                                      unsigned EncodedValue) const;
295  unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
296                                          unsigned EncodedValue) const;
297  unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
298                                    unsigned EncodedValue) const;
299
300  unsigned VFPThumb2PostEncoder(const MCInst &MI,
301                                unsigned EncodedValue) const;
302
303  void EmitByte(unsigned char C, raw_ostream &OS) const {
304    OS << (char)C;
305  }
306
307  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
308    // Output the constant in little endian byte order.
309    for (unsigned i = 0; i != Size; ++i) {
310      EmitByte(Val & 255, OS);
311      Val >>= 8;
312    }
313  }
314
315  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
316                         SmallVectorImpl<MCFixup> &Fixups) const;
317};
318
319} // end anonymous namespace
320
321MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
322                                            const MCSubtargetInfo &STI,
323                                            MCContext &Ctx) {
324  return new ARMMCCodeEmitter(MCII, STI, Ctx);
325}
326
327/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
328/// instructions, and rewrite them to their Thumb2 form if we are currently in
329/// Thumb2 mode.
330unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
331                                                 unsigned EncodedValue) const {
332  if (isThumb2()) {
333    // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
334    // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
335    // set to 1111.
336    unsigned Bit24 = EncodedValue & 0x01000000;
337    unsigned Bit28 = Bit24 << 4;
338    EncodedValue &= 0xEFFFFFFF;
339    EncodedValue |= Bit28;
340    EncodedValue |= 0x0F000000;
341  }
342
343  return EncodedValue;
344}
345
346/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
347/// instructions, and rewrite them to their Thumb2 form if we are currently in
348/// Thumb2 mode.
349unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
350                                                 unsigned EncodedValue) const {
351  if (isThumb2()) {
352    EncodedValue &= 0xF0FFFFFF;
353    EncodedValue |= 0x09000000;
354  }
355
356  return EncodedValue;
357}
358
359/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
360/// instructions, and rewrite them to their Thumb2 form if we are currently in
361/// Thumb2 mode.
362unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
363                                                 unsigned EncodedValue) const {
364  if (isThumb2()) {
365    EncodedValue &= 0x00FFFFFF;
366    EncodedValue |= 0xEE000000;
367  }
368
369  return EncodedValue;
370}
371
372/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
373/// them to their Thumb2 form if we are currently in Thumb2 mode.
374unsigned ARMMCCodeEmitter::
375VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
376  if (isThumb2()) {
377    EncodedValue &= 0x0FFFFFFF;
378    EncodedValue |= 0xE0000000;
379  }
380  return EncodedValue;
381}
382
383/// getMachineOpValue - Return binary encoding of operand. If the machine
384/// operand requires relocation, record the relocation and return zero.
385unsigned ARMMCCodeEmitter::
386getMachineOpValue(const MCInst &MI, const MCOperand &MO,
387                  SmallVectorImpl<MCFixup> &Fixups) const {
388  if (MO.isReg()) {
389    unsigned Reg = MO.getReg();
390    unsigned RegNo = getARMRegisterNumbering(Reg);
391
392    // Q registers are encoded as 2x their register number.
393    switch (Reg) {
394    default:
395      return RegNo;
396    case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
397    case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
398    case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
399    case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
400      return 2 * RegNo;
401    }
402  } else if (MO.isImm()) {
403    return static_cast<unsigned>(MO.getImm());
404  } else if (MO.isFPImm()) {
405    return static_cast<unsigned>(APFloat(MO.getFPImm())
406                     .bitcastToAPInt().getHiBits(32).getLimitedValue());
407  }
408
409  llvm_unreachable("Unable to encode MCOperand!");
410  return 0;
411}
412
413/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
414bool ARMMCCodeEmitter::
415EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
416                       unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
417  const MCOperand &MO  = MI.getOperand(OpIdx);
418  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
419
420  Reg = getARMRegisterNumbering(MO.getReg());
421
422  int32_t SImm = MO1.getImm();
423  bool isAdd = true;
424
425  // Special value for #-0
426  if (SImm == INT32_MIN)
427    SImm = 0;
428
429  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
430  if (SImm < 0) {
431    SImm = -SImm;
432    isAdd = false;
433  }
434
435  Imm = SImm;
436  return isAdd;
437}
438
439/// getBranchTargetOpValue - Helper function to get the branch target operand,
440/// which is either an immediate or requires a fixup.
441static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
442                                       unsigned FixupKind,
443                                       SmallVectorImpl<MCFixup> &Fixups) {
444  const MCOperand &MO = MI.getOperand(OpIdx);
445
446  // If the destination is an immediate, we have nothing to do.
447  if (MO.isImm()) return MO.getImm();
448  assert(MO.isExpr() && "Unexpected branch target type!");
449  const MCExpr *Expr = MO.getExpr();
450  MCFixupKind Kind = MCFixupKind(FixupKind);
451  Fixups.push_back(MCFixup::Create(0, Expr, Kind));
452
453  // All of the information is in the fixup.
454  return 0;
455}
456
457/// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
458uint32_t ARMMCCodeEmitter::
459getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
460                        SmallVectorImpl<MCFixup> &Fixups) const {
461  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
462}
463
464/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
465/// BLX branch target.
466uint32_t ARMMCCodeEmitter::
467getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
468                         SmallVectorImpl<MCFixup> &Fixups) const {
469  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
470}
471
472/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
473uint32_t ARMMCCodeEmitter::
474getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
475                        SmallVectorImpl<MCFixup> &Fixups) const {
476  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
477}
478
479/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
480uint32_t ARMMCCodeEmitter::
481getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
482                         SmallVectorImpl<MCFixup> &Fixups) const {
483  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
484}
485
486/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
487uint32_t ARMMCCodeEmitter::
488getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
489                        SmallVectorImpl<MCFixup> &Fixups) const {
490  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
491}
492
493/// Return true if this branch has a non-always predication
494static bool HasConditionalBranch(const MCInst &MI) {
495  int NumOp = MI.getNumOperands();
496  if (NumOp >= 2) {
497    for (int i = 0; i < NumOp-1; ++i) {
498      const MCOperand &MCOp1 = MI.getOperand(i);
499      const MCOperand &MCOp2 = MI.getOperand(i + 1);
500      if (MCOp1.isImm() && MCOp2.isReg() &&
501          (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
502        if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
503          return true;
504      }
505    }
506  }
507  return false;
508}
509
510/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
511/// target.
512uint32_t ARMMCCodeEmitter::
513getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
514                       SmallVectorImpl<MCFixup> &Fixups) const {
515  // FIXME: This really, really shouldn't use TargetMachine. We don't want
516  // coupling between MC and TM anywhere we can help it.
517  if (isThumb2())
518    return
519      ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
520  return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
521}
522
523/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
524/// target.
525uint32_t ARMMCCodeEmitter::
526getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
527                          SmallVectorImpl<MCFixup> &Fixups) const {
528  if (HasConditionalBranch(MI))
529    return ::getBranchTargetOpValue(MI, OpIdx,
530                                    ARM::fixup_arm_condbranch, Fixups);
531  return ::getBranchTargetOpValue(MI, OpIdx,
532                                  ARM::fixup_arm_uncondbranch, Fixups);
533}
534
535
536
537
538/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
539/// immediate branch target.
540uint32_t ARMMCCodeEmitter::
541getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
542                       SmallVectorImpl<MCFixup> &Fixups) const {
543  unsigned Val =
544    ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
545  bool I  = (Val & 0x800000);
546  bool J1 = (Val & 0x400000);
547  bool J2 = (Val & 0x200000);
548  if (I ^ J1)
549    Val &= ~0x400000;
550  else
551    Val |= 0x400000;
552
553  if (I ^ J2)
554    Val &= ~0x200000;
555  else
556    Val |= 0x200000;
557
558  return Val;
559}
560
561/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
562/// target.
563uint32_t ARMMCCodeEmitter::
564getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
565                   SmallVectorImpl<MCFixup> &Fixups) const {
566  assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
567  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
568                                  Fixups);
569}
570
571/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
572/// target.
573uint32_t ARMMCCodeEmitter::
574getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
575                   SmallVectorImpl<MCFixup> &Fixups) const {
576  assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
577  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
578                                  Fixups);
579}
580
581/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
582/// target.
583uint32_t ARMMCCodeEmitter::
584getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
585                   SmallVectorImpl<MCFixup> &Fixups) const {
586  assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
587  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
588                                  Fixups);
589}
590
591/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
592/// operand.
593uint32_t ARMMCCodeEmitter::
594getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
595                              SmallVectorImpl<MCFixup> &) const {
596  // [Rn, Rm]
597  //   {5-3} = Rm
598  //   {2-0} = Rn
599  const MCOperand &MO1 = MI.getOperand(OpIdx);
600  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
601  unsigned Rn = getARMRegisterNumbering(MO1.getReg());
602  unsigned Rm = getARMRegisterNumbering(MO2.getReg());
603  return (Rm << 3) | Rn;
604}
605
606/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
607uint32_t ARMMCCodeEmitter::
608getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
609                        SmallVectorImpl<MCFixup> &Fixups) const {
610  // {17-13} = reg
611  // {12}    = (U)nsigned (add == '1', sub == '0')
612  // {11-0}  = imm12
613  unsigned Reg, Imm12;
614  bool isAdd = true;
615  // If The first operand isn't a register, we have a label reference.
616  const MCOperand &MO = MI.getOperand(OpIdx);
617  if (!MO.isReg()) {
618    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
619    Imm12 = 0;
620    isAdd = false ; // 'U' bit is set as part of the fixup.
621
622    assert(MO.isExpr() && "Unexpected machine operand type!");
623    const MCExpr *Expr = MO.getExpr();
624
625    MCFixupKind Kind;
626    if (isThumb2())
627      Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
628    else
629      Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
630    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
631
632    ++MCNumCPRelocations;
633  } else
634    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
635
636  uint32_t Binary = Imm12 & 0xfff;
637  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
638  if (isAdd)
639    Binary |= (1 << 12);
640  Binary |= (Reg << 13);
641  return Binary;
642}
643
644/// getT2AddrModeImm8s4OpValue - Return encoding info for
645/// 'reg +/- imm8<<2' operand.
646uint32_t ARMMCCodeEmitter::
647getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
648                        SmallVectorImpl<MCFixup> &Fixups) const {
649  // {12-9} = reg
650  // {8}    = (U)nsigned (add == '1', sub == '0')
651  // {7-0}  = imm8
652  unsigned Reg, Imm8;
653  bool isAdd = true;
654  // If The first operand isn't a register, we have a label reference.
655  const MCOperand &MO = MI.getOperand(OpIdx);
656  if (!MO.isReg()) {
657    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
658    Imm8 = 0;
659    isAdd = false ; // 'U' bit is set as part of the fixup.
660
661    assert(MO.isExpr() && "Unexpected machine operand type!");
662    const MCExpr *Expr = MO.getExpr();
663    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
664    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
665
666    ++MCNumCPRelocations;
667  } else
668    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
669
670  uint32_t Binary = (Imm8 >> 2) & 0xff;
671  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
672  if (isAdd)
673    Binary |= (1 << 8);
674  Binary |= (Reg << 9);
675  return Binary;
676}
677
678// FIXME: This routine assumes that a binary
679// expression will always result in a PCRel expression
680// In reality, its only true if one or more subexpressions
681// is itself a PCRel (i.e. "." in asm or some other pcrel construct)
682// but this is good enough for now.
683static bool EvaluateAsPCRel(const MCExpr *Expr) {
684  switch (Expr->getKind()) {
685  default: assert(0 && "Unexpected expression type");
686  case MCExpr::SymbolRef: return false;
687  case MCExpr::Binary: return true;
688  }
689}
690
691uint32_t
692ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
693                                      SmallVectorImpl<MCFixup> &Fixups) const {
694  // {20-16} = imm{15-12}
695  // {11-0}  = imm{11-0}
696  const MCOperand &MO = MI.getOperand(OpIdx);
697  if (MO.isImm())
698    // Hi / lo 16 bits already extracted during earlier passes.
699    return static_cast<unsigned>(MO.getImm());
700
701  // Handle :upper16: and :lower16: assembly prefixes.
702  const MCExpr *E = MO.getExpr();
703  if (E->getKind() == MCExpr::Target) {
704    const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
705    E = ARM16Expr->getSubExpr();
706
707    MCFixupKind Kind;
708    switch (ARM16Expr->getKind()) {
709    default: assert(0 && "Unsupported ARMFixup");
710    case ARMMCExpr::VK_ARM_HI16:
711      if (!isTargetDarwin() && EvaluateAsPCRel(E))
712        Kind = MCFixupKind(isThumb2()
713                           ? ARM::fixup_t2_movt_hi16_pcrel
714                           : ARM::fixup_arm_movt_hi16_pcrel);
715      else
716        Kind = MCFixupKind(isThumb2()
717                           ? ARM::fixup_t2_movt_hi16
718                           : ARM::fixup_arm_movt_hi16);
719      break;
720    case ARMMCExpr::VK_ARM_LO16:
721      if (!isTargetDarwin() && EvaluateAsPCRel(E))
722        Kind = MCFixupKind(isThumb2()
723                           ? ARM::fixup_t2_movw_lo16_pcrel
724                           : ARM::fixup_arm_movw_lo16_pcrel);
725      else
726        Kind = MCFixupKind(isThumb2()
727                           ? ARM::fixup_t2_movw_lo16
728                           : ARM::fixup_arm_movw_lo16);
729      break;
730    }
731    Fixups.push_back(MCFixup::Create(0, E, Kind));
732    return 0;
733  };
734
735  llvm_unreachable("Unsupported MCExpr type in MCOperand!");
736  return 0;
737}
738
739uint32_t ARMMCCodeEmitter::
740getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
741                    SmallVectorImpl<MCFixup> &Fixups) const {
742  const MCOperand &MO = MI.getOperand(OpIdx);
743  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
744  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
745  unsigned Rn = getARMRegisterNumbering(MO.getReg());
746  unsigned Rm = getARMRegisterNumbering(MO1.getReg());
747  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
748  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
749  ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
750  unsigned SBits = getShiftOp(ShOp);
751
752  // {16-13} = Rn
753  // {12}    = isAdd
754  // {11-0}  = shifter
755  //  {3-0}  = Rm
756  //  {4}    = 0
757  //  {6-5}  = type
758  //  {11-7} = imm
759  uint32_t Binary = Rm;
760  Binary |= Rn << 13;
761  Binary |= SBits << 5;
762  Binary |= ShImm << 7;
763  if (isAdd)
764    Binary |= 1 << 12;
765  return Binary;
766}
767
768uint32_t ARMMCCodeEmitter::
769getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
770                    SmallVectorImpl<MCFixup> &Fixups) const {
771  // {17-14}  Rn
772  // {13}     1 == imm12, 0 == Rm
773  // {12}     isAdd
774  // {11-0}   imm12/Rm
775  const MCOperand &MO = MI.getOperand(OpIdx);
776  unsigned Rn = getARMRegisterNumbering(MO.getReg());
777  uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
778  Binary |= Rn << 14;
779  return Binary;
780}
781
782uint32_t ARMMCCodeEmitter::
783getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
784                          SmallVectorImpl<MCFixup> &Fixups) const {
785  // {13}     1 == imm12, 0 == Rm
786  // {12}     isAdd
787  // {11-0}   imm12/Rm
788  const MCOperand &MO = MI.getOperand(OpIdx);
789  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
790  unsigned Imm = MO1.getImm();
791  bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
792  bool isReg = MO.getReg() != 0;
793  uint32_t Binary = ARM_AM::getAM2Offset(Imm);
794  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
795  if (isReg) {
796    ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
797    Binary <<= 7;                    // Shift amount is bits [11:7]
798    Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
799    Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
800  }
801  return Binary | (isAdd << 12) | (isReg << 13);
802}
803
804uint32_t ARMMCCodeEmitter::
805getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
806                          SmallVectorImpl<MCFixup> &Fixups) const {
807  // {9}      1 == imm8, 0 == Rm
808  // {8}      isAdd
809  // {7-4}    imm7_4/zero
810  // {3-0}    imm3_0/Rm
811  const MCOperand &MO = MI.getOperand(OpIdx);
812  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
813  unsigned Imm = MO1.getImm();
814  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
815  bool isImm = MO.getReg() == 0;
816  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
817  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
818  if (!isImm)
819    Imm8 = getARMRegisterNumbering(MO.getReg());
820  return Imm8 | (isAdd << 8) | (isImm << 9);
821}
822
823uint32_t ARMMCCodeEmitter::
824getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
825                    SmallVectorImpl<MCFixup> &Fixups) const {
826  // {13}     1 == imm8, 0 == Rm
827  // {12-9}   Rn
828  // {8}      isAdd
829  // {7-4}    imm7_4/zero
830  // {3-0}    imm3_0/Rm
831  const MCOperand &MO = MI.getOperand(OpIdx);
832  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
833  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
834  unsigned Rn = getARMRegisterNumbering(MO.getReg());
835  unsigned Imm = MO2.getImm();
836  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
837  bool isImm = MO1.getReg() == 0;
838  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
839  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
840  if (!isImm)
841    Imm8 = getARMRegisterNumbering(MO1.getReg());
842  return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
843}
844
845/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
846uint32_t ARMMCCodeEmitter::
847getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
848                          SmallVectorImpl<MCFixup> &Fixups) const {
849  // [SP, #imm]
850  //   {7-0} = imm8
851  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
852  assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
853         "Unexpected base register!");
854
855  // The immediate is already shifted for the implicit zeroes, so no change
856  // here.
857  return MO1.getImm() & 0xff;
858}
859
860/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
861uint32_t ARMMCCodeEmitter::
862getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
863                     SmallVectorImpl<MCFixup> &Fixups) const {
864  // [Rn, #imm]
865  //   {7-3} = imm5
866  //   {2-0} = Rn
867  const MCOperand &MO = MI.getOperand(OpIdx);
868  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
869  unsigned Rn = getARMRegisterNumbering(MO.getReg());
870  unsigned Imm5 = MO1.getImm();
871  return ((Imm5 & 0x1f) << 3) | Rn;
872}
873
874/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
875uint32_t ARMMCCodeEmitter::
876getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
877                     SmallVectorImpl<MCFixup> &Fixups) const {
878  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
879}
880
881/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
882uint32_t ARMMCCodeEmitter::
883getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
884                    SmallVectorImpl<MCFixup> &Fixups) const {
885  // {12-9} = reg
886  // {8}    = (U)nsigned (add == '1', sub == '0')
887  // {7-0}  = imm8
888  unsigned Reg, Imm8;
889  bool isAdd;
890  // If The first operand isn't a register, we have a label reference.
891  const MCOperand &MO = MI.getOperand(OpIdx);
892  if (!MO.isReg()) {
893    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
894    Imm8 = 0;
895    isAdd = false; // 'U' bit is handled as part of the fixup.
896
897    assert(MO.isExpr() && "Unexpected machine operand type!");
898    const MCExpr *Expr = MO.getExpr();
899    MCFixupKind Kind;
900    if (isThumb2())
901      Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
902    else
903      Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
904    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
905
906    ++MCNumCPRelocations;
907  } else {
908    EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
909    isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
910  }
911
912  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
913  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
914  if (isAdd)
915    Binary |= (1 << 8);
916  Binary |= (Reg << 9);
917  return Binary;
918}
919
920unsigned ARMMCCodeEmitter::
921getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
922                SmallVectorImpl<MCFixup> &Fixups) const {
923  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
924  // shifted. The second is Rs, the amount to shift by, and the third specifies
925  // the type of the shift.
926  //
927  // {3-0} = Rm.
928  // {4}   = 1
929  // {6-5} = type
930  // {11-8} = Rs
931  // {7}    = 0
932
933  const MCOperand &MO  = MI.getOperand(OpIdx);
934  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
935  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
936  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
937
938  // Encode Rm.
939  unsigned Binary = getARMRegisterNumbering(MO.getReg());
940
941  // Encode the shift opcode.
942  unsigned SBits = 0;
943  unsigned Rs = MO1.getReg();
944  if (Rs) {
945    // Set shift operand (bit[7:4]).
946    // LSL - 0001
947    // LSR - 0011
948    // ASR - 0101
949    // ROR - 0111
950    switch (SOpc) {
951    default: llvm_unreachable("Unknown shift opc!");
952    case ARM_AM::lsl: SBits = 0x1; break;
953    case ARM_AM::lsr: SBits = 0x3; break;
954    case ARM_AM::asr: SBits = 0x5; break;
955    case ARM_AM::ror: SBits = 0x7; break;
956    }
957  }
958
959  Binary |= SBits << 4;
960
961  // Encode the shift operation Rs.
962  // Encode Rs bit[11:8].
963  assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
964  return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
965}
966
967unsigned ARMMCCodeEmitter::
968getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
969                SmallVectorImpl<MCFixup> &Fixups) const {
970  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
971  // shifted. The second is the amount to shift by.
972  //
973  // {3-0} = Rm.
974  // {4}   = 0
975  // {6-5} = type
976  // {11-7} = imm
977
978  const MCOperand &MO  = MI.getOperand(OpIdx);
979  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
980  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
981
982  // Encode Rm.
983  unsigned Binary = getARMRegisterNumbering(MO.getReg());
984
985  // Encode the shift opcode.
986  unsigned SBits = 0;
987
988  // Set shift operand (bit[6:4]).
989  // LSL - 000
990  // LSR - 010
991  // ASR - 100
992  // ROR - 110
993  // RRX - 110 and bit[11:8] clear.
994  switch (SOpc) {
995  default: llvm_unreachable("Unknown shift opc!");
996  case ARM_AM::lsl: SBits = 0x0; break;
997  case ARM_AM::lsr: SBits = 0x2; break;
998  case ARM_AM::asr: SBits = 0x4; break;
999  case ARM_AM::ror: SBits = 0x6; break;
1000  case ARM_AM::rrx:
1001    Binary |= 0x60;
1002    return Binary;
1003  }
1004
1005  // Encode shift_imm bit[11:7].
1006  Binary |= SBits << 4;
1007  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1008}
1009
1010
1011unsigned ARMMCCodeEmitter::
1012getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1013                SmallVectorImpl<MCFixup> &Fixups) const {
1014  const MCOperand &MO1 = MI.getOperand(OpNum);
1015  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1016  const MCOperand &MO3 = MI.getOperand(OpNum+2);
1017
1018  // Encoded as [Rn, Rm, imm].
1019  // FIXME: Needs fixup support.
1020  unsigned Value = getARMRegisterNumbering(MO1.getReg());
1021  Value <<= 4;
1022  Value |= getARMRegisterNumbering(MO2.getReg());
1023  Value <<= 2;
1024  Value |= MO3.getImm();
1025
1026  return Value;
1027}
1028
1029unsigned ARMMCCodeEmitter::
1030getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1031                         SmallVectorImpl<MCFixup> &Fixups) const {
1032  const MCOperand &MO1 = MI.getOperand(OpNum);
1033  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1034
1035  // FIXME: Needs fixup support.
1036  unsigned Value = getARMRegisterNumbering(MO1.getReg());
1037
1038  // Even though the immediate is 8 bits long, we need 9 bits in order
1039  // to represent the (inverse of the) sign bit.
1040  Value <<= 9;
1041  int32_t tmp = (int32_t)MO2.getImm();
1042  if (tmp < 0)
1043    tmp = abs(tmp);
1044  else
1045    Value |= 256; // Set the ADD bit
1046  Value |= tmp & 255;
1047  return Value;
1048}
1049
1050unsigned ARMMCCodeEmitter::
1051getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1052                         SmallVectorImpl<MCFixup> &Fixups) const {
1053  const MCOperand &MO1 = MI.getOperand(OpNum);
1054
1055  // FIXME: Needs fixup support.
1056  unsigned Value = 0;
1057  int32_t tmp = (int32_t)MO1.getImm();
1058  if (tmp < 0)
1059    tmp = abs(tmp);
1060  else
1061    Value |= 256; // Set the ADD bit
1062  Value |= tmp & 255;
1063  return Value;
1064}
1065
1066unsigned ARMMCCodeEmitter::
1067getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1068                         SmallVectorImpl<MCFixup> &Fixups) const {
1069  const MCOperand &MO1 = MI.getOperand(OpNum);
1070
1071  // FIXME: Needs fixup support.
1072  unsigned Value = 0;
1073  int32_t tmp = (int32_t)MO1.getImm();
1074  if (tmp < 0)
1075    tmp = abs(tmp);
1076  else
1077    Value |= 4096; // Set the ADD bit
1078  Value |= tmp & 4095;
1079  return Value;
1080}
1081
1082unsigned ARMMCCodeEmitter::
1083getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1084                SmallVectorImpl<MCFixup> &Fixups) const {
1085  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1086  // shifted. The second is the amount to shift by.
1087  //
1088  // {3-0} = Rm.
1089  // {4}   = 0
1090  // {6-5} = type
1091  // {11-7} = imm
1092
1093  const MCOperand &MO  = MI.getOperand(OpIdx);
1094  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1095  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1096
1097  // Encode Rm.
1098  unsigned Binary = getARMRegisterNumbering(MO.getReg());
1099
1100  // Encode the shift opcode.
1101  unsigned SBits = 0;
1102  // Set shift operand (bit[6:4]).
1103  // LSL - 000
1104  // LSR - 010
1105  // ASR - 100
1106  // ROR - 110
1107  switch (SOpc) {
1108  default: llvm_unreachable("Unknown shift opc!");
1109  case ARM_AM::lsl: SBits = 0x0; break;
1110  case ARM_AM::lsr: SBits = 0x2; break;
1111  case ARM_AM::asr: SBits = 0x4; break;
1112  case ARM_AM::ror: SBits = 0x6; break;
1113  }
1114
1115  Binary |= SBits << 4;
1116  if (SOpc == ARM_AM::rrx)
1117    return Binary;
1118
1119  // Encode shift_imm bit[11:7].
1120  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1121}
1122
1123unsigned ARMMCCodeEmitter::
1124getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1125                               SmallVectorImpl<MCFixup> &Fixups) const {
1126  // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1127  // msb of the mask.
1128  const MCOperand &MO = MI.getOperand(Op);
1129  uint32_t v = ~MO.getImm();
1130  uint32_t lsb = CountTrailingZeros_32(v);
1131  uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1132  assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1133  return lsb | (msb << 5);
1134}
1135
1136unsigned ARMMCCodeEmitter::
1137getMsbOpValue(const MCInst &MI, unsigned Op,
1138              SmallVectorImpl<MCFixup> &Fixups) const {
1139  // MSB - 5 bits.
1140  uint32_t lsb = MI.getOperand(Op-1).getImm();
1141  uint32_t width = MI.getOperand(Op).getImm();
1142  uint32_t msb = lsb+width-1;
1143  assert (width != 0 && msb < 32 && "Illegal bit width!");
1144  return msb;
1145}
1146
1147unsigned ARMMCCodeEmitter::
1148getRegisterListOpValue(const MCInst &MI, unsigned Op,
1149                       SmallVectorImpl<MCFixup> &Fixups) const {
1150  // VLDM/VSTM:
1151  //   {12-8} = Vd
1152  //   {7-0}  = Number of registers
1153  //
1154  // LDM/STM:
1155  //   {15-0}  = Bitfield of GPRs.
1156  unsigned Reg = MI.getOperand(Op).getReg();
1157  bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1158  bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1159
1160  unsigned Binary = 0;
1161
1162  if (SPRRegs || DPRRegs) {
1163    // VLDM/VSTM
1164    unsigned RegNo = getARMRegisterNumbering(Reg);
1165    unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1166    Binary |= (RegNo & 0x1f) << 8;
1167    if (SPRRegs)
1168      Binary |= NumRegs;
1169    else
1170      Binary |= NumRegs * 2;
1171  } else {
1172    for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1173      unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1174      Binary |= 1 << RegNo;
1175    }
1176  }
1177
1178  return Binary;
1179}
1180
1181/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1182/// with the alignment operand.
1183unsigned ARMMCCodeEmitter::
1184getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1185                           SmallVectorImpl<MCFixup> &Fixups) const {
1186  const MCOperand &Reg = MI.getOperand(Op);
1187  const MCOperand &Imm = MI.getOperand(Op + 1);
1188
1189  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1190  unsigned Align = 0;
1191
1192  switch (Imm.getImm()) {
1193  default: break;
1194  case 2:
1195  case 4:
1196  case 8:  Align = 0x01; break;
1197  case 16: Align = 0x02; break;
1198  case 32: Align = 0x03; break;
1199  }
1200
1201  return RegNo | (Align << 4);
1202}
1203
1204/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1205/// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1206unsigned ARMMCCodeEmitter::
1207getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1208                                    SmallVectorImpl<MCFixup> &Fixups) const {
1209  const MCOperand &Reg = MI.getOperand(Op);
1210  const MCOperand &Imm = MI.getOperand(Op + 1);
1211
1212  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1213  unsigned Align = 0;
1214
1215  switch (Imm.getImm()) {
1216  default: break;
1217  case 2:
1218  case 4:
1219  case 8:
1220  case 16: Align = 0x00; break;
1221  case 32: Align = 0x03; break;
1222  }
1223
1224  return RegNo | (Align << 4);
1225}
1226
1227
1228/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1229/// alignment operand for use in VLD-dup instructions.  This is the same as
1230/// getAddrMode6AddressOpValue except for the alignment encoding, which is
1231/// different for VLD4-dup.
1232unsigned ARMMCCodeEmitter::
1233getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1234                              SmallVectorImpl<MCFixup> &Fixups) const {
1235  const MCOperand &Reg = MI.getOperand(Op);
1236  const MCOperand &Imm = MI.getOperand(Op + 1);
1237
1238  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1239  unsigned Align = 0;
1240
1241  switch (Imm.getImm()) {
1242  default: break;
1243  case 2:
1244  case 4:
1245  case 8:  Align = 0x01; break;
1246  case 16: Align = 0x03; break;
1247  }
1248
1249  return RegNo | (Align << 4);
1250}
1251
1252unsigned ARMMCCodeEmitter::
1253getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1254                          SmallVectorImpl<MCFixup> &Fixups) const {
1255  const MCOperand &MO = MI.getOperand(Op);
1256  if (MO.getReg() == 0) return 0x0D;
1257  return MO.getReg();
1258}
1259
1260unsigned ARMMCCodeEmitter::
1261getShiftRight8Imm(const MCInst &MI, unsigned Op,
1262                  SmallVectorImpl<MCFixup> &Fixups) const {
1263  return 8 - MI.getOperand(Op).getImm();
1264}
1265
1266unsigned ARMMCCodeEmitter::
1267getShiftRight16Imm(const MCInst &MI, unsigned Op,
1268                   SmallVectorImpl<MCFixup> &Fixups) const {
1269  return 16 - MI.getOperand(Op).getImm();
1270}
1271
1272unsigned ARMMCCodeEmitter::
1273getShiftRight32Imm(const MCInst &MI, unsigned Op,
1274                   SmallVectorImpl<MCFixup> &Fixups) const {
1275  return 32 - MI.getOperand(Op).getImm();
1276}
1277
1278unsigned ARMMCCodeEmitter::
1279getShiftRight64Imm(const MCInst &MI, unsigned Op,
1280                   SmallVectorImpl<MCFixup> &Fixups) const {
1281  return 64 - MI.getOperand(Op).getImm();
1282}
1283
1284void ARMMCCodeEmitter::
1285EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1286                  SmallVectorImpl<MCFixup> &Fixups) const {
1287  // Pseudo instructions don't get encoded.
1288  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1289  uint64_t TSFlags = Desc.TSFlags;
1290  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1291    return;
1292
1293  int Size;
1294  if (Desc.getSize() == 2 || Desc.getSize() == 4)
1295    Size = Desc.getSize();
1296  else
1297    llvm_unreachable("Unexpected instruction size!");
1298
1299  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1300  // Thumb 32-bit wide instructions need to emit the high order halfword
1301  // first.
1302  if (isThumb() && Size == 4) {
1303    EmitConstant(Binary >> 16, 2, OS);
1304    EmitConstant(Binary & 0xffff, 2, OS);
1305  } else
1306    EmitConstant(Binary, Size, OS);
1307  ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1308}
1309
1310#include "ARMGenMCCodeEmitter.inc"
1311