ARMMCCodeEmitter.cpp revision cb0809b82b126e79b99755ae4fc3d9733faea038 
1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARMMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "MCTargetDesc/ARMFixupKinds.h"
18#include "MCTargetDesc/ARMMCExpr.h"
19#include "MCTargetDesc/ARMMCTargetDesc.h"
20#include "llvm/MC/MCCodeEmitter.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/Support/raw_ostream.h"
29
30using namespace llvm;
31
32STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
34
35namespace {
36class ARMMCCodeEmitter : public MCCodeEmitter {
37  ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38  void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39  const MCInstrInfo &MCII;
40  const MCSubtargetInfo &STI;
41
42public:
43  ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
44                   MCContext &ctx)
45    : MCII(mcii), STI(sti) {
46  }
47
48  ~ARMMCCodeEmitter() {}
49
50  bool isThumb() const {
51    // FIXME: Can tablegen auto-generate this?
52    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
53  }
54  bool isThumb2() const {
55    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
56  }
57  bool isTargetDarwin() const {
58    Triple TT(STI.getTargetTriple());
59    Triple::OSType OS = TT.getOS();
60    return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
61  }
62
63  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
64
65  // getBinaryCodeForInstr - TableGen'erated function for getting the
66  // binary encoding for an instruction.
67  uint64_t getBinaryCodeForInstr(const MCInst &MI,
68                                 SmallVectorImpl<MCFixup> &Fixups) const;
69
70  /// getMachineOpValue - Return binary encoding of operand. If the machine
71  /// operand requires relocation, record the relocation and return zero.
72  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73                             SmallVectorImpl<MCFixup> &Fixups) const;
74
75  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76  /// the specified operand. This is used for operands with :lower16: and
77  /// :upper16: prefixes.
78  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79                               SmallVectorImpl<MCFixup> &Fixups) const;
80
81  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82                              unsigned &Reg, unsigned &Imm,
83                              SmallVectorImpl<MCFixup> &Fixups) const;
84
85  /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
86  /// BL branch target.
87  uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88                                   SmallVectorImpl<MCFixup> &Fixups) const;
89
90  /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91  /// BLX branch target.
92  uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93                                    SmallVectorImpl<MCFixup> &Fixups) const;
94
95  /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96  uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97                                   SmallVectorImpl<MCFixup> &Fixups) const;
98
99  /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100  uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101                                    SmallVectorImpl<MCFixup> &Fixups) const;
102
103  /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104  uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105                                   SmallVectorImpl<MCFixup> &Fixups) const;
106
107  /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
108  /// branch target.
109  uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110                                  SmallVectorImpl<MCFixup> &Fixups) const;
111
112  /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113  /// immediate Thumb2 direct branch target.
114  uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115                                  SmallVectorImpl<MCFixup> &Fixups) const;
116
117  /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
118  /// branch target.
119  uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120                                     SmallVectorImpl<MCFixup> &Fixups) const;
121  uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
122                                 SmallVectorImpl<MCFixup> &Fixups) const;
123  uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
124                                  SmallVectorImpl<MCFixup> &Fixups) const;
125
126  /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
127  /// ADR label target.
128  uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129                              SmallVectorImpl<MCFixup> &Fixups) const;
130  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131                              SmallVectorImpl<MCFixup> &Fixups) const;
132  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
133                              SmallVectorImpl<MCFixup> &Fixups) const;
134
135
136  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
137  /// operand.
138  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
139                                   SmallVectorImpl<MCFixup> &Fixups) const;
140
141  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
142  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
143                                         SmallVectorImpl<MCFixup> &Fixups)const;
144
145  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
146  /// operand.
147  uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
148                                   SmallVectorImpl<MCFixup> &Fixups) const;
149
150  /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
151  /// operand.
152  uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
153                                   SmallVectorImpl<MCFixup> &Fixups) const;
154
155  /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
156  /// operand.
157  uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
158                              SmallVectorImpl<MCFixup> &Fixups) const;
159
160
161  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
162  /// operand as needed by load/store instructions.
163  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
164                               SmallVectorImpl<MCFixup> &Fixups) const;
165
166  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
167  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
168                               SmallVectorImpl<MCFixup> &Fixups) const {
169    ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
170    switch (Mode) {
171    default: llvm_unreachable("Unknown addressing sub-mode!");
172    case ARM_AM::da: return 0;
173    case ARM_AM::ia: return 1;
174    case ARM_AM::db: return 2;
175    case ARM_AM::ib: return 3;
176    }
177  }
178  /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
179  ///
180  unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
181    switch (ShOpc) {
182    case ARM_AM::no_shift:
183    case ARM_AM::lsl: return 0;
184    case ARM_AM::lsr: return 1;
185    case ARM_AM::asr: return 2;
186    case ARM_AM::ror:
187    case ARM_AM::rrx: return 3;
188    }
189    llvm_unreachable("Invalid ShiftOpc!");
190  }
191
192  /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
193  uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
194                               SmallVectorImpl<MCFixup> &Fixups) const;
195
196  /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
197  uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
198                                     SmallVectorImpl<MCFixup> &Fixups) const;
199
200  /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
201  uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
202                                SmallVectorImpl<MCFixup> &Fixups) const;
203
204  /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
205  uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
206                                     SmallVectorImpl<MCFixup> &Fixups) const;
207
208  /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
209  uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
210                               SmallVectorImpl<MCFixup> &Fixups) const;
211
212  /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
213  /// operand.
214  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
215                                     SmallVectorImpl<MCFixup> &Fixups) const;
216
217  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
218  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
219                                SmallVectorImpl<MCFixup> &Fixups) const;
220
221  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
222  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
223                                SmallVectorImpl<MCFixup> &Fixups) const;
224
225  /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
226  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
227                               SmallVectorImpl<MCFixup> &Fixups) const;
228
229  /// getCCOutOpValue - Return encoding of the 's' bit.
230  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
231                           SmallVectorImpl<MCFixup> &Fixups) const {
232    // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
233    // '1' respectively.
234    return MI.getOperand(Op).getReg() == ARM::CPSR;
235  }
236
237  /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
238  unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
239                           SmallVectorImpl<MCFixup> &Fixups) const {
240    unsigned SoImm = MI.getOperand(Op).getImm();
241    int SoImmVal = ARM_AM::getSOImmVal(SoImm);
242    assert(SoImmVal != -1 && "Not a valid so_imm value!");
243
244    // Encode rotate_imm.
245    unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
246      << ARMII::SoRotImmShift;
247
248    // Encode immed_8.
249    Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
250    return Binary;
251  }
252
253  /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
254  unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
255                           SmallVectorImpl<MCFixup> &Fixups) const {
256    unsigned SoImm = MI.getOperand(Op).getImm();
257    unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
258    assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
259    return Encoded;
260  }
261
262  unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
263    SmallVectorImpl<MCFixup> &Fixups) const;
264  unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
265    SmallVectorImpl<MCFixup> &Fixups) const;
266  unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
267    SmallVectorImpl<MCFixup> &Fixups) const;
268  unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
269    SmallVectorImpl<MCFixup> &Fixups) const;
270
271  /// getSORegOpValue - Return an encoded so_reg shifted register value.
272  unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
273                           SmallVectorImpl<MCFixup> &Fixups) const;
274  unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
275                           SmallVectorImpl<MCFixup> &Fixups) const;
276  unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
277                             SmallVectorImpl<MCFixup> &Fixups) const;
278
279  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
280                                   SmallVectorImpl<MCFixup> &Fixups) const {
281    return 64 - MI.getOperand(Op).getImm();
282  }
283
284  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
285                                      SmallVectorImpl<MCFixup> &Fixups) const;
286
287  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
288                                  SmallVectorImpl<MCFixup> &Fixups) const;
289  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
290                                      SmallVectorImpl<MCFixup> &Fixups) const;
291  unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
292                                        SmallVectorImpl<MCFixup> &Fixups) const;
293  unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
294                                        SmallVectorImpl<MCFixup> &Fixups) const;
295  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
296                                     SmallVectorImpl<MCFixup> &Fixups) const;
297
298  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
299                             SmallVectorImpl<MCFixup> &Fixups) const;
300  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
301                              SmallVectorImpl<MCFixup> &Fixups) const;
302  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
303                              SmallVectorImpl<MCFixup> &Fixups) const;
304  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
305                              SmallVectorImpl<MCFixup> &Fixups) const;
306
307  unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
308                                 SmallVectorImpl<MCFixup> &Fixups) const;
309
310  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
311                                      unsigned EncodedValue) const;
312  unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
313                                          unsigned EncodedValue) const;
314  unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
315                                    unsigned EncodedValue) const;
316
317  unsigned VFPThumb2PostEncoder(const MCInst &MI,
318                                unsigned EncodedValue) const;
319
320  void EmitByte(unsigned char C, raw_ostream &OS) const {
321    OS << (char)C;
322  }
323
324  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
325    // Output the constant in little endian byte order.
326    for (unsigned i = 0; i != Size; ++i) {
327      EmitByte(Val & 255, OS);
328      Val >>= 8;
329    }
330  }
331
332  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
333                         SmallVectorImpl<MCFixup> &Fixups) const;
334};
335
336} // end anonymous namespace
337
338MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
339                                            const MCSubtargetInfo &STI,
340                                            MCContext &Ctx) {
341  return new ARMMCCodeEmitter(MCII, STI, Ctx);
342}
343
344/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
345/// instructions, and rewrite them to their Thumb2 form if we are currently in
346/// Thumb2 mode.
347unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
348                                                 unsigned EncodedValue) const {
349  if (isThumb2()) {
350    // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
351    // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
352    // set to 1111.
353    unsigned Bit24 = EncodedValue & 0x01000000;
354    unsigned Bit28 = Bit24 << 4;
355    EncodedValue &= 0xEFFFFFFF;
356    EncodedValue |= Bit28;
357    EncodedValue |= 0x0F000000;
358  }
359
360  return EncodedValue;
361}
362
363/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
364/// instructions, and rewrite them to their Thumb2 form if we are currently in
365/// Thumb2 mode.
366unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
367                                                 unsigned EncodedValue) const {
368  if (isThumb2()) {
369    EncodedValue &= 0xF0FFFFFF;
370    EncodedValue |= 0x09000000;
371  }
372
373  return EncodedValue;
374}
375
376/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
377/// instructions, and rewrite them to their Thumb2 form if we are currently in
378/// Thumb2 mode.
379unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
380                                                 unsigned EncodedValue) const {
381  if (isThumb2()) {
382    EncodedValue &= 0x00FFFFFF;
383    EncodedValue |= 0xEE000000;
384  }
385
386  return EncodedValue;
387}
388
389/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
390/// them to their Thumb2 form if we are currently in Thumb2 mode.
391unsigned ARMMCCodeEmitter::
392VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
393  if (isThumb2()) {
394    EncodedValue &= 0x0FFFFFFF;
395    EncodedValue |= 0xE0000000;
396  }
397  return EncodedValue;
398}
399
400/// getMachineOpValue - Return binary encoding of operand. If the machine
401/// operand requires relocation, record the relocation and return zero.
402unsigned ARMMCCodeEmitter::
403getMachineOpValue(const MCInst &MI, const MCOperand &MO,
404                  SmallVectorImpl<MCFixup> &Fixups) const {
405  if (MO.isReg()) {
406    unsigned Reg = MO.getReg();
407    unsigned RegNo = getARMRegisterNumbering(Reg);
408
409    // Q registers are encoded as 2x their register number.
410    switch (Reg) {
411    default:
412      return RegNo;
413    case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
414    case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
415    case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
416    case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
417      return 2 * RegNo;
418    }
419  } else if (MO.isImm()) {
420    return static_cast<unsigned>(MO.getImm());
421  } else if (MO.isFPImm()) {
422    return static_cast<unsigned>(APFloat(MO.getFPImm())
423                     .bitcastToAPInt().getHiBits(32).getLimitedValue());
424  }
425
426  llvm_unreachable("Unable to encode MCOperand!");
427}
428
429/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
430bool ARMMCCodeEmitter::
431EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
432                       unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
433  const MCOperand &MO  = MI.getOperand(OpIdx);
434  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
435
436  Reg = getARMRegisterNumbering(MO.getReg());
437
438  int32_t SImm = MO1.getImm();
439  bool isAdd = true;
440
441  // Special value for #-0
442  if (SImm == INT32_MIN) {
443    SImm = 0;
444    isAdd = false;
445  }
446
447  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
448  if (SImm < 0) {
449    SImm = -SImm;
450    isAdd = false;
451  }
452
453  Imm = SImm;
454  return isAdd;
455}
456
457/// getBranchTargetOpValue - Helper function to get the branch target operand,
458/// which is either an immediate or requires a fixup.
459static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
460                                       unsigned FixupKind,
461                                       SmallVectorImpl<MCFixup> &Fixups) {
462  const MCOperand &MO = MI.getOperand(OpIdx);
463
464  // If the destination is an immediate, we have nothing to do.
465  if (MO.isImm()) return MO.getImm();
466  assert(MO.isExpr() && "Unexpected branch target type!");
467  const MCExpr *Expr = MO.getExpr();
468  MCFixupKind Kind = MCFixupKind(FixupKind);
469  Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
470
471  // All of the information is in the fixup.
472  return 0;
473}
474
475// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
476// determined by negating them and XOR'ing them with bit 23.
477static int32_t encodeThumbBLOffset(int32_t offset) {
478  offset >>= 1;
479  uint32_t S  = (offset & 0x800000) >> 23;
480  uint32_t J1 = (offset & 0x400000) >> 22;
481  uint32_t J2 = (offset & 0x200000) >> 21;
482  J1 = (~J1 & 0x1);
483  J2 = (~J2 & 0x1);
484  J1 ^= S;
485  J2 ^= S;
486
487  offset &= ~0x600000;
488  offset |= J1 << 22;
489  offset |= J2 << 21;
490
491  return offset;
492}
493
494/// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
495uint32_t ARMMCCodeEmitter::
496getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
497                        SmallVectorImpl<MCFixup> &Fixups) const {
498  const MCOperand MO = MI.getOperand(OpIdx);
499  if (MO.isExpr())
500    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
501                                    Fixups);
502  return encodeThumbBLOffset(MO.getImm());
503}
504
505/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
506/// BLX branch target.
507uint32_t ARMMCCodeEmitter::
508getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
509                         SmallVectorImpl<MCFixup> &Fixups) const {
510  const MCOperand MO = MI.getOperand(OpIdx);
511  if (MO.isExpr())
512    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
513                                    Fixups);
514  return encodeThumbBLOffset(MO.getImm());
515}
516
517/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
518uint32_t ARMMCCodeEmitter::
519getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
520                        SmallVectorImpl<MCFixup> &Fixups) const {
521  const MCOperand MO = MI.getOperand(OpIdx);
522  if (MO.isExpr())
523    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
524                                    Fixups);
525  return (MO.getImm() >> 1);
526}
527
528/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
529uint32_t ARMMCCodeEmitter::
530getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
531                         SmallVectorImpl<MCFixup> &Fixups) const {
532  const MCOperand MO = MI.getOperand(OpIdx);
533  if (MO.isExpr())
534    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
535                                    Fixups);
536  return (MO.getImm() >> 1);
537}
538
539/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
540uint32_t ARMMCCodeEmitter::
541getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
542                        SmallVectorImpl<MCFixup> &Fixups) const {
543  const MCOperand MO = MI.getOperand(OpIdx);
544  if (MO.isExpr())
545    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
546  return (MO.getImm() >> 1);
547}
548
549/// Return true if this branch has a non-always predication
550static bool HasConditionalBranch(const MCInst &MI) {
551  int NumOp = MI.getNumOperands();
552  if (NumOp >= 2) {
553    for (int i = 0; i < NumOp-1; ++i) {
554      const MCOperand &MCOp1 = MI.getOperand(i);
555      const MCOperand &MCOp2 = MI.getOperand(i + 1);
556      if (MCOp1.isImm() && MCOp2.isReg() &&
557          (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
558        if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
559          return true;
560      }
561    }
562  }
563  return false;
564}
565
566/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
567/// target.
568uint32_t ARMMCCodeEmitter::
569getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
570                       SmallVectorImpl<MCFixup> &Fixups) const {
571  // FIXME: This really, really shouldn't use TargetMachine. We don't want
572  // coupling between MC and TM anywhere we can help it.
573  if (isThumb2())
574    return
575      ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
576  return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
577}
578
579/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
580/// target.
581uint32_t ARMMCCodeEmitter::
582getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
583                          SmallVectorImpl<MCFixup> &Fixups) const {
584  const MCOperand MO = MI.getOperand(OpIdx);
585  if (MO.isExpr()) {
586    if (HasConditionalBranch(MI))
587      return ::getBranchTargetOpValue(MI, OpIdx,
588                                      ARM::fixup_arm_condbranch, Fixups);
589    return ::getBranchTargetOpValue(MI, OpIdx,
590                                    ARM::fixup_arm_uncondbranch, Fixups);
591  }
592
593  return MO.getImm() >> 2;
594}
595
596uint32_t ARMMCCodeEmitter::
597getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
598                          SmallVectorImpl<MCFixup> &Fixups) const {
599  const MCOperand MO = MI.getOperand(OpIdx);
600  if (MO.isExpr()) {
601    if (HasConditionalBranch(MI))
602      return ::getBranchTargetOpValue(MI, OpIdx,
603                                      ARM::fixup_arm_condbl, Fixups);
604    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups);
605  }
606
607  return MO.getImm() >> 2;
608}
609
610uint32_t ARMMCCodeEmitter::
611getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
612                          SmallVectorImpl<MCFixup> &Fixups) const {
613  const MCOperand MO = MI.getOperand(OpIdx);
614  if (MO.isExpr())
615    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups);
616
617  return MO.getImm() >> 1;
618}
619
620/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
621/// immediate branch target.
622uint32_t ARMMCCodeEmitter::
623getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
624                       SmallVectorImpl<MCFixup> &Fixups) const {
625  unsigned Val =
626    ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
627  bool I  = (Val & 0x800000);
628  bool J1 = (Val & 0x400000);
629  bool J2 = (Val & 0x200000);
630  if (I ^ J1)
631    Val &= ~0x400000;
632  else
633    Val |= 0x400000;
634
635  if (I ^ J2)
636    Val &= ~0x200000;
637  else
638    Val |= 0x200000;
639
640  return Val;
641}
642
643/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
644/// target.
645uint32_t ARMMCCodeEmitter::
646getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
647                   SmallVectorImpl<MCFixup> &Fixups) const {
648  const MCOperand MO = MI.getOperand(OpIdx);
649  if (MO.isExpr())
650    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
651                                    Fixups);
652  int32_t offset = MO.getImm();
653  uint32_t Val = 0x2000;
654  if (offset < 0) {
655    Val = 0x1000;
656    offset *= -1;
657  }
658  Val |= offset;
659  return Val;
660}
661
662/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
663/// target.
664uint32_t ARMMCCodeEmitter::
665getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
666                   SmallVectorImpl<MCFixup> &Fixups) const {
667  const MCOperand MO = MI.getOperand(OpIdx);
668  if (MO.isExpr())
669    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
670                                    Fixups);
671  int32_t Val = MO.getImm();
672  if (Val < 0) {
673    Val *= -1;
674    Val |= 0x1000;
675  }
676  return Val;
677}
678
679/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
680/// target.
681uint32_t ARMMCCodeEmitter::
682getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
683                   SmallVectorImpl<MCFixup> &Fixups) const {
684  const MCOperand MO = MI.getOperand(OpIdx);
685  if (MO.isExpr())
686    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
687                                    Fixups);
688  return MO.getImm();
689}
690
691/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
692/// operand.
693uint32_t ARMMCCodeEmitter::
694getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
695                              SmallVectorImpl<MCFixup> &) const {
696  // [Rn, Rm]
697  //   {5-3} = Rm
698  //   {2-0} = Rn
699  const MCOperand &MO1 = MI.getOperand(OpIdx);
700  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
701  unsigned Rn = getARMRegisterNumbering(MO1.getReg());
702  unsigned Rm = getARMRegisterNumbering(MO2.getReg());
703  return (Rm << 3) | Rn;
704}
705
706/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
707uint32_t ARMMCCodeEmitter::
708getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
709                        SmallVectorImpl<MCFixup> &Fixups) const {
710  // {17-13} = reg
711  // {12}    = (U)nsigned (add == '1', sub == '0')
712  // {11-0}  = imm12
713  unsigned Reg, Imm12;
714  bool isAdd = true;
715  // If The first operand isn't a register, we have a label reference.
716  const MCOperand &MO = MI.getOperand(OpIdx);
717  if (!MO.isReg()) {
718    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
719    Imm12 = 0;
720    isAdd = false ; // 'U' bit is set as part of the fixup.
721
722    if (MO.isExpr()) {
723      const MCExpr *Expr = MO.getExpr();
724
725      MCFixupKind Kind;
726      if (isThumb2())
727        Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
728      else
729        Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
730      Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
731
732      ++MCNumCPRelocations;
733    } else {
734      Reg = ARM::PC;
735      int32_t Offset = MO.getImm();
736      // FIXME: Handle #-0.
737      if (Offset < 0) {
738        Offset *= -1;
739        isAdd = false;
740      }
741      Imm12 = Offset;
742    }
743  } else
744    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
745
746  uint32_t Binary = Imm12 & 0xfff;
747  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
748  if (isAdd)
749    Binary |= (1 << 12);
750  Binary |= (Reg << 13);
751  return Binary;
752}
753
754/// getT2Imm8s4OpValue - Return encoding info for
755/// '+/- imm8<<2' operand.
756uint32_t ARMMCCodeEmitter::
757getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
758                   SmallVectorImpl<MCFixup> &Fixups) const {
759  // FIXME: The immediate operand should have already been encoded like this
760  // before ever getting here. The encoder method should just need to combine
761  // the MI operands for the register and the offset into a single
762  // representation for the complex operand in the .td file. This isn't just
763  // style, unfortunately. As-is, we can't represent the distinct encoding
764  // for #-0.
765
766  // {8}    = (U)nsigned (add == '1', sub == '0')
767  // {7-0}  = imm8
768  int32_t Imm8 = MI.getOperand(OpIdx).getImm();
769  bool isAdd = Imm8 >= 0;
770
771  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
772  if (Imm8 < 0)
773    Imm8 = -Imm8;
774
775  // Scaled by 4.
776  Imm8 /= 4;
777
778  uint32_t Binary = Imm8 & 0xff;
779  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
780  if (isAdd)
781    Binary |= (1 << 8);
782  return Binary;
783}
784
785/// getT2AddrModeImm8s4OpValue - Return encoding info for
786/// 'reg +/- imm8<<2' operand.
787uint32_t ARMMCCodeEmitter::
788getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
789                        SmallVectorImpl<MCFixup> &Fixups) const {
790  // {12-9} = reg
791  // {8}    = (U)nsigned (add == '1', sub == '0')
792  // {7-0}  = imm8
793  unsigned Reg, Imm8;
794  bool isAdd = true;
795  // If The first operand isn't a register, we have a label reference.
796  const MCOperand &MO = MI.getOperand(OpIdx);
797  if (!MO.isReg()) {
798    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
799    Imm8 = 0;
800    isAdd = false ; // 'U' bit is set as part of the fixup.
801
802    assert(MO.isExpr() && "Unexpected machine operand type!");
803    const MCExpr *Expr = MO.getExpr();
804    MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
805    Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
806
807    ++MCNumCPRelocations;
808  } else
809    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
810
811  // FIXME: The immediate operand should have already been encoded like this
812  // before ever getting here. The encoder method should just need to combine
813  // the MI operands for the register and the offset into a single
814  // representation for the complex operand in the .td file. This isn't just
815  // style, unfortunately. As-is, we can't represent the distinct encoding
816  // for #-0.
817  uint32_t Binary = (Imm8 >> 2) & 0xff;
818  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
819  if (isAdd)
820    Binary |= (1 << 8);
821  Binary |= (Reg << 9);
822  return Binary;
823}
824
825/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
826/// 'reg + imm8<<2' operand.
827uint32_t ARMMCCodeEmitter::
828getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
829                        SmallVectorImpl<MCFixup> &Fixups) const {
830  // {11-8} = reg
831  // {7-0}  = imm8
832  const MCOperand &MO = MI.getOperand(OpIdx);
833  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
834  unsigned Reg = getARMRegisterNumbering(MO.getReg());
835  unsigned Imm8 = MO1.getImm();
836  return (Reg << 8) | Imm8;
837}
838
839// FIXME: This routine assumes that a binary
840// expression will always result in a PCRel expression
841// In reality, its only true if one or more subexpressions
842// is itself a PCRel (i.e. "." in asm or some other pcrel construct)
843// but this is good enough for now.
844static bool EvaluateAsPCRel(const MCExpr *Expr) {
845  switch (Expr->getKind()) {
846  default: llvm_unreachable("Unexpected expression type");
847  case MCExpr::SymbolRef: return false;
848  case MCExpr::Binary: return true;
849  }
850}
851
852uint32_t
853ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
854                                      SmallVectorImpl<MCFixup> &Fixups) const {
855  // {20-16} = imm{15-12}
856  // {11-0}  = imm{11-0}
857  const MCOperand &MO = MI.getOperand(OpIdx);
858  if (MO.isImm())
859    // Hi / lo 16 bits already extracted during earlier passes.
860    return static_cast<unsigned>(MO.getImm());
861
862  // Handle :upper16: and :lower16: assembly prefixes.
863  const MCExpr *E = MO.getExpr();
864  if (E->getKind() == MCExpr::Target) {
865    const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
866    E = ARM16Expr->getSubExpr();
867
868    MCFixupKind Kind;
869    switch (ARM16Expr->getKind()) {
870    default: llvm_unreachable("Unsupported ARMFixup");
871    case ARMMCExpr::VK_ARM_HI16:
872      if (!isTargetDarwin() && EvaluateAsPCRel(E))
873        Kind = MCFixupKind(isThumb2()
874                           ? ARM::fixup_t2_movt_hi16_pcrel
875                           : ARM::fixup_arm_movt_hi16_pcrel);
876      else
877        Kind = MCFixupKind(isThumb2()
878                           ? ARM::fixup_t2_movt_hi16
879                           : ARM::fixup_arm_movt_hi16);
880      break;
881    case ARMMCExpr::VK_ARM_LO16:
882      if (!isTargetDarwin() && EvaluateAsPCRel(E))
883        Kind = MCFixupKind(isThumb2()
884                           ? ARM::fixup_t2_movw_lo16_pcrel
885                           : ARM::fixup_arm_movw_lo16_pcrel);
886      else
887        Kind = MCFixupKind(isThumb2()
888                           ? ARM::fixup_t2_movw_lo16
889                           : ARM::fixup_arm_movw_lo16);
890      break;
891    }
892    Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
893    return 0;
894  };
895
896  llvm_unreachable("Unsupported MCExpr type in MCOperand!");
897}
898
899uint32_t ARMMCCodeEmitter::
900getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
901                    SmallVectorImpl<MCFixup> &Fixups) const {
902  const MCOperand &MO = MI.getOperand(OpIdx);
903  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
904  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
905  unsigned Rn = getARMRegisterNumbering(MO.getReg());
906  unsigned Rm = getARMRegisterNumbering(MO1.getReg());
907  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
908  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
909  ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
910  unsigned SBits = getShiftOp(ShOp);
911
912  // {16-13} = Rn
913  // {12}    = isAdd
914  // {11-0}  = shifter
915  //  {3-0}  = Rm
916  //  {4}    = 0
917  //  {6-5}  = type
918  //  {11-7} = imm
919  uint32_t Binary = Rm;
920  Binary |= Rn << 13;
921  Binary |= SBits << 5;
922  Binary |= ShImm << 7;
923  if (isAdd)
924    Binary |= 1 << 12;
925  return Binary;
926}
927
928uint32_t ARMMCCodeEmitter::
929getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
930                    SmallVectorImpl<MCFixup> &Fixups) const {
931  // {17-14}  Rn
932  // {13}     1 == imm12, 0 == Rm
933  // {12}     isAdd
934  // {11-0}   imm12/Rm
935  const MCOperand &MO = MI.getOperand(OpIdx);
936  unsigned Rn = getARMRegisterNumbering(MO.getReg());
937  uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
938  Binary |= Rn << 14;
939  return Binary;
940}
941
942uint32_t ARMMCCodeEmitter::
943getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
944                          SmallVectorImpl<MCFixup> &Fixups) const {
945  // {13}     1 == imm12, 0 == Rm
946  // {12}     isAdd
947  // {11-0}   imm12/Rm
948  const MCOperand &MO = MI.getOperand(OpIdx);
949  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
950  unsigned Imm = MO1.getImm();
951  bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
952  bool isReg = MO.getReg() != 0;
953  uint32_t Binary = ARM_AM::getAM2Offset(Imm);
954  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
955  if (isReg) {
956    ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
957    Binary <<= 7;                    // Shift amount is bits [11:7]
958    Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
959    Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
960  }
961  return Binary | (isAdd << 12) | (isReg << 13);
962}
963
964uint32_t ARMMCCodeEmitter::
965getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
966                     SmallVectorImpl<MCFixup> &Fixups) const {
967  // {4}      isAdd
968  // {3-0}    Rm
969  const MCOperand &MO = MI.getOperand(OpIdx);
970  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
971  bool isAdd = MO1.getImm() != 0;
972  return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
973}
974
975uint32_t ARMMCCodeEmitter::
976getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
977                          SmallVectorImpl<MCFixup> &Fixups) const {
978  // {9}      1 == imm8, 0 == Rm
979  // {8}      isAdd
980  // {7-4}    imm7_4/zero
981  // {3-0}    imm3_0/Rm
982  const MCOperand &MO = MI.getOperand(OpIdx);
983  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
984  unsigned Imm = MO1.getImm();
985  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
986  bool isImm = MO.getReg() == 0;
987  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
988  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
989  if (!isImm)
990    Imm8 = getARMRegisterNumbering(MO.getReg());
991  return Imm8 | (isAdd << 8) | (isImm << 9);
992}
993
994uint32_t ARMMCCodeEmitter::
995getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
996                    SmallVectorImpl<MCFixup> &Fixups) const {
997  // {13}     1 == imm8, 0 == Rm
998  // {12-9}   Rn
999  // {8}      isAdd
1000  // {7-4}    imm7_4/zero
1001  // {3-0}    imm3_0/Rm
1002  const MCOperand &MO = MI.getOperand(OpIdx);
1003  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1004  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1005
1006  // If The first operand isn't a register, we have a label reference.
1007  if (!MO.isReg()) {
1008    unsigned Rn = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
1009
1010    assert(MO.isExpr() && "Unexpected machine operand type!");
1011    const MCExpr *Expr = MO.getExpr();
1012    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1013    Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1014
1015    ++MCNumCPRelocations;
1016    return (Rn << 9) | (1 << 13);
1017  }
1018  unsigned Rn = getARMRegisterNumbering(MO.getReg());
1019  unsigned Imm = MO2.getImm();
1020  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1021  bool isImm = MO1.getReg() == 0;
1022  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1023  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1024  if (!isImm)
1025    Imm8 = getARMRegisterNumbering(MO1.getReg());
1026  return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1027}
1028
1029/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1030uint32_t ARMMCCodeEmitter::
1031getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1032                          SmallVectorImpl<MCFixup> &Fixups) const {
1033  // [SP, #imm]
1034  //   {7-0} = imm8
1035  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1036  assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1037         "Unexpected base register!");
1038
1039  // The immediate is already shifted for the implicit zeroes, so no change
1040  // here.
1041  return MO1.getImm() & 0xff;
1042}
1043
1044/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1045uint32_t ARMMCCodeEmitter::
1046getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1047                     SmallVectorImpl<MCFixup> &Fixups) const {
1048  // [Rn, #imm]
1049  //   {7-3} = imm5
1050  //   {2-0} = Rn
1051  const MCOperand &MO = MI.getOperand(OpIdx);
1052  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1053  unsigned Rn = getARMRegisterNumbering(MO.getReg());
1054  unsigned Imm5 = MO1.getImm();
1055  return ((Imm5 & 0x1f) << 3) | Rn;
1056}
1057
1058/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1059uint32_t ARMMCCodeEmitter::
1060getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1061                     SmallVectorImpl<MCFixup> &Fixups) const {
1062  const MCOperand MO = MI.getOperand(OpIdx);
1063  if (MO.isExpr())
1064    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
1065  return (MO.getImm() >> 2);
1066}
1067
1068/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1069uint32_t ARMMCCodeEmitter::
1070getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1071                    SmallVectorImpl<MCFixup> &Fixups) const {
1072  // {12-9} = reg
1073  // {8}    = (U)nsigned (add == '1', sub == '0')
1074  // {7-0}  = imm8
1075  unsigned Reg, Imm8;
1076  bool isAdd;
1077  // If The first operand isn't a register, we have a label reference.
1078  const MCOperand &MO = MI.getOperand(OpIdx);
1079  if (!MO.isReg()) {
1080    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
1081    Imm8 = 0;
1082    isAdd = false; // 'U' bit is handled as part of the fixup.
1083
1084    assert(MO.isExpr() && "Unexpected machine operand type!");
1085    const MCExpr *Expr = MO.getExpr();
1086    MCFixupKind Kind;
1087    if (isThumb2())
1088      Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1089    else
1090      Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1091    Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
1092
1093    ++MCNumCPRelocations;
1094  } else {
1095    EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
1096    isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1097  }
1098
1099  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1100  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1101  if (isAdd)
1102    Binary |= (1 << 8);
1103  Binary |= (Reg << 9);
1104  return Binary;
1105}
1106
1107unsigned ARMMCCodeEmitter::
1108getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1109                SmallVectorImpl<MCFixup> &Fixups) const {
1110  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1111  // shifted. The second is Rs, the amount to shift by, and the third specifies
1112  // the type of the shift.
1113  //
1114  // {3-0} = Rm.
1115  // {4}   = 1
1116  // {6-5} = type
1117  // {11-8} = Rs
1118  // {7}    = 0
1119
1120  const MCOperand &MO  = MI.getOperand(OpIdx);
1121  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1122  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1123  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1124
1125  // Encode Rm.
1126  unsigned Binary = getARMRegisterNumbering(MO.getReg());
1127
1128  // Encode the shift opcode.
1129  unsigned SBits = 0;
1130  unsigned Rs = MO1.getReg();
1131  if (Rs) {
1132    // Set shift operand (bit[7:4]).
1133    // LSL - 0001
1134    // LSR - 0011
1135    // ASR - 0101
1136    // ROR - 0111
1137    switch (SOpc) {
1138    default: llvm_unreachable("Unknown shift opc!");
1139    case ARM_AM::lsl: SBits = 0x1; break;
1140    case ARM_AM::lsr: SBits = 0x3; break;
1141    case ARM_AM::asr: SBits = 0x5; break;
1142    case ARM_AM::ror: SBits = 0x7; break;
1143    }
1144  }
1145
1146  Binary |= SBits << 4;
1147
1148  // Encode the shift operation Rs.
1149  // Encode Rs bit[11:8].
1150  assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1151  return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1152}
1153
1154unsigned ARMMCCodeEmitter::
1155getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1156                SmallVectorImpl<MCFixup> &Fixups) const {
1157  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1158  // shifted. The second is the amount to shift by.
1159  //
1160  // {3-0} = Rm.
1161  // {4}   = 0
1162  // {6-5} = type
1163  // {11-7} = imm
1164
1165  const MCOperand &MO  = MI.getOperand(OpIdx);
1166  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1167  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1168
1169  // Encode Rm.
1170  unsigned Binary = getARMRegisterNumbering(MO.getReg());
1171
1172  // Encode the shift opcode.
1173  unsigned SBits = 0;
1174
1175  // Set shift operand (bit[6:4]).
1176  // LSL - 000
1177  // LSR - 010
1178  // ASR - 100
1179  // ROR - 110
1180  // RRX - 110 and bit[11:8] clear.
1181  switch (SOpc) {
1182  default: llvm_unreachable("Unknown shift opc!");
1183  case ARM_AM::lsl: SBits = 0x0; break;
1184  case ARM_AM::lsr: SBits = 0x2; break;
1185  case ARM_AM::asr: SBits = 0x4; break;
1186  case ARM_AM::ror: SBits = 0x6; break;
1187  case ARM_AM::rrx:
1188    Binary |= 0x60;
1189    return Binary;
1190  }
1191
1192  // Encode shift_imm bit[11:7].
1193  Binary |= SBits << 4;
1194  unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1195  assert(Offset && "Offset must be in range 1-32!");
1196  if (Offset == 32) Offset = 0;
1197  return Binary | (Offset << 7);
1198}
1199
1200
1201unsigned ARMMCCodeEmitter::
1202getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1203                SmallVectorImpl<MCFixup> &Fixups) const {
1204  const MCOperand &MO1 = MI.getOperand(OpNum);
1205  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1206  const MCOperand &MO3 = MI.getOperand(OpNum+2);
1207
1208  // Encoded as [Rn, Rm, imm].
1209  // FIXME: Needs fixup support.
1210  unsigned Value = getARMRegisterNumbering(MO1.getReg());
1211  Value <<= 4;
1212  Value |= getARMRegisterNumbering(MO2.getReg());
1213  Value <<= 2;
1214  Value |= MO3.getImm();
1215
1216  return Value;
1217}
1218
1219unsigned ARMMCCodeEmitter::
1220getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1221                         SmallVectorImpl<MCFixup> &Fixups) const {
1222  const MCOperand &MO1 = MI.getOperand(OpNum);
1223  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1224
1225  // FIXME: Needs fixup support.
1226  unsigned Value = getARMRegisterNumbering(MO1.getReg());
1227
1228  // Even though the immediate is 8 bits long, we need 9 bits in order
1229  // to represent the (inverse of the) sign bit.
1230  Value <<= 9;
1231  int32_t tmp = (int32_t)MO2.getImm();
1232  if (tmp < 0)
1233    tmp = abs(tmp);
1234  else
1235    Value |= 256; // Set the ADD bit
1236  Value |= tmp & 255;
1237  return Value;
1238}
1239
1240unsigned ARMMCCodeEmitter::
1241getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1242                         SmallVectorImpl<MCFixup> &Fixups) const {
1243  const MCOperand &MO1 = MI.getOperand(OpNum);
1244
1245  // FIXME: Needs fixup support.
1246  unsigned Value = 0;
1247  int32_t tmp = (int32_t)MO1.getImm();
1248  if (tmp < 0)
1249    tmp = abs(tmp);
1250  else
1251    Value |= 256; // Set the ADD bit
1252  Value |= tmp & 255;
1253  return Value;
1254}
1255
1256unsigned ARMMCCodeEmitter::
1257getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1258                         SmallVectorImpl<MCFixup> &Fixups) const {
1259  const MCOperand &MO1 = MI.getOperand(OpNum);
1260
1261  // FIXME: Needs fixup support.
1262  unsigned Value = 0;
1263  int32_t tmp = (int32_t)MO1.getImm();
1264  if (tmp < 0)
1265    tmp = abs(tmp);
1266  else
1267    Value |= 4096; // Set the ADD bit
1268  Value |= tmp & 4095;
1269  return Value;
1270}
1271
1272unsigned ARMMCCodeEmitter::
1273getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1274                SmallVectorImpl<MCFixup> &Fixups) const {
1275  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1276  // shifted. The second is the amount to shift by.
1277  //
1278  // {3-0} = Rm.
1279  // {4}   = 0
1280  // {6-5} = type
1281  // {11-7} = imm
1282
1283  const MCOperand &MO  = MI.getOperand(OpIdx);
1284  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1285  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1286
1287  // Encode Rm.
1288  unsigned Binary = getARMRegisterNumbering(MO.getReg());
1289
1290  // Encode the shift opcode.
1291  unsigned SBits = 0;
1292  // Set shift operand (bit[6:4]).
1293  // LSL - 000
1294  // LSR - 010
1295  // ASR - 100
1296  // ROR - 110
1297  switch (SOpc) {
1298  default: llvm_unreachable("Unknown shift opc!");
1299  case ARM_AM::lsl: SBits = 0x0; break;
1300  case ARM_AM::lsr: SBits = 0x2; break;
1301  case ARM_AM::asr: SBits = 0x4; break;
1302  case ARM_AM::rrx: // FALLTHROUGH
1303  case ARM_AM::ror: SBits = 0x6; break;
1304  }
1305
1306  Binary |= SBits << 4;
1307  if (SOpc == ARM_AM::rrx)
1308    return Binary;
1309
1310  // Encode shift_imm bit[11:7].
1311  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1312}
1313
1314unsigned ARMMCCodeEmitter::
1315getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1316                               SmallVectorImpl<MCFixup> &Fixups) const {
1317  // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1318  // msb of the mask.
1319  const MCOperand &MO = MI.getOperand(Op);
1320  uint32_t v = ~MO.getImm();
1321  uint32_t lsb = CountTrailingZeros_32(v);
1322  uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1323  assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1324  return lsb | (msb << 5);
1325}
1326
1327unsigned ARMMCCodeEmitter::
1328getRegisterListOpValue(const MCInst &MI, unsigned Op,
1329                       SmallVectorImpl<MCFixup> &Fixups) const {
1330  // VLDM/VSTM:
1331  //   {12-8} = Vd
1332  //   {7-0}  = Number of registers
1333  //
1334  // LDM/STM:
1335  //   {15-0}  = Bitfield of GPRs.
1336  unsigned Reg = MI.getOperand(Op).getReg();
1337  bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1338  bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1339
1340  unsigned Binary = 0;
1341
1342  if (SPRRegs || DPRRegs) {
1343    // VLDM/VSTM
1344    unsigned RegNo = getARMRegisterNumbering(Reg);
1345    unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1346    Binary |= (RegNo & 0x1f) << 8;
1347    if (SPRRegs)
1348      Binary |= NumRegs;
1349    else
1350      Binary |= NumRegs * 2;
1351  } else {
1352    for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1353      unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1354      Binary |= 1 << RegNo;
1355    }
1356  }
1357
1358  return Binary;
1359}
1360
1361/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1362/// with the alignment operand.
1363unsigned ARMMCCodeEmitter::
1364getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1365                           SmallVectorImpl<MCFixup> &Fixups) const {
1366  const MCOperand &Reg = MI.getOperand(Op);
1367  const MCOperand &Imm = MI.getOperand(Op + 1);
1368
1369  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1370  unsigned Align = 0;
1371
1372  switch (Imm.getImm()) {
1373  default: break;
1374  case 2:
1375  case 4:
1376  case 8:  Align = 0x01; break;
1377  case 16: Align = 0x02; break;
1378  case 32: Align = 0x03; break;
1379  }
1380
1381  return RegNo | (Align << 4);
1382}
1383
1384/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1385/// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1386unsigned ARMMCCodeEmitter::
1387getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1388                                    SmallVectorImpl<MCFixup> &Fixups) const {
1389  const MCOperand &Reg = MI.getOperand(Op);
1390  const MCOperand &Imm = MI.getOperand(Op + 1);
1391
1392  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1393  unsigned Align = 0;
1394
1395  switch (Imm.getImm()) {
1396  default: break;
1397  case 8:
1398  case 16:
1399  case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1400  case 2: Align = 0x00; break;
1401  case 4: Align = 0x03; break;
1402  }
1403
1404  return RegNo | (Align << 4);
1405}
1406
1407
1408/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1409/// alignment operand for use in VLD-dup instructions.  This is the same as
1410/// getAddrMode6AddressOpValue except for the alignment encoding, which is
1411/// different for VLD4-dup.
1412unsigned ARMMCCodeEmitter::
1413getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1414                              SmallVectorImpl<MCFixup> &Fixups) const {
1415  const MCOperand &Reg = MI.getOperand(Op);
1416  const MCOperand &Imm = MI.getOperand(Op + 1);
1417
1418  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1419  unsigned Align = 0;
1420
1421  switch (Imm.getImm()) {
1422  default: break;
1423  case 2:
1424  case 4:
1425  case 8:  Align = 0x01; break;
1426  case 16: Align = 0x03; break;
1427  }
1428
1429  return RegNo | (Align << 4);
1430}
1431
1432unsigned ARMMCCodeEmitter::
1433getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1434                          SmallVectorImpl<MCFixup> &Fixups) const {
1435  const MCOperand &MO = MI.getOperand(Op);
1436  if (MO.getReg() == 0) return 0x0D;
1437  return getARMRegisterNumbering(MO.getReg());
1438}
1439
1440unsigned ARMMCCodeEmitter::
1441getShiftRight8Imm(const MCInst &MI, unsigned Op,
1442                  SmallVectorImpl<MCFixup> &Fixups) const {
1443  return 8 - MI.getOperand(Op).getImm();
1444}
1445
1446unsigned ARMMCCodeEmitter::
1447getShiftRight16Imm(const MCInst &MI, unsigned Op,
1448                   SmallVectorImpl<MCFixup> &Fixups) const {
1449  return 16 - MI.getOperand(Op).getImm();
1450}
1451
1452unsigned ARMMCCodeEmitter::
1453getShiftRight32Imm(const MCInst &MI, unsigned Op,
1454                   SmallVectorImpl<MCFixup> &Fixups) const {
1455  return 32 - MI.getOperand(Op).getImm();
1456}
1457
1458unsigned ARMMCCodeEmitter::
1459getShiftRight64Imm(const MCInst &MI, unsigned Op,
1460                   SmallVectorImpl<MCFixup> &Fixups) const {
1461  return 64 - MI.getOperand(Op).getImm();
1462}
1463
1464void ARMMCCodeEmitter::
1465EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1466                  SmallVectorImpl<MCFixup> &Fixups) const {
1467  // Pseudo instructions don't get encoded.
1468  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1469  uint64_t TSFlags = Desc.TSFlags;
1470  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1471    return;
1472
1473  int Size;
1474  if (Desc.getSize() == 2 || Desc.getSize() == 4)
1475    Size = Desc.getSize();
1476  else
1477    llvm_unreachable("Unexpected instruction size!");
1478
1479  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1480  // Thumb 32-bit wide instructions need to emit the high order halfword
1481  // first.
1482  if (isThumb() && Size == 4) {
1483    EmitConstant(Binary >> 16, 2, OS);
1484    EmitConstant(Binary & 0xffff, 2, OS);
1485  } else
1486    EmitConstant(Binary, Size, OS);
1487  ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1488}
1489
1490#include "ARMGenMCCodeEmitter.inc"
1491