ARMMCCodeEmitter.cpp revision f1eab597b2316c6cfcabfcee98895fedb2071722 
1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARMMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "MCTargetDesc/ARMFixupKinds.h"
18#include "MCTargetDesc/ARMMCExpr.h"
19#include "MCTargetDesc/ARMMCTargetDesc.h"
20#include "llvm/MC/MCCodeEmitter.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/Support/raw_ostream.h"
29
30using namespace llvm;
31
32STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
33STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
34
35namespace {
36class ARMMCCodeEmitter : public MCCodeEmitter {
37  ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
38  void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
39  const MCInstrInfo &MCII;
40  const MCSubtargetInfo &STI;
41
42public:
43  ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
44                   MCContext &ctx)
45    : MCII(mcii), STI(sti) {
46  }
47
48  ~ARMMCCodeEmitter() {}
49
50  bool isThumb() const {
51    // FIXME: Can tablegen auto-generate this?
52    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
53  }
54  bool isThumb2() const {
55    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
56  }
57  bool isTargetDarwin() const {
58    Triple TT(STI.getTargetTriple());
59    Triple::OSType OS = TT.getOS();
60    return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS;
61  }
62
63  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
64
65  // getBinaryCodeForInstr - TableGen'erated function for getting the
66  // binary encoding for an instruction.
67  unsigned getBinaryCodeForInstr(const MCInst &MI,
68                                 SmallVectorImpl<MCFixup> &Fixups) const;
69
70  /// getMachineOpValue - Return binary encoding of operand. If the machine
71  /// operand requires relocation, record the relocation and return zero.
72  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73                             SmallVectorImpl<MCFixup> &Fixups) const;
74
75  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
76  /// the specified operand. This is used for operands with :lower16: and
77  /// :upper16: prefixes.
78  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
79                               SmallVectorImpl<MCFixup> &Fixups) const;
80
81  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
82                              unsigned &Reg, unsigned &Imm,
83                              SmallVectorImpl<MCFixup> &Fixups) const;
84
85  /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
86  /// BL branch target.
87  uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
88                                   SmallVectorImpl<MCFixup> &Fixups) const;
89
90  /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
91  /// BLX branch target.
92  uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
93                                    SmallVectorImpl<MCFixup> &Fixups) const;
94
95  /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
96  uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
97                                   SmallVectorImpl<MCFixup> &Fixups) const;
98
99  /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
100  uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
101                                    SmallVectorImpl<MCFixup> &Fixups) const;
102
103  /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104  uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105                                   SmallVectorImpl<MCFixup> &Fixups) const;
106
107  /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
108  /// branch target.
109  uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110                                  SmallVectorImpl<MCFixup> &Fixups) const;
111
112  /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
113  /// immediate Thumb2 direct branch target.
114  uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
115                                  SmallVectorImpl<MCFixup> &Fixups) const;
116
117  /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
118  /// branch target.
119  uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120                                     SmallVectorImpl<MCFixup> &Fixups) const;
121  uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
122                                     SmallVectorImpl<MCFixup> &Fixups) const;
123
124  /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
125  /// ADR label target.
126  uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
127                              SmallVectorImpl<MCFixup> &Fixups) const;
128  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129                              SmallVectorImpl<MCFixup> &Fixups) const;
130  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
131                              SmallVectorImpl<MCFixup> &Fixups) const;
132
133
134  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
135  /// operand.
136  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
137                                   SmallVectorImpl<MCFixup> &Fixups) const;
138
139  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
140  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
141                                         SmallVectorImpl<MCFixup> &Fixups)const;
142
143  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
144  /// operand.
145  uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
146                                   SmallVectorImpl<MCFixup> &Fixups) const;
147
148
149  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
150  /// operand as needed by load/store instructions.
151  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
152                               SmallVectorImpl<MCFixup> &Fixups) const;
153
154  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
155  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
156                               SmallVectorImpl<MCFixup> &Fixups) const {
157    ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
158    switch (Mode) {
159    default: assert(0 && "Unknown addressing sub-mode!");
160    case ARM_AM::da: return 0;
161    case ARM_AM::ia: return 1;
162    case ARM_AM::db: return 2;
163    case ARM_AM::ib: return 3;
164    }
165  }
166  /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
167  ///
168  unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
169    switch (ShOpc) {
170    default: llvm_unreachable("Unknown shift opc!");
171    case ARM_AM::no_shift:
172    case ARM_AM::lsl: return 0;
173    case ARM_AM::lsr: return 1;
174    case ARM_AM::asr: return 2;
175    case ARM_AM::ror:
176    case ARM_AM::rrx: return 3;
177    }
178    return 0;
179  }
180
181  /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
182  uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
183                               SmallVectorImpl<MCFixup> &Fixups) const;
184
185  /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
186  uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
187                                     SmallVectorImpl<MCFixup> &Fixups) const;
188
189  /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
190  uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
191                                SmallVectorImpl<MCFixup> &Fixups) const;
192
193  /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
194  uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
195                                     SmallVectorImpl<MCFixup> &Fixups) const;
196
197  /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
198  uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
199                               SmallVectorImpl<MCFixup> &Fixups) const;
200
201  /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
202  /// operand.
203  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
204                                     SmallVectorImpl<MCFixup> &Fixups) const;
205
206  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
207  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
208                                SmallVectorImpl<MCFixup> &Fixups) const;
209
210  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
211  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
212                                SmallVectorImpl<MCFixup> &Fixups) const;
213
214  /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
215  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
216                               SmallVectorImpl<MCFixup> &Fixups) const;
217
218  /// getCCOutOpValue - Return encoding of the 's' bit.
219  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
220                           SmallVectorImpl<MCFixup> &Fixups) const {
221    // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
222    // '1' respectively.
223    return MI.getOperand(Op).getReg() == ARM::CPSR;
224  }
225
226  /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
227  unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
228                           SmallVectorImpl<MCFixup> &Fixups) const {
229    unsigned SoImm = MI.getOperand(Op).getImm();
230    int SoImmVal = ARM_AM::getSOImmVal(SoImm);
231    assert(SoImmVal != -1 && "Not a valid so_imm value!");
232
233    // Encode rotate_imm.
234    unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
235      << ARMII::SoRotImmShift;
236
237    // Encode immed_8.
238    Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
239    return Binary;
240  }
241
242  /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
243  unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
244                           SmallVectorImpl<MCFixup> &Fixups) const {
245    unsigned SoImm = MI.getOperand(Op).getImm();
246    unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
247    assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
248    return Encoded;
249  }
250
251  unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
252    SmallVectorImpl<MCFixup> &Fixups) const;
253  unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
254    SmallVectorImpl<MCFixup> &Fixups) const;
255  unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
256    SmallVectorImpl<MCFixup> &Fixups) const;
257  unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
258    SmallVectorImpl<MCFixup> &Fixups) const;
259
260  /// getSORegOpValue - Return an encoded so_reg shifted register value.
261  unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
262                           SmallVectorImpl<MCFixup> &Fixups) const;
263  unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
264                           SmallVectorImpl<MCFixup> &Fixups) const;
265  unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
266                             SmallVectorImpl<MCFixup> &Fixups) const;
267
268  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
269                                   SmallVectorImpl<MCFixup> &Fixups) const {
270    return 64 - MI.getOperand(Op).getImm();
271  }
272
273  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
274                                      SmallVectorImpl<MCFixup> &Fixups) const;
275
276  unsigned getMsbOpValue(const MCInst &MI, unsigned Op,
277                         SmallVectorImpl<MCFixup> &Fixups) const;
278
279  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
280                                  SmallVectorImpl<MCFixup> &Fixups) const;
281  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
282                                      SmallVectorImpl<MCFixup> &Fixups) const;
283  unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
284                                        SmallVectorImpl<MCFixup> &Fixups) const;
285  unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
286                                        SmallVectorImpl<MCFixup> &Fixups) const;
287  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
288                                     SmallVectorImpl<MCFixup> &Fixups) const;
289
290  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
291                             SmallVectorImpl<MCFixup> &Fixups) const;
292  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
293                              SmallVectorImpl<MCFixup> &Fixups) const;
294  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
295                              SmallVectorImpl<MCFixup> &Fixups) const;
296  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
297                              SmallVectorImpl<MCFixup> &Fixups) const;
298
299  unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
300                                 SmallVectorImpl<MCFixup> &Fixups) const;
301
302  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
303                                      unsigned EncodedValue) const;
304  unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
305                                          unsigned EncodedValue) const;
306  unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
307                                    unsigned EncodedValue) const;
308
309  unsigned VFPThumb2PostEncoder(const MCInst &MI,
310                                unsigned EncodedValue) const;
311
312  void EmitByte(unsigned char C, raw_ostream &OS) const {
313    OS << (char)C;
314  }
315
316  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
317    // Output the constant in little endian byte order.
318    for (unsigned i = 0; i != Size; ++i) {
319      EmitByte(Val & 255, OS);
320      Val >>= 8;
321    }
322  }
323
324  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
325                         SmallVectorImpl<MCFixup> &Fixups) const;
326};
327
328} // end anonymous namespace
329
330MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
331                                            const MCSubtargetInfo &STI,
332                                            MCContext &Ctx) {
333  return new ARMMCCodeEmitter(MCII, STI, Ctx);
334}
335
336/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
337/// instructions, and rewrite them to their Thumb2 form if we are currently in
338/// Thumb2 mode.
339unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
340                                                 unsigned EncodedValue) const {
341  if (isThumb2()) {
342    // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
343    // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
344    // set to 1111.
345    unsigned Bit24 = EncodedValue & 0x01000000;
346    unsigned Bit28 = Bit24 << 4;
347    EncodedValue &= 0xEFFFFFFF;
348    EncodedValue |= Bit28;
349    EncodedValue |= 0x0F000000;
350  }
351
352  return EncodedValue;
353}
354
355/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
356/// instructions, and rewrite them to their Thumb2 form if we are currently in
357/// Thumb2 mode.
358unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
359                                                 unsigned EncodedValue) const {
360  if (isThumb2()) {
361    EncodedValue &= 0xF0FFFFFF;
362    EncodedValue |= 0x09000000;
363  }
364
365  return EncodedValue;
366}
367
368/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
369/// instructions, and rewrite them to their Thumb2 form if we are currently in
370/// Thumb2 mode.
371unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
372                                                 unsigned EncodedValue) const {
373  if (isThumb2()) {
374    EncodedValue &= 0x00FFFFFF;
375    EncodedValue |= 0xEE000000;
376  }
377
378  return EncodedValue;
379}
380
381/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
382/// them to their Thumb2 form if we are currently in Thumb2 mode.
383unsigned ARMMCCodeEmitter::
384VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
385  if (isThumb2()) {
386    EncodedValue &= 0x0FFFFFFF;
387    EncodedValue |= 0xE0000000;
388  }
389  return EncodedValue;
390}
391
392/// getMachineOpValue - Return binary encoding of operand. If the machine
393/// operand requires relocation, record the relocation and return zero.
394unsigned ARMMCCodeEmitter::
395getMachineOpValue(const MCInst &MI, const MCOperand &MO,
396                  SmallVectorImpl<MCFixup> &Fixups) const {
397  if (MO.isReg()) {
398    unsigned Reg = MO.getReg();
399    unsigned RegNo = getARMRegisterNumbering(Reg);
400
401    // Q registers are encoded as 2x their register number.
402    switch (Reg) {
403    default:
404      return RegNo;
405    case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
406    case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
407    case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
408    case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
409      return 2 * RegNo;
410    }
411  } else if (MO.isImm()) {
412    return static_cast<unsigned>(MO.getImm());
413  } else if (MO.isFPImm()) {
414    return static_cast<unsigned>(APFloat(MO.getFPImm())
415                     .bitcastToAPInt().getHiBits(32).getLimitedValue());
416  }
417
418  llvm_unreachable("Unable to encode MCOperand!");
419  return 0;
420}
421
422/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
423bool ARMMCCodeEmitter::
424EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
425                       unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
426  const MCOperand &MO  = MI.getOperand(OpIdx);
427  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
428
429  Reg = getARMRegisterNumbering(MO.getReg());
430
431  int32_t SImm = MO1.getImm();
432  bool isAdd = true;
433
434  // Special value for #-0
435  if (SImm == INT32_MIN)
436    SImm = 0;
437
438  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
439  if (SImm < 0) {
440    SImm = -SImm;
441    isAdd = false;
442  }
443
444  Imm = SImm;
445  return isAdd;
446}
447
448/// getBranchTargetOpValue - Helper function to get the branch target operand,
449/// which is either an immediate or requires a fixup.
450static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
451                                       unsigned FixupKind,
452                                       SmallVectorImpl<MCFixup> &Fixups) {
453  const MCOperand &MO = MI.getOperand(OpIdx);
454
455  // If the destination is an immediate, we have nothing to do.
456  if (MO.isImm()) return MO.getImm();
457  assert(MO.isExpr() && "Unexpected branch target type!");
458  const MCExpr *Expr = MO.getExpr();
459  MCFixupKind Kind = MCFixupKind(FixupKind);
460  Fixups.push_back(MCFixup::Create(0, Expr, Kind));
461
462  // All of the information is in the fixup.
463  return 0;
464}
465
466/// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
467uint32_t ARMMCCodeEmitter::
468getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
469                        SmallVectorImpl<MCFixup> &Fixups) const {
470  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
471}
472
473/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
474/// BLX branch target.
475uint32_t ARMMCCodeEmitter::
476getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
477                         SmallVectorImpl<MCFixup> &Fixups) const {
478  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
479}
480
481/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
482uint32_t ARMMCCodeEmitter::
483getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
484                        SmallVectorImpl<MCFixup> &Fixups) const {
485  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
486}
487
488/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
489uint32_t ARMMCCodeEmitter::
490getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
491                         SmallVectorImpl<MCFixup> &Fixups) const {
492  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
493}
494
495/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
496uint32_t ARMMCCodeEmitter::
497getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
498                        SmallVectorImpl<MCFixup> &Fixups) const {
499  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
500}
501
502/// Return true if this branch has a non-always predication
503static bool HasConditionalBranch(const MCInst &MI) {
504  int NumOp = MI.getNumOperands();
505  if (NumOp >= 2) {
506    for (int i = 0; i < NumOp-1; ++i) {
507      const MCOperand &MCOp1 = MI.getOperand(i);
508      const MCOperand &MCOp2 = MI.getOperand(i + 1);
509      if (MCOp1.isImm() && MCOp2.isReg() &&
510          (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
511        if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
512          return true;
513      }
514    }
515  }
516  return false;
517}
518
519/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
520/// target.
521uint32_t ARMMCCodeEmitter::
522getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
523                       SmallVectorImpl<MCFixup> &Fixups) const {
524  // FIXME: This really, really shouldn't use TargetMachine. We don't want
525  // coupling between MC and TM anywhere we can help it.
526  if (isThumb2())
527    return
528      ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
529  return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
530}
531
532/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
533/// target.
534uint32_t ARMMCCodeEmitter::
535getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
536                          SmallVectorImpl<MCFixup> &Fixups) const {
537  const MCOperand MO = MI.getOperand(OpIdx);
538  if (MO.isExpr()) {
539    if (HasConditionalBranch(MI))
540      return ::getBranchTargetOpValue(MI, OpIdx,
541                                      ARM::fixup_arm_condbranch, Fixups);
542    return ::getBranchTargetOpValue(MI, OpIdx,
543                                    ARM::fixup_arm_uncondbranch, Fixups);
544  }
545
546  return MO.getImm() >> 2;
547}
548
549uint32_t ARMMCCodeEmitter::
550getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
551                          SmallVectorImpl<MCFixup> &Fixups) const {
552  const MCOperand MO = MI.getOperand(OpIdx);
553  if (MO.isExpr()) {
554    if (HasConditionalBranch(MI))
555      return ::getBranchTargetOpValue(MI, OpIdx,
556                                      ARM::fixup_arm_condbranch, Fixups);
557    return ::getBranchTargetOpValue(MI, OpIdx,
558                                    ARM::fixup_arm_uncondbranch, Fixups);
559  }
560
561  return MO.getImm() >> 1;
562}
563
564/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
565/// immediate branch target.
566uint32_t ARMMCCodeEmitter::
567getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
568                       SmallVectorImpl<MCFixup> &Fixups) const {
569  unsigned Val =
570    ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
571  bool I  = (Val & 0x800000);
572  bool J1 = (Val & 0x400000);
573  bool J2 = (Val & 0x200000);
574  if (I ^ J1)
575    Val &= ~0x400000;
576  else
577    Val |= 0x400000;
578
579  if (I ^ J2)
580    Val &= ~0x200000;
581  else
582    Val |= 0x200000;
583
584  return Val;
585}
586
587/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
588/// target.
589uint32_t ARMMCCodeEmitter::
590getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
591                   SmallVectorImpl<MCFixup> &Fixups) const {
592  const MCOperand MO = MI.getOperand(OpIdx);
593  if (MO.isExpr())
594    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
595                                    Fixups);
596  int32_t offset = MO.getImm();
597  uint32_t Val = 0x2000;
598  if (offset < 0) {
599    Val = 0x1000;
600    offset *= -1;
601  }
602  Val |= offset;
603  return Val;
604}
605
606/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
607/// target.
608uint32_t ARMMCCodeEmitter::
609getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
610                   SmallVectorImpl<MCFixup> &Fixups) const {
611  const MCOperand MO = MI.getOperand(OpIdx);
612  if (MO.isExpr())
613    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
614                                    Fixups);
615  return MO.getImm();
616}
617
618/// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
619/// target.
620uint32_t ARMMCCodeEmitter::
621getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
622                   SmallVectorImpl<MCFixup> &Fixups) const {
623  const MCOperand MO = MI.getOperand(OpIdx);
624  if (MO.isExpr())
625    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
626                                    Fixups);
627  return MO.getImm();
628}
629
630/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
631/// operand.
632uint32_t ARMMCCodeEmitter::
633getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
634                              SmallVectorImpl<MCFixup> &) const {
635  // [Rn, Rm]
636  //   {5-3} = Rm
637  //   {2-0} = Rn
638  const MCOperand &MO1 = MI.getOperand(OpIdx);
639  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
640  unsigned Rn = getARMRegisterNumbering(MO1.getReg());
641  unsigned Rm = getARMRegisterNumbering(MO2.getReg());
642  return (Rm << 3) | Rn;
643}
644
645/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
646uint32_t ARMMCCodeEmitter::
647getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
648                        SmallVectorImpl<MCFixup> &Fixups) const {
649  // {17-13} = reg
650  // {12}    = (U)nsigned (add == '1', sub == '0')
651  // {11-0}  = imm12
652  unsigned Reg, Imm12;
653  bool isAdd = true;
654  // If The first operand isn't a register, we have a label reference.
655  const MCOperand &MO = MI.getOperand(OpIdx);
656  if (!MO.isReg()) {
657    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
658    Imm12 = 0;
659    isAdd = false ; // 'U' bit is set as part of the fixup.
660
661    assert(MO.isExpr() && "Unexpected machine operand type!");
662    const MCExpr *Expr = MO.getExpr();
663
664    MCFixupKind Kind;
665    if (isThumb2())
666      Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
667    else
668      Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
669    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
670
671    ++MCNumCPRelocations;
672  } else
673    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
674
675  uint32_t Binary = Imm12 & 0xfff;
676  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
677  if (isAdd)
678    Binary |= (1 << 12);
679  Binary |= (Reg << 13);
680  return Binary;
681}
682
683/// getT2AddrModeImm8s4OpValue - Return encoding info for
684/// 'reg +/- imm8<<2' operand.
685uint32_t ARMMCCodeEmitter::
686getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
687                        SmallVectorImpl<MCFixup> &Fixups) const {
688  // {12-9} = reg
689  // {8}    = (U)nsigned (add == '1', sub == '0')
690  // {7-0}  = imm8
691  unsigned Reg, Imm8;
692  bool isAdd = true;
693  // If The first operand isn't a register, we have a label reference.
694  const MCOperand &MO = MI.getOperand(OpIdx);
695  if (!MO.isReg()) {
696    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
697    Imm8 = 0;
698    isAdd = false ; // 'U' bit is set as part of the fixup.
699
700    assert(MO.isExpr() && "Unexpected machine operand type!");
701    const MCExpr *Expr = MO.getExpr();
702    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
703    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
704
705    ++MCNumCPRelocations;
706  } else
707    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
708
709  uint32_t Binary = (Imm8 >> 2) & 0xff;
710  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
711  if (isAdd)
712    Binary |= (1 << 8);
713  Binary |= (Reg << 9);
714  return Binary;
715}
716
717// FIXME: This routine assumes that a binary
718// expression will always result in a PCRel expression
719// In reality, its only true if one or more subexpressions
720// is itself a PCRel (i.e. "." in asm or some other pcrel construct)
721// but this is good enough for now.
722static bool EvaluateAsPCRel(const MCExpr *Expr) {
723  switch (Expr->getKind()) {
724  default: assert(0 && "Unexpected expression type");
725  case MCExpr::SymbolRef: return false;
726  case MCExpr::Binary: return true;
727  }
728}
729
730uint32_t
731ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
732                                      SmallVectorImpl<MCFixup> &Fixups) const {
733  // {20-16} = imm{15-12}
734  // {11-0}  = imm{11-0}
735  const MCOperand &MO = MI.getOperand(OpIdx);
736  if (MO.isImm())
737    // Hi / lo 16 bits already extracted during earlier passes.
738    return static_cast<unsigned>(MO.getImm());
739
740  // Handle :upper16: and :lower16: assembly prefixes.
741  const MCExpr *E = MO.getExpr();
742  if (E->getKind() == MCExpr::Target) {
743    const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
744    E = ARM16Expr->getSubExpr();
745
746    MCFixupKind Kind;
747    switch (ARM16Expr->getKind()) {
748    default: assert(0 && "Unsupported ARMFixup");
749    case ARMMCExpr::VK_ARM_HI16:
750      if (!isTargetDarwin() && EvaluateAsPCRel(E))
751        Kind = MCFixupKind(isThumb2()
752                           ? ARM::fixup_t2_movt_hi16_pcrel
753                           : ARM::fixup_arm_movt_hi16_pcrel);
754      else
755        Kind = MCFixupKind(isThumb2()
756                           ? ARM::fixup_t2_movt_hi16
757                           : ARM::fixup_arm_movt_hi16);
758      break;
759    case ARMMCExpr::VK_ARM_LO16:
760      if (!isTargetDarwin() && EvaluateAsPCRel(E))
761        Kind = MCFixupKind(isThumb2()
762                           ? ARM::fixup_t2_movw_lo16_pcrel
763                           : ARM::fixup_arm_movw_lo16_pcrel);
764      else
765        Kind = MCFixupKind(isThumb2()
766                           ? ARM::fixup_t2_movw_lo16
767                           : ARM::fixup_arm_movw_lo16);
768      break;
769    }
770    Fixups.push_back(MCFixup::Create(0, E, Kind));
771    return 0;
772  };
773
774  llvm_unreachable("Unsupported MCExpr type in MCOperand!");
775  return 0;
776}
777
778uint32_t ARMMCCodeEmitter::
779getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
780                    SmallVectorImpl<MCFixup> &Fixups) const {
781  const MCOperand &MO = MI.getOperand(OpIdx);
782  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
783  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
784  unsigned Rn = getARMRegisterNumbering(MO.getReg());
785  unsigned Rm = getARMRegisterNumbering(MO1.getReg());
786  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
787  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
788  ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
789  unsigned SBits = getShiftOp(ShOp);
790
791  // {16-13} = Rn
792  // {12}    = isAdd
793  // {11-0}  = shifter
794  //  {3-0}  = Rm
795  //  {4}    = 0
796  //  {6-5}  = type
797  //  {11-7} = imm
798  uint32_t Binary = Rm;
799  Binary |= Rn << 13;
800  Binary |= SBits << 5;
801  Binary |= ShImm << 7;
802  if (isAdd)
803    Binary |= 1 << 12;
804  return Binary;
805}
806
807uint32_t ARMMCCodeEmitter::
808getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
809                    SmallVectorImpl<MCFixup> &Fixups) const {
810  // {17-14}  Rn
811  // {13}     1 == imm12, 0 == Rm
812  // {12}     isAdd
813  // {11-0}   imm12/Rm
814  const MCOperand &MO = MI.getOperand(OpIdx);
815  unsigned Rn = getARMRegisterNumbering(MO.getReg());
816  uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
817  Binary |= Rn << 14;
818  return Binary;
819}
820
821uint32_t ARMMCCodeEmitter::
822getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
823                          SmallVectorImpl<MCFixup> &Fixups) const {
824  // {13}     1 == imm12, 0 == Rm
825  // {12}     isAdd
826  // {11-0}   imm12/Rm
827  const MCOperand &MO = MI.getOperand(OpIdx);
828  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
829  unsigned Imm = MO1.getImm();
830  bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
831  bool isReg = MO.getReg() != 0;
832  uint32_t Binary = ARM_AM::getAM2Offset(Imm);
833  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
834  if (isReg) {
835    ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
836    Binary <<= 7;                    // Shift amount is bits [11:7]
837    Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
838    Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
839  }
840  return Binary | (isAdd << 12) | (isReg << 13);
841}
842
843uint32_t ARMMCCodeEmitter::
844getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
845                     SmallVectorImpl<MCFixup> &Fixups) const {
846  // {4}      isAdd
847  // {3-0}    Rm
848  const MCOperand &MO = MI.getOperand(OpIdx);
849  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
850  bool isAdd = MO1.getImm() != 0;
851  return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
852}
853
854uint32_t ARMMCCodeEmitter::
855getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
856                          SmallVectorImpl<MCFixup> &Fixups) const {
857  // {9}      1 == imm8, 0 == Rm
858  // {8}      isAdd
859  // {7-4}    imm7_4/zero
860  // {3-0}    imm3_0/Rm
861  const MCOperand &MO = MI.getOperand(OpIdx);
862  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
863  unsigned Imm = MO1.getImm();
864  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
865  bool isImm = MO.getReg() == 0;
866  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
867  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
868  if (!isImm)
869    Imm8 = getARMRegisterNumbering(MO.getReg());
870  return Imm8 | (isAdd << 8) | (isImm << 9);
871}
872
873uint32_t ARMMCCodeEmitter::
874getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
875                    SmallVectorImpl<MCFixup> &Fixups) const {
876  // {13}     1 == imm8, 0 == Rm
877  // {12-9}   Rn
878  // {8}      isAdd
879  // {7-4}    imm7_4/zero
880  // {3-0}    imm3_0/Rm
881  const MCOperand &MO = MI.getOperand(OpIdx);
882  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
883  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
884  unsigned Rn = getARMRegisterNumbering(MO.getReg());
885  unsigned Imm = MO2.getImm();
886  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
887  bool isImm = MO1.getReg() == 0;
888  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
889  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
890  if (!isImm)
891    Imm8 = getARMRegisterNumbering(MO1.getReg());
892  return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
893}
894
895/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
896uint32_t ARMMCCodeEmitter::
897getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
898                          SmallVectorImpl<MCFixup> &Fixups) const {
899  // [SP, #imm]
900  //   {7-0} = imm8
901  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
902  assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
903         "Unexpected base register!");
904
905  // The immediate is already shifted for the implicit zeroes, so no change
906  // here.
907  return MO1.getImm() & 0xff;
908}
909
910/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
911uint32_t ARMMCCodeEmitter::
912getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
913                     SmallVectorImpl<MCFixup> &Fixups) const {
914  // [Rn, #imm]
915  //   {7-3} = imm5
916  //   {2-0} = Rn
917  const MCOperand &MO = MI.getOperand(OpIdx);
918  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
919  unsigned Rn = getARMRegisterNumbering(MO.getReg());
920  unsigned Imm5 = MO1.getImm();
921  return ((Imm5 & 0x1f) << 3) | Rn;
922}
923
924/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
925uint32_t ARMMCCodeEmitter::
926getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
927                     SmallVectorImpl<MCFixup> &Fixups) const {
928  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
929}
930
931/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
932uint32_t ARMMCCodeEmitter::
933getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
934                    SmallVectorImpl<MCFixup> &Fixups) const {
935  // {12-9} = reg
936  // {8}    = (U)nsigned (add == '1', sub == '0')
937  // {7-0}  = imm8
938  unsigned Reg, Imm8;
939  bool isAdd;
940  // If The first operand isn't a register, we have a label reference.
941  const MCOperand &MO = MI.getOperand(OpIdx);
942  if (!MO.isReg()) {
943    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
944    Imm8 = 0;
945    isAdd = false; // 'U' bit is handled as part of the fixup.
946
947    assert(MO.isExpr() && "Unexpected machine operand type!");
948    const MCExpr *Expr = MO.getExpr();
949    MCFixupKind Kind;
950    if (isThumb2())
951      Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
952    else
953      Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
954    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
955
956    ++MCNumCPRelocations;
957  } else {
958    EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
959    isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
960  }
961
962  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
963  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
964  if (isAdd)
965    Binary |= (1 << 8);
966  Binary |= (Reg << 9);
967  return Binary;
968}
969
970unsigned ARMMCCodeEmitter::
971getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
972                SmallVectorImpl<MCFixup> &Fixups) const {
973  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
974  // shifted. The second is Rs, the amount to shift by, and the third specifies
975  // the type of the shift.
976  //
977  // {3-0} = Rm.
978  // {4}   = 1
979  // {6-5} = type
980  // {11-8} = Rs
981  // {7}    = 0
982
983  const MCOperand &MO  = MI.getOperand(OpIdx);
984  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
985  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
986  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
987
988  // Encode Rm.
989  unsigned Binary = getARMRegisterNumbering(MO.getReg());
990
991  // Encode the shift opcode.
992  unsigned SBits = 0;
993  unsigned Rs = MO1.getReg();
994  if (Rs) {
995    // Set shift operand (bit[7:4]).
996    // LSL - 0001
997    // LSR - 0011
998    // ASR - 0101
999    // ROR - 0111
1000    switch (SOpc) {
1001    default: llvm_unreachable("Unknown shift opc!");
1002    case ARM_AM::lsl: SBits = 0x1; break;
1003    case ARM_AM::lsr: SBits = 0x3; break;
1004    case ARM_AM::asr: SBits = 0x5; break;
1005    case ARM_AM::ror: SBits = 0x7; break;
1006    }
1007  }
1008
1009  Binary |= SBits << 4;
1010
1011  // Encode the shift operation Rs.
1012  // Encode Rs bit[11:8].
1013  assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1014  return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1015}
1016
1017unsigned ARMMCCodeEmitter::
1018getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1019                SmallVectorImpl<MCFixup> &Fixups) const {
1020  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1021  // shifted. The second is the amount to shift by.
1022  //
1023  // {3-0} = Rm.
1024  // {4}   = 0
1025  // {6-5} = type
1026  // {11-7} = imm
1027
1028  const MCOperand &MO  = MI.getOperand(OpIdx);
1029  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1030  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1031
1032  // Encode Rm.
1033  unsigned Binary = getARMRegisterNumbering(MO.getReg());
1034
1035  // Encode the shift opcode.
1036  unsigned SBits = 0;
1037
1038  // Set shift operand (bit[6:4]).
1039  // LSL - 000
1040  // LSR - 010
1041  // ASR - 100
1042  // ROR - 110
1043  // RRX - 110 and bit[11:8] clear.
1044  switch (SOpc) {
1045  default: llvm_unreachable("Unknown shift opc!");
1046  case ARM_AM::lsl: SBits = 0x0; break;
1047  case ARM_AM::lsr: SBits = 0x2; break;
1048  case ARM_AM::asr: SBits = 0x4; break;
1049  case ARM_AM::ror: SBits = 0x6; break;
1050  case ARM_AM::rrx:
1051    Binary |= 0x60;
1052    return Binary;
1053  }
1054
1055  // Encode shift_imm bit[11:7].
1056  Binary |= SBits << 4;
1057  unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1058  assert(Offset && "Offset must be in range 1-32!");
1059  if (Offset == 32) Offset = 0;
1060  return Binary | (Offset << 7);
1061}
1062
1063
1064unsigned ARMMCCodeEmitter::
1065getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1066                SmallVectorImpl<MCFixup> &Fixups) const {
1067  const MCOperand &MO1 = MI.getOperand(OpNum);
1068  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1069  const MCOperand &MO3 = MI.getOperand(OpNum+2);
1070
1071  // Encoded as [Rn, Rm, imm].
1072  // FIXME: Needs fixup support.
1073  unsigned Value = getARMRegisterNumbering(MO1.getReg());
1074  Value <<= 4;
1075  Value |= getARMRegisterNumbering(MO2.getReg());
1076  Value <<= 2;
1077  Value |= MO3.getImm();
1078
1079  return Value;
1080}
1081
1082unsigned ARMMCCodeEmitter::
1083getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1084                         SmallVectorImpl<MCFixup> &Fixups) const {
1085  const MCOperand &MO1 = MI.getOperand(OpNum);
1086  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1087
1088  // FIXME: Needs fixup support.
1089  unsigned Value = getARMRegisterNumbering(MO1.getReg());
1090
1091  // Even though the immediate is 8 bits long, we need 9 bits in order
1092  // to represent the (inverse of the) sign bit.
1093  Value <<= 9;
1094  int32_t tmp = (int32_t)MO2.getImm();
1095  if (tmp < 0)
1096    tmp = abs(tmp);
1097  else
1098    Value |= 256; // Set the ADD bit
1099  Value |= tmp & 255;
1100  return Value;
1101}
1102
1103unsigned ARMMCCodeEmitter::
1104getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1105                         SmallVectorImpl<MCFixup> &Fixups) const {
1106  const MCOperand &MO1 = MI.getOperand(OpNum);
1107
1108  // FIXME: Needs fixup support.
1109  unsigned Value = 0;
1110  int32_t tmp = (int32_t)MO1.getImm();
1111  if (tmp < 0)
1112    tmp = abs(tmp);
1113  else
1114    Value |= 256; // Set the ADD bit
1115  Value |= tmp & 255;
1116  return Value;
1117}
1118
1119unsigned ARMMCCodeEmitter::
1120getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1121                         SmallVectorImpl<MCFixup> &Fixups) const {
1122  const MCOperand &MO1 = MI.getOperand(OpNum);
1123
1124  // FIXME: Needs fixup support.
1125  unsigned Value = 0;
1126  int32_t tmp = (int32_t)MO1.getImm();
1127  if (tmp < 0)
1128    tmp = abs(tmp);
1129  else
1130    Value |= 4096; // Set the ADD bit
1131  Value |= tmp & 4095;
1132  return Value;
1133}
1134
1135unsigned ARMMCCodeEmitter::
1136getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1137                SmallVectorImpl<MCFixup> &Fixups) const {
1138  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1139  // shifted. The second is the amount to shift by.
1140  //
1141  // {3-0} = Rm.
1142  // {4}   = 0
1143  // {6-5} = type
1144  // {11-7} = imm
1145
1146  const MCOperand &MO  = MI.getOperand(OpIdx);
1147  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1148  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1149
1150  // Encode Rm.
1151  unsigned Binary = getARMRegisterNumbering(MO.getReg());
1152
1153  // Encode the shift opcode.
1154  unsigned SBits = 0;
1155  // Set shift operand (bit[6:4]).
1156  // LSL - 000
1157  // LSR - 010
1158  // ASR - 100
1159  // ROR - 110
1160  switch (SOpc) {
1161  default: llvm_unreachable("Unknown shift opc!");
1162  case ARM_AM::lsl: SBits = 0x0; break;
1163  case ARM_AM::lsr: SBits = 0x2; break;
1164  case ARM_AM::asr: SBits = 0x4; break;
1165  case ARM_AM::ror: SBits = 0x6; break;
1166  }
1167
1168  Binary |= SBits << 4;
1169  if (SOpc == ARM_AM::rrx)
1170    return Binary;
1171
1172  // Encode shift_imm bit[11:7].
1173  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1174}
1175
1176unsigned ARMMCCodeEmitter::
1177getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1178                               SmallVectorImpl<MCFixup> &Fixups) const {
1179  // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1180  // msb of the mask.
1181  const MCOperand &MO = MI.getOperand(Op);
1182  uint32_t v = ~MO.getImm();
1183  uint32_t lsb = CountTrailingZeros_32(v);
1184  uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1185  assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1186  return lsb | (msb << 5);
1187}
1188
1189unsigned ARMMCCodeEmitter::
1190getMsbOpValue(const MCInst &MI, unsigned Op,
1191              SmallVectorImpl<MCFixup> &Fixups) const {
1192  // MSB - 5 bits.
1193  uint32_t lsb = MI.getOperand(Op-1).getImm();
1194  uint32_t width = MI.getOperand(Op).getImm();
1195  uint32_t msb = lsb+width-1;
1196  assert (width != 0 && msb < 32 && "Illegal bit width!");
1197  return msb;
1198}
1199
1200unsigned ARMMCCodeEmitter::
1201getRegisterListOpValue(const MCInst &MI, unsigned Op,
1202                       SmallVectorImpl<MCFixup> &Fixups) const {
1203  // VLDM/VSTM:
1204  //   {12-8} = Vd
1205  //   {7-0}  = Number of registers
1206  //
1207  // LDM/STM:
1208  //   {15-0}  = Bitfield of GPRs.
1209  unsigned Reg = MI.getOperand(Op).getReg();
1210  bool SPRRegs = llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1211  bool DPRRegs = llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1212
1213  unsigned Binary = 0;
1214
1215  if (SPRRegs || DPRRegs) {
1216    // VLDM/VSTM
1217    unsigned RegNo = getARMRegisterNumbering(Reg);
1218    unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1219    Binary |= (RegNo & 0x1f) << 8;
1220    if (SPRRegs)
1221      Binary |= NumRegs;
1222    else
1223      Binary |= NumRegs * 2;
1224  } else {
1225    for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1226      unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1227      Binary |= 1 << RegNo;
1228    }
1229  }
1230
1231  return Binary;
1232}
1233
1234/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1235/// with the alignment operand.
1236unsigned ARMMCCodeEmitter::
1237getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1238                           SmallVectorImpl<MCFixup> &Fixups) const {
1239  const MCOperand &Reg = MI.getOperand(Op);
1240  const MCOperand &Imm = MI.getOperand(Op + 1);
1241
1242  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1243  unsigned Align = 0;
1244
1245  switch (Imm.getImm()) {
1246  default: break;
1247  case 2:
1248  case 4:
1249  case 8:  Align = 0x01; break;
1250  case 16: Align = 0x02; break;
1251  case 32: Align = 0x03; break;
1252  }
1253
1254  return RegNo | (Align << 4);
1255}
1256
1257/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1258/// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1259unsigned ARMMCCodeEmitter::
1260getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1261                                    SmallVectorImpl<MCFixup> &Fixups) const {
1262  const MCOperand &Reg = MI.getOperand(Op);
1263  const MCOperand &Imm = MI.getOperand(Op + 1);
1264
1265  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1266  unsigned Align = 0;
1267
1268  switch (Imm.getImm()) {
1269  default: break;
1270  case 2:
1271  case 4:
1272  case 8:
1273  case 16: Align = 0x00; break;
1274  case 32: Align = 0x03; break;
1275  }
1276
1277  return RegNo | (Align << 4);
1278}
1279
1280
1281/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1282/// alignment operand for use in VLD-dup instructions.  This is the same as
1283/// getAddrMode6AddressOpValue except for the alignment encoding, which is
1284/// different for VLD4-dup.
1285unsigned ARMMCCodeEmitter::
1286getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1287                              SmallVectorImpl<MCFixup> &Fixups) const {
1288  const MCOperand &Reg = MI.getOperand(Op);
1289  const MCOperand &Imm = MI.getOperand(Op + 1);
1290
1291  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1292  unsigned Align = 0;
1293
1294  switch (Imm.getImm()) {
1295  default: break;
1296  case 2:
1297  case 4:
1298  case 8:  Align = 0x01; break;
1299  case 16: Align = 0x03; break;
1300  }
1301
1302  return RegNo | (Align << 4);
1303}
1304
1305unsigned ARMMCCodeEmitter::
1306getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1307                          SmallVectorImpl<MCFixup> &Fixups) const {
1308  const MCOperand &MO = MI.getOperand(Op);
1309  if (MO.getReg() == 0) return 0x0D;
1310  return MO.getReg();
1311}
1312
1313unsigned ARMMCCodeEmitter::
1314getShiftRight8Imm(const MCInst &MI, unsigned Op,
1315                  SmallVectorImpl<MCFixup> &Fixups) const {
1316  return 8 - MI.getOperand(Op).getImm();
1317}
1318
1319unsigned ARMMCCodeEmitter::
1320getShiftRight16Imm(const MCInst &MI, unsigned Op,
1321                   SmallVectorImpl<MCFixup> &Fixups) const {
1322  return 16 - MI.getOperand(Op).getImm();
1323}
1324
1325unsigned ARMMCCodeEmitter::
1326getShiftRight32Imm(const MCInst &MI, unsigned Op,
1327                   SmallVectorImpl<MCFixup> &Fixups) const {
1328  return 32 - MI.getOperand(Op).getImm();
1329}
1330
1331unsigned ARMMCCodeEmitter::
1332getShiftRight64Imm(const MCInst &MI, unsigned Op,
1333                   SmallVectorImpl<MCFixup> &Fixups) const {
1334  return 64 - MI.getOperand(Op).getImm();
1335}
1336
1337void ARMMCCodeEmitter::
1338EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1339                  SmallVectorImpl<MCFixup> &Fixups) const {
1340  // Pseudo instructions don't get encoded.
1341  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1342  uint64_t TSFlags = Desc.TSFlags;
1343  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1344    return;
1345
1346  int Size;
1347  if (Desc.getSize() == 2 || Desc.getSize() == 4)
1348    Size = Desc.getSize();
1349  else
1350    llvm_unreachable("Unexpected instruction size!");
1351
1352  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1353  // Thumb 32-bit wide instructions need to emit the high order halfword
1354  // first.
1355  if (isThumb() && Size == 4) {
1356    EmitConstant(Binary >> 16, 2, OS);
1357    EmitConstant(Binary & 0xffff, 2, OS);
1358  } else
1359    EmitConstant(Binary, Size, OS);
1360  ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1361}
1362
1363#include "ARMGenMCCodeEmitter.inc"
1364