MSP430ISelLowering.cpp revision 6cbeb4d839a7fc465c651f0df0b090052cd87a5c 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430TargetMachine.h"
20#include "MSP430Subtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CallingConv.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/GlobalAlias.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39using namespace llvm;
40
41typedef enum {
42  NoHWMult,
43  HWMultIntr,
44  HWMultNoIntr
45} HWMultUseMode;
46
47static cl::opt<HWMultUseMode>
48HWMultMode("msp430-hwmult-mode",
49           cl::desc("Hardware multiplier use mode"),
50           cl::init(HWMultNoIntr),
51           cl::values(
52             clEnumValN(NoHWMult, "no",
53                "Do not use hardware multiplier"),
54             clEnumValN(HWMultIntr, "interrupts",
55                "Assume hardware multiplier can be used inside interrupts"),
56             clEnumValN(HWMultNoIntr, "use",
57                "Assume hardware multiplier cannot be used inside interrupts"),
58             clEnumValEnd));
59
60MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
61  TargetLowering(tm, new TargetLoweringObjectFileELF()),
62  Subtarget(*tm.getSubtargetImpl()) {
63
64  TD = getDataLayout();
65
66  // Set up the register classes.
67  addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
68  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
69
70  // Compute derived properties from the register classes
71  computeRegisterProperties();
72
73  // Provide all sorts of operation actions
74
75  // Division is expensive
76  setIntDivIsCheap(false);
77
78  setStackPointerRegisterToSaveRestore(MSP430::SPW);
79  setBooleanContents(ZeroOrOneBooleanContent);
80  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
81
82  // We have post-incremented loads / stores.
83  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
84  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
85
86  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
87  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
88  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
89  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
90  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
91
92  // We don't have any truncstores
93  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
94
95  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
96  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
97  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
98  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
99  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
100  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
101  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
102  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
103  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
104  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
105  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
106  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
107  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
108  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
109  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
110  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
111  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
112  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
113  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
114  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
115  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
116  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
117  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
118  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
119  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
120  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
121
122  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
123  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
124  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i8,    Expand);
125  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i16,   Expand);
126  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
127  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
128  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i8,    Expand);
129  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i16,   Expand);
130  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
131  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
132
133  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
134  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
135  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
139
140  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
141
142  // FIXME: Implement efficiently multiplication by a constant
143  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
144  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
145  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
146  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
147  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
148  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
149  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
150  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
151  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
152  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
153
154  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
155  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
156  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
157  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
158  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
159  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
160  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
161  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
162  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
163  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
164  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
165  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
166
167  // Libcalls names.
168  if (HWMultMode == HWMultIntr) {
169    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
170    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
171  } else if (HWMultMode == HWMultNoIntr) {
172    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
173    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
174  }
175
176  setMinFunctionAlignment(1);
177  setPrefFunctionAlignment(2);
178}
179
180SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
181                                             SelectionDAG &DAG) const {
182  switch (Op.getOpcode()) {
183  case ISD::SHL: // FALLTHROUGH
184  case ISD::SRL:
185  case ISD::SRA:              return LowerShifts(Op, DAG);
186  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
187  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
188  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
189  case ISD::SETCC:            return LowerSETCC(Op, DAG);
190  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
191  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
192  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
193  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
194  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
195  default:
196    llvm_unreachable("unimplemented operand");
197  }
198}
199
200//===----------------------------------------------------------------------===//
201//                       MSP430 Inline Assembly Support
202//===----------------------------------------------------------------------===//
203
204/// getConstraintType - Given a constraint letter, return the type of
205/// constraint it is for this target.
206TargetLowering::ConstraintType
207MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
208  if (Constraint.size() == 1) {
209    switch (Constraint[0]) {
210    case 'r':
211      return C_RegisterClass;
212    default:
213      break;
214    }
215  }
216  return TargetLowering::getConstraintType(Constraint);
217}
218
219std::pair<unsigned, const TargetRegisterClass*>
220MSP430TargetLowering::
221getRegForInlineAsmConstraint(const std::string &Constraint,
222                             EVT VT) const {
223  if (Constraint.size() == 1) {
224    // GCC Constraint Letters
225    switch (Constraint[0]) {
226    default: break;
227    case 'r':   // GENERAL_REGS
228      if (VT == MVT::i8)
229        return std::make_pair(0U, &MSP430::GR8RegClass);
230
231      return std::make_pair(0U, &MSP430::GR16RegClass);
232    }
233  }
234
235  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
236}
237
238//===----------------------------------------------------------------------===//
239//                      Calling Convention Implementation
240//===----------------------------------------------------------------------===//
241
242#include "MSP430GenCallingConv.inc"
243
244SDValue
245MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
246                                           CallingConv::ID CallConv,
247                                           bool isVarArg,
248                                           const SmallVectorImpl<ISD::InputArg>
249                                             &Ins,
250                                           DebugLoc dl,
251                                           SelectionDAG &DAG,
252                                           SmallVectorImpl<SDValue> &InVals)
253                                             const {
254
255  switch (CallConv) {
256  default:
257    llvm_unreachable("Unsupported calling convention");
258  case CallingConv::C:
259  case CallingConv::Fast:
260    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
261  case CallingConv::MSP430_INTR:
262    if (Ins.empty())
263      return Chain;
264    report_fatal_error("ISRs cannot have arguments");
265  }
266}
267
268SDValue
269MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
270                                SmallVectorImpl<SDValue> &InVals) const {
271  SelectionDAG &DAG                     = CLI.DAG;
272  DebugLoc &dl                          = CLI.DL;
273  SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
274  SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;
275  SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;
276  SDValue Chain                         = CLI.Chain;
277  SDValue Callee                        = CLI.Callee;
278  bool &isTailCall                      = CLI.IsTailCall;
279  CallingConv::ID CallConv              = CLI.CallConv;
280  bool isVarArg                         = CLI.IsVarArg;
281
282  // MSP430 target does not yet support tail call optimization.
283  isTailCall = false;
284
285  switch (CallConv) {
286  default:
287    llvm_unreachable("Unsupported calling convention");
288  case CallingConv::Fast:
289  case CallingConv::C:
290    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
291                          Outs, OutVals, Ins, dl, DAG, InVals);
292  case CallingConv::MSP430_INTR:
293    report_fatal_error("ISRs cannot be called directly");
294  }
295}
296
297/// LowerCCCArguments - transform physical registers into virtual registers and
298/// generate load operations for arguments places on the stack.
299// FIXME: struct return stuff
300// FIXME: varargs
301SDValue
302MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
303                                        CallingConv::ID CallConv,
304                                        bool isVarArg,
305                                        const SmallVectorImpl<ISD::InputArg>
306                                          &Ins,
307                                        DebugLoc dl,
308                                        SelectionDAG &DAG,
309                                        SmallVectorImpl<SDValue> &InVals)
310                                          const {
311  MachineFunction &MF = DAG.getMachineFunction();
312  MachineFrameInfo *MFI = MF.getFrameInfo();
313  MachineRegisterInfo &RegInfo = MF.getRegInfo();
314
315  // Assign locations to all of the incoming arguments.
316  SmallVector<CCValAssign, 16> ArgLocs;
317  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
318                 getTargetMachine(), ArgLocs, *DAG.getContext());
319  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
320
321  assert(!isVarArg && "Varargs not supported yet");
322
323  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
324    CCValAssign &VA = ArgLocs[i];
325    if (VA.isRegLoc()) {
326      // Arguments passed in registers
327      EVT RegVT = VA.getLocVT();
328      switch (RegVT.getSimpleVT().SimpleTy) {
329      default:
330        {
331#ifndef NDEBUG
332          errs() << "LowerFormalArguments Unhandled argument type: "
333               << RegVT.getSimpleVT().SimpleTy << "\n";
334#endif
335          llvm_unreachable(0);
336        }
337      case MVT::i16:
338        unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
339        RegInfo.addLiveIn(VA.getLocReg(), VReg);
340        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
341
342        // If this is an 8-bit value, it is really passed promoted to 16
343        // bits. Insert an assert[sz]ext to capture this, then truncate to the
344        // right size.
345        if (VA.getLocInfo() == CCValAssign::SExt)
346          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
347                                 DAG.getValueType(VA.getValVT()));
348        else if (VA.getLocInfo() == CCValAssign::ZExt)
349          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
350                                 DAG.getValueType(VA.getValVT()));
351
352        if (VA.getLocInfo() != CCValAssign::Full)
353          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
354
355        InVals.push_back(ArgValue);
356      }
357    } else {
358      // Sanity check
359      assert(VA.isMemLoc());
360
361      SDValue InVal;
362      ISD::ArgFlagsTy Flags = Ins[i].Flags;
363
364      if (Flags.isByVal()) {
365        int FI = MFI->CreateFixedObject(Flags.getByValSize(),
366                                        VA.getLocMemOffset(), true);
367        InVal = DAG.getFrameIndex(FI, getPointerTy());
368      } else {
369        // Load the argument to a virtual register
370        unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
371        if (ObjSize > 2) {
372            errs() << "LowerFormalArguments Unhandled argument type: "
373                << EVT(VA.getLocVT()).getEVTString()
374                << "\n";
375        }
376        // Create the frame index object for this incoming parameter...
377        int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
378
379        // Create the SelectionDAG nodes corresponding to a load
380        //from this parameter
381        SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
382        InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
383                            MachinePointerInfo::getFixedStack(FI),
384                            false, false, false, 0);
385      }
386
387      InVals.push_back(InVal);
388    }
389  }
390
391  return Chain;
392}
393
394SDValue
395MSP430TargetLowering::LowerReturn(SDValue Chain,
396                                  CallingConv::ID CallConv, bool isVarArg,
397                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
398                                  const SmallVectorImpl<SDValue> &OutVals,
399                                  DebugLoc dl, SelectionDAG &DAG) const {
400
401  // CCValAssign - represent the assignment of the return value to a location
402  SmallVector<CCValAssign, 16> RVLocs;
403
404  // ISRs cannot return any value.
405  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
406    report_fatal_error("ISRs cannot return any value");
407
408  // CCState - Info about the registers and stack slot.
409  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
410                 getTargetMachine(), RVLocs, *DAG.getContext());
411
412  // Analize return values.
413  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
414
415  // If this is the first return lowered for this function, add the regs to the
416  // liveout set for the function.
417  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
418    for (unsigned i = 0; i != RVLocs.size(); ++i)
419      if (RVLocs[i].isRegLoc())
420        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
421  }
422
423  SDValue Flag;
424
425  // Copy the result values into the output registers.
426  for (unsigned i = 0; i != RVLocs.size(); ++i) {
427    CCValAssign &VA = RVLocs[i];
428    assert(VA.isRegLoc() && "Can only return in registers!");
429
430    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
431                             OutVals[i], Flag);
432
433    // Guarantee that all emitted copies are stuck together,
434    // avoiding something bad.
435    Flag = Chain.getValue(1);
436  }
437
438  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
439                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
440
441  if (Flag.getNode())
442    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
443
444  // Return Void
445  return DAG.getNode(Opc, dl, MVT::Other, Chain);
446}
447
448/// LowerCCCCallTo - functions arguments are copied from virtual regs to
449/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
450/// TODO: sret.
451SDValue
452MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
453                                     CallingConv::ID CallConv, bool isVarArg,
454                                     bool isTailCall,
455                                     const SmallVectorImpl<ISD::OutputArg>
456                                       &Outs,
457                                     const SmallVectorImpl<SDValue> &OutVals,
458                                     const SmallVectorImpl<ISD::InputArg> &Ins,
459                                     DebugLoc dl, SelectionDAG &DAG,
460                                     SmallVectorImpl<SDValue> &InVals) const {
461  // Analyze operands of the call, assigning locations to each operand.
462  SmallVector<CCValAssign, 16> ArgLocs;
463  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
464                 getTargetMachine(), ArgLocs, *DAG.getContext());
465
466  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
467
468  // Get a count of how many bytes are to be pushed on the stack.
469  unsigned NumBytes = CCInfo.getNextStackOffset();
470
471  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
472                                                      getPointerTy(), true));
473
474  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
475  SmallVector<SDValue, 12> MemOpChains;
476  SDValue StackPtr;
477
478  // Walk the register/memloc assignments, inserting copies/loads.
479  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
480    CCValAssign &VA = ArgLocs[i];
481
482    SDValue Arg = OutVals[i];
483
484    // Promote the value if needed.
485    switch (VA.getLocInfo()) {
486      default: llvm_unreachable("Unknown loc info!");
487      case CCValAssign::Full: break;
488      case CCValAssign::SExt:
489        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
490        break;
491      case CCValAssign::ZExt:
492        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
493        break;
494      case CCValAssign::AExt:
495        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
496        break;
497    }
498
499    // Arguments that can be passed on register must be kept at RegsToPass
500    // vector
501    if (VA.isRegLoc()) {
502      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
503    } else {
504      assert(VA.isMemLoc());
505
506      if (StackPtr.getNode() == 0)
507        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
508
509      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
510                                   StackPtr,
511                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
512
513      SDValue MemOp;
514      ISD::ArgFlagsTy Flags = Outs[i].Flags;
515
516      if (Flags.isByVal()) {
517        SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i16);
518        MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
519                              Flags.getByValAlign(),
520                              /*isVolatile*/false,
521                              /*AlwaysInline=*/true,
522                              MachinePointerInfo(),
523                              MachinePointerInfo());
524      } else {
525        MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
526                             false, false, 0);
527      }
528
529      MemOpChains.push_back(MemOp);
530    }
531  }
532
533  // Transform all store nodes into one single node because all store nodes are
534  // independent of each other.
535  if (!MemOpChains.empty())
536    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
537                        &MemOpChains[0], MemOpChains.size());
538
539  // Build a sequence of copy-to-reg nodes chained together with token chain and
540  // flag operands which copy the outgoing args into registers.  The InFlag in
541  // necessary since all emitted instructions must be stuck together.
542  SDValue InFlag;
543  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
544    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
545                             RegsToPass[i].second, InFlag);
546    InFlag = Chain.getValue(1);
547  }
548
549  // If the callee is a GlobalAddress node (quite common, every direct call is)
550  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
551  // Likewise ExternalSymbol -> TargetExternalSymbol.
552  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
553    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
554  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
555    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
556
557  // Returns a chain & a flag for retval copy to use.
558  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
559  SmallVector<SDValue, 8> Ops;
560  Ops.push_back(Chain);
561  Ops.push_back(Callee);
562
563  // Add argument registers to the end of the list so that they are
564  // known live into the call.
565  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
566    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
567                                  RegsToPass[i].second.getValueType()));
568
569  if (InFlag.getNode())
570    Ops.push_back(InFlag);
571
572  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
573  InFlag = Chain.getValue(1);
574
575  // Create the CALLSEQ_END node.
576  Chain = DAG.getCALLSEQ_END(Chain,
577                             DAG.getConstant(NumBytes, getPointerTy(), true),
578                             DAG.getConstant(0, getPointerTy(), true),
579                             InFlag);
580  InFlag = Chain.getValue(1);
581
582  // Handle result values, copying them out of physregs into vregs that we
583  // return.
584  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
585                         DAG, InVals);
586}
587
588/// LowerCallResult - Lower the result values of a call into the
589/// appropriate copies out of appropriate physical registers.
590///
591SDValue
592MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
593                                      CallingConv::ID CallConv, bool isVarArg,
594                                      const SmallVectorImpl<ISD::InputArg> &Ins,
595                                      DebugLoc dl, SelectionDAG &DAG,
596                                      SmallVectorImpl<SDValue> &InVals) const {
597
598  // Assign locations to each value returned by this call.
599  SmallVector<CCValAssign, 16> RVLocs;
600  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
601                 getTargetMachine(), RVLocs, *DAG.getContext());
602
603  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
604
605  // Copy all of the result registers out of their specified physreg.
606  for (unsigned i = 0; i != RVLocs.size(); ++i) {
607    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
608                               RVLocs[i].getValVT(), InFlag).getValue(1);
609    InFlag = Chain.getValue(2);
610    InVals.push_back(Chain.getValue(0));
611  }
612
613  return Chain;
614}
615
616SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
617                                          SelectionDAG &DAG) const {
618  unsigned Opc = Op.getOpcode();
619  SDNode* N = Op.getNode();
620  EVT VT = Op.getValueType();
621  DebugLoc dl = N->getDebugLoc();
622
623  // Expand non-constant shifts to loops:
624  if (!isa<ConstantSDNode>(N->getOperand(1)))
625    switch (Opc) {
626    default: llvm_unreachable("Invalid shift opcode!");
627    case ISD::SHL:
628      return DAG.getNode(MSP430ISD::SHL, dl,
629                         VT, N->getOperand(0), N->getOperand(1));
630    case ISD::SRA:
631      return DAG.getNode(MSP430ISD::SRA, dl,
632                         VT, N->getOperand(0), N->getOperand(1));
633    case ISD::SRL:
634      return DAG.getNode(MSP430ISD::SRL, dl,
635                         VT, N->getOperand(0), N->getOperand(1));
636    }
637
638  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
639
640  // Expand the stuff into sequence of shifts.
641  // FIXME: for some shift amounts this might be done better!
642  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
643  SDValue Victim = N->getOperand(0);
644
645  if (Opc == ISD::SRL && ShiftAmount) {
646    // Emit a special goodness here:
647    // srl A, 1 => clrc; rrc A
648    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
649    ShiftAmount -= 1;
650  }
651
652  while (ShiftAmount--)
653    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
654                         dl, VT, Victim);
655
656  return Victim;
657}
658
659SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
660                                                 SelectionDAG &DAG) const {
661  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
662  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
663
664  // Create the TargetGlobalAddress node, folding in the constant offset.
665  SDValue Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
666                                              getPointerTy(), Offset);
667  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
668                     getPointerTy(), Result);
669}
670
671SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
672                                                  SelectionDAG &DAG) const {
673  DebugLoc dl = Op.getDebugLoc();
674  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
675  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
676
677  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
678}
679
680SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
681                                                SelectionDAG &DAG) const {
682  DebugLoc dl = Op.getDebugLoc();
683  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
684  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy());
685
686  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
687}
688
689static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
690                       ISD::CondCode CC,
691                       DebugLoc dl, SelectionDAG &DAG) {
692  // FIXME: Handle bittests someday
693  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
694
695  // FIXME: Handle jump negative someday
696  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
697  switch (CC) {
698  default: llvm_unreachable("Invalid integer condition!");
699  case ISD::SETEQ:
700    TCC = MSP430CC::COND_E;     // aka COND_Z
701    // Minor optimization: if LHS is a constant, swap operands, then the
702    // constant can be folded into comparison.
703    if (LHS.getOpcode() == ISD::Constant)
704      std::swap(LHS, RHS);
705    break;
706  case ISD::SETNE:
707    TCC = MSP430CC::COND_NE;    // aka COND_NZ
708    // Minor optimization: if LHS is a constant, swap operands, then the
709    // constant can be folded into comparison.
710    if (LHS.getOpcode() == ISD::Constant)
711      std::swap(LHS, RHS);
712    break;
713  case ISD::SETULE:
714    std::swap(LHS, RHS);        // FALLTHROUGH
715  case ISD::SETUGE:
716    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
717    // fold constant into instruction.
718    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
719      LHS = RHS;
720      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
721      TCC = MSP430CC::COND_LO;
722      break;
723    }
724    TCC = MSP430CC::COND_HS;    // aka COND_C
725    break;
726  case ISD::SETUGT:
727    std::swap(LHS, RHS);        // FALLTHROUGH
728  case ISD::SETULT:
729    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
730    // fold constant into instruction.
731    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
732      LHS = RHS;
733      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
734      TCC = MSP430CC::COND_HS;
735      break;
736    }
737    TCC = MSP430CC::COND_LO;    // aka COND_NC
738    break;
739  case ISD::SETLE:
740    std::swap(LHS, RHS);        // FALLTHROUGH
741  case ISD::SETGE:
742    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
743    // fold constant into instruction.
744    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
745      LHS = RHS;
746      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
747      TCC = MSP430CC::COND_L;
748      break;
749    }
750    TCC = MSP430CC::COND_GE;
751    break;
752  case ISD::SETGT:
753    std::swap(LHS, RHS);        // FALLTHROUGH
754  case ISD::SETLT:
755    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
756    // fold constant into instruction.
757    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
758      LHS = RHS;
759      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
760      TCC = MSP430CC::COND_GE;
761      break;
762    }
763    TCC = MSP430CC::COND_L;
764    break;
765  }
766
767  TargetCC = DAG.getConstant(TCC, MVT::i8);
768  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
769}
770
771
772SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
773  SDValue Chain = Op.getOperand(0);
774  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
775  SDValue LHS   = Op.getOperand(2);
776  SDValue RHS   = Op.getOperand(3);
777  SDValue Dest  = Op.getOperand(4);
778  DebugLoc dl   = Op.getDebugLoc();
779
780  SDValue TargetCC;
781  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
782
783  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
784                     Chain, Dest, TargetCC, Flag);
785}
786
787SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
788  SDValue LHS   = Op.getOperand(0);
789  SDValue RHS   = Op.getOperand(1);
790  DebugLoc dl   = Op.getDebugLoc();
791
792  // If we are doing an AND and testing against zero, then the CMP
793  // will not be generated.  The AND (or BIT) will generate the condition codes,
794  // but they are different from CMP.
795  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
796  // lowering & isel wouldn't diverge.
797  bool andCC = false;
798  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
799    if (RHSC->isNullValue() && LHS.hasOneUse() &&
800        (LHS.getOpcode() == ISD::AND ||
801         (LHS.getOpcode() == ISD::TRUNCATE &&
802          LHS.getOperand(0).getOpcode() == ISD::AND))) {
803      andCC = true;
804    }
805  }
806  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
807  SDValue TargetCC;
808  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
809
810  // Get the condition codes directly from the status register, if its easy.
811  // Otherwise a branch will be generated.  Note that the AND and BIT
812  // instructions generate different flags than CMP, the carry bit can be used
813  // for NE/EQ.
814  bool Invert = false;
815  bool Shift = false;
816  bool Convert = true;
817  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
818   default:
819    Convert = false;
820    break;
821   case MSP430CC::COND_HS:
822     // Res = SRW & 1, no processing is required
823     break;
824   case MSP430CC::COND_LO:
825     // Res = ~(SRW & 1)
826     Invert = true;
827     break;
828   case MSP430CC::COND_NE:
829     if (andCC) {
830       // C = ~Z, thus Res = SRW & 1, no processing is required
831     } else {
832       // Res = ~((SRW >> 1) & 1)
833       Shift = true;
834       Invert = true;
835     }
836     break;
837   case MSP430CC::COND_E:
838     Shift = true;
839     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
840     // Res = (SRW >> 1) & 1 is 1 word shorter.
841     break;
842  }
843  EVT VT = Op.getValueType();
844  SDValue One  = DAG.getConstant(1, VT);
845  if (Convert) {
846    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
847                                    MVT::i16, Flag);
848    if (Shift)
849      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
850      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
851    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
852    if (Invert)
853      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
854    return SR;
855  } else {
856    SDValue Zero = DAG.getConstant(0, VT);
857    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
858    SmallVector<SDValue, 4> Ops;
859    Ops.push_back(One);
860    Ops.push_back(Zero);
861    Ops.push_back(TargetCC);
862    Ops.push_back(Flag);
863    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
864  }
865}
866
867SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
868                                             SelectionDAG &DAG) const {
869  SDValue LHS    = Op.getOperand(0);
870  SDValue RHS    = Op.getOperand(1);
871  SDValue TrueV  = Op.getOperand(2);
872  SDValue FalseV = Op.getOperand(3);
873  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
874  DebugLoc dl    = Op.getDebugLoc();
875
876  SDValue TargetCC;
877  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
878
879  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
880  SmallVector<SDValue, 4> Ops;
881  Ops.push_back(TrueV);
882  Ops.push_back(FalseV);
883  Ops.push_back(TargetCC);
884  Ops.push_back(Flag);
885
886  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
887}
888
889SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
890                                               SelectionDAG &DAG) const {
891  SDValue Val = Op.getOperand(0);
892  EVT VT      = Op.getValueType();
893  DebugLoc dl = Op.getDebugLoc();
894
895  assert(VT == MVT::i16 && "Only support i16 for now!");
896
897  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
898                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
899                     DAG.getValueType(Val.getValueType()));
900}
901
902SDValue
903MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
904  MachineFunction &MF = DAG.getMachineFunction();
905  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
906  int ReturnAddrIndex = FuncInfo->getRAIndex();
907
908  if (ReturnAddrIndex == 0) {
909    // Set up a frame object for the return address.
910    uint64_t SlotSize = TD->getPointerSize();
911    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
912                                                           true);
913    FuncInfo->setRAIndex(ReturnAddrIndex);
914  }
915
916  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
917}
918
919SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
920                                              SelectionDAG &DAG) const {
921  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
922  MFI->setReturnAddressIsTaken(true);
923
924  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
925  DebugLoc dl = Op.getDebugLoc();
926
927  if (Depth > 0) {
928    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
929    SDValue Offset =
930      DAG.getConstant(TD->getPointerSize(), MVT::i16);
931    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
932                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
933                                   FrameAddr, Offset),
934                       MachinePointerInfo(), false, false, false, 0);
935  }
936
937  // Just load the return address.
938  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
939  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
940                     RetAddrFI, MachinePointerInfo(), false, false, false, 0);
941}
942
943SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
944                                             SelectionDAG &DAG) const {
945  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
946  MFI->setFrameAddressIsTaken(true);
947
948  EVT VT = Op.getValueType();
949  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
950  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
951  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
952                                         MSP430::FPW, VT);
953  while (Depth--)
954    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
955                            MachinePointerInfo(),
956                            false, false, false, 0);
957  return FrameAddr;
958}
959
960/// getPostIndexedAddressParts - returns true by value, base pointer and
961/// offset pointer and addressing mode by reference if this node can be
962/// combined with a load / store to form a post-indexed load / store.
963bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
964                                                      SDValue &Base,
965                                                      SDValue &Offset,
966                                                      ISD::MemIndexedMode &AM,
967                                                      SelectionDAG &DAG) const {
968
969  LoadSDNode *LD = cast<LoadSDNode>(N);
970  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
971    return false;
972
973  EVT VT = LD->getMemoryVT();
974  if (VT != MVT::i8 && VT != MVT::i16)
975    return false;
976
977  if (Op->getOpcode() != ISD::ADD)
978    return false;
979
980  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
981    uint64_t RHSC = RHS->getZExtValue();
982    if ((VT == MVT::i16 && RHSC != 2) ||
983        (VT == MVT::i8 && RHSC != 1))
984      return false;
985
986    Base = Op->getOperand(0);
987    Offset = DAG.getConstant(RHSC, VT);
988    AM = ISD::POST_INC;
989    return true;
990  }
991
992  return false;
993}
994
995
996const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
997  switch (Opcode) {
998  default: return NULL;
999  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
1000  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
1001  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
1002  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
1003  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
1004  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
1005  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
1006  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
1007  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
1008  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
1009  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
1010  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
1011  }
1012}
1013
1014bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1015                                          Type *Ty2) const {
1016  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1017    return false;
1018
1019  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1020}
1021
1022bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1023  if (!VT1.isInteger() || !VT2.isInteger())
1024    return false;
1025
1026  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1027}
1028
1029bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1030  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1031  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1032}
1033
1034bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1035  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1036  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1037}
1038
1039//===----------------------------------------------------------------------===//
1040//  Other Lowering Code
1041//===----------------------------------------------------------------------===//
1042
1043MachineBasicBlock*
1044MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1045                                     MachineBasicBlock *BB) const {
1046  MachineFunction *F = BB->getParent();
1047  MachineRegisterInfo &RI = F->getRegInfo();
1048  DebugLoc dl = MI->getDebugLoc();
1049  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1050
1051  unsigned Opc;
1052  const TargetRegisterClass * RC;
1053  switch (MI->getOpcode()) {
1054  default: llvm_unreachable("Invalid shift opcode!");
1055  case MSP430::Shl8:
1056   Opc = MSP430::SHL8r1;
1057   RC = &MSP430::GR8RegClass;
1058   break;
1059  case MSP430::Shl16:
1060   Opc = MSP430::SHL16r1;
1061   RC = &MSP430::GR16RegClass;
1062   break;
1063  case MSP430::Sra8:
1064   Opc = MSP430::SAR8r1;
1065   RC = &MSP430::GR8RegClass;
1066   break;
1067  case MSP430::Sra16:
1068   Opc = MSP430::SAR16r1;
1069   RC = &MSP430::GR16RegClass;
1070   break;
1071  case MSP430::Srl8:
1072   Opc = MSP430::SAR8r1c;
1073   RC = &MSP430::GR8RegClass;
1074   break;
1075  case MSP430::Srl16:
1076   Opc = MSP430::SAR16r1c;
1077   RC = &MSP430::GR16RegClass;
1078   break;
1079  }
1080
1081  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1082  MachineFunction::iterator I = BB;
1083  ++I;
1084
1085  // Create loop block
1086  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1087  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1088
1089  F->insert(I, LoopBB);
1090  F->insert(I, RemBB);
1091
1092  // Update machine-CFG edges by transferring all successors of the current
1093  // block to the block containing instructions after shift.
1094  RemBB->splice(RemBB->begin(), BB,
1095                llvm::next(MachineBasicBlock::iterator(MI)),
1096                BB->end());
1097  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1098
1099  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1100  BB->addSuccessor(LoopBB);
1101  BB->addSuccessor(RemBB);
1102  LoopBB->addSuccessor(RemBB);
1103  LoopBB->addSuccessor(LoopBB);
1104
1105  unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1106  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1107  unsigned ShiftReg = RI.createVirtualRegister(RC);
1108  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1109  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1110  unsigned SrcReg = MI->getOperand(1).getReg();
1111  unsigned DstReg = MI->getOperand(0).getReg();
1112
1113  // BB:
1114  // cmp 0, N
1115  // je RemBB
1116  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1117    .addReg(ShiftAmtSrcReg).addImm(0);
1118  BuildMI(BB, dl, TII.get(MSP430::JCC))
1119    .addMBB(RemBB)
1120    .addImm(MSP430CC::COND_E);
1121
1122  // LoopBB:
1123  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1124  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1125  // ShiftReg2 = shift ShiftReg
1126  // ShiftAmt2 = ShiftAmt - 1;
1127  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1128    .addReg(SrcReg).addMBB(BB)
1129    .addReg(ShiftReg2).addMBB(LoopBB);
1130  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1131    .addReg(ShiftAmtSrcReg).addMBB(BB)
1132    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1133  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1134    .addReg(ShiftReg);
1135  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1136    .addReg(ShiftAmtReg).addImm(1);
1137  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1138    .addMBB(LoopBB)
1139    .addImm(MSP430CC::COND_NE);
1140
1141  // RemBB:
1142  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1143  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1144    .addReg(SrcReg).addMBB(BB)
1145    .addReg(ShiftReg2).addMBB(LoopBB);
1146
1147  MI->eraseFromParent();   // The pseudo instruction is gone now.
1148  return RemBB;
1149}
1150
1151MachineBasicBlock*
1152MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1153                                                  MachineBasicBlock *BB) const {
1154  unsigned Opc = MI->getOpcode();
1155
1156  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1157      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1158      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1159    return EmitShiftInstr(MI, BB);
1160
1161  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1162  DebugLoc dl = MI->getDebugLoc();
1163
1164  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1165         "Unexpected instr type to insert");
1166
1167  // To "insert" a SELECT instruction, we actually have to insert the diamond
1168  // control-flow pattern.  The incoming instruction knows the destination vreg
1169  // to set, the condition code register to branch on, the true/false values to
1170  // select between, and a branch opcode to use.
1171  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1172  MachineFunction::iterator I = BB;
1173  ++I;
1174
1175  //  thisMBB:
1176  //  ...
1177  //   TrueVal = ...
1178  //   cmpTY ccX, r1, r2
1179  //   jCC copy1MBB
1180  //   fallthrough --> copy0MBB
1181  MachineBasicBlock *thisMBB = BB;
1182  MachineFunction *F = BB->getParent();
1183  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1184  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1185  F->insert(I, copy0MBB);
1186  F->insert(I, copy1MBB);
1187  // Update machine-CFG edges by transferring all successors of the current
1188  // block to the new block which will contain the Phi node for the select.
1189  copy1MBB->splice(copy1MBB->begin(), BB,
1190                   llvm::next(MachineBasicBlock::iterator(MI)),
1191                   BB->end());
1192  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1193  // Next, add the true and fallthrough blocks as its successors.
1194  BB->addSuccessor(copy0MBB);
1195  BB->addSuccessor(copy1MBB);
1196
1197  BuildMI(BB, dl, TII.get(MSP430::JCC))
1198    .addMBB(copy1MBB)
1199    .addImm(MI->getOperand(3).getImm());
1200
1201  //  copy0MBB:
1202  //   %FalseValue = ...
1203  //   # fallthrough to copy1MBB
1204  BB = copy0MBB;
1205
1206  // Update machine-CFG edges
1207  BB->addSuccessor(copy1MBB);
1208
1209  //  copy1MBB:
1210  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1211  //  ...
1212  BB = copy1MBB;
1213  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1214          MI->getOperand(0).getReg())
1215    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1216    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1217
1218  MI->eraseFromParent();   // The pseudo instruction is gone now.
1219  return BB;
1220}
1221