MSP430ISelLowering.cpp revision 7a2bdde0a0eebcd2125055e0eacaca040f0b766c 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430TargetMachine.h"
20#include "MSP430Subtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CallingConv.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/GlobalAlias.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/CodeGen/SelectionDAGISel.h"
34#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
35#include "llvm/CodeGen/ValueTypes.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/ADT/VectorExtras.h"
41using namespace llvm;
42
43typedef enum {
44  NoHWMult,
45  HWMultIntr,
46  HWMultNoIntr
47} HWMultUseMode;
48
49static cl::opt<HWMultUseMode>
50HWMultMode("msp430-hwmult-mode",
51           cl::desc("Hardware multiplier use mode"),
52           cl::init(HWMultNoIntr),
53           cl::values(
54             clEnumValN(NoHWMult, "no",
55                "Do not use hardware multiplier"),
56             clEnumValN(HWMultIntr, "interrupts",
57                "Assume hardware multiplier can be used inside interrupts"),
58             clEnumValN(HWMultNoIntr, "use",
59                "Assume hardware multiplier cannot be used inside interrupts"),
60             clEnumValEnd));
61
62MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
63  TargetLowering(tm, new TargetLoweringObjectFileELF()),
64  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
65
66  TD = getTargetData();
67
68  // Set up the register classes.
69  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
70  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
71
72  // Compute derived properties from the register classes
73  computeRegisterProperties();
74
75  // Provide all sorts of operation actions
76
77  // Division is expensive
78  setIntDivIsCheap(false);
79
80  setStackPointerRegisterToSaveRestore(MSP430::SPW);
81  setBooleanContents(ZeroOrOneBooleanContent);
82  setSchedulingPreference(Sched::Latency);
83
84  // We have post-incremented loads / stores.
85  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
86  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
87
88  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
89  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
90  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
91  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
92  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
93
94  // We don't have any truncstores
95  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
96
97  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
98  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
99  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
100  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
101  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
102  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
103  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
104  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
105  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
106  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
107  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
108  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
109  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
110  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
111  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
112  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
113  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
114  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
115  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
116  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
117  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
118  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
119  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
120  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
121  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
122  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
123
124  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
125  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
126  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
127  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
128  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
129  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
130
131  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
132  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
133  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
134  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
135  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
137
138  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
139
140  // FIXME: Implement efficiently multiplication by a constant
141  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
142  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
143  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
144  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
145  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
146  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
147  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
148  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
149  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
150  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
151
152  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
153  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
154  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
155  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
156  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
157  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
158  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
159  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
160  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
161  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
162  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
163  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
164
165  // Libcalls names.
166  if (HWMultMode == HWMultIntr) {
167    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
168    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
169  } else if (HWMultMode == HWMultNoIntr) {
170    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
171    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
172  }
173}
174
175SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
176                                             SelectionDAG &DAG) const {
177  switch (Op.getOpcode()) {
178  case ISD::SHL: // FALLTHROUGH
179  case ISD::SRL:
180  case ISD::SRA:              return LowerShifts(Op, DAG);
181  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
182  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
183  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
184  case ISD::SETCC:            return LowerSETCC(Op, DAG);
185  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
186  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
187  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
188  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
189  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
190  default:
191    llvm_unreachable("unimplemented operand");
192    return SDValue();
193  }
194}
195
196/// getFunctionAlignment - Return the Log2 alignment of this function.
197unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
198  return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
199}
200
201//===----------------------------------------------------------------------===//
202//                       MSP430 Inline Assembly Support
203//===----------------------------------------------------------------------===//
204
205/// getConstraintType - Given a constraint letter, return the type of
206/// constraint it is for this target.
207TargetLowering::ConstraintType
208MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
209  if (Constraint.size() == 1) {
210    switch (Constraint[0]) {
211    case 'r':
212      return C_RegisterClass;
213    default:
214      break;
215    }
216  }
217  return TargetLowering::getConstraintType(Constraint);
218}
219
220std::pair<unsigned, const TargetRegisterClass*>
221MSP430TargetLowering::
222getRegForInlineAsmConstraint(const std::string &Constraint,
223                             EVT VT) const {
224  if (Constraint.size() == 1) {
225    // GCC Constraint Letters
226    switch (Constraint[0]) {
227    default: break;
228    case 'r':   // GENERAL_REGS
229      if (VT == MVT::i8)
230        return std::make_pair(0U, MSP430::GR8RegisterClass);
231
232      return std::make_pair(0U, MSP430::GR16RegisterClass);
233    }
234  }
235
236  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
237}
238
239//===----------------------------------------------------------------------===//
240//                      Calling Convention Implementation
241//===----------------------------------------------------------------------===//
242
243#include "MSP430GenCallingConv.inc"
244
245SDValue
246MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
247                                           CallingConv::ID CallConv,
248                                           bool isVarArg,
249                                           const SmallVectorImpl<ISD::InputArg>
250                                             &Ins,
251                                           DebugLoc dl,
252                                           SelectionDAG &DAG,
253                                           SmallVectorImpl<SDValue> &InVals)
254                                             const {
255
256  switch (CallConv) {
257  default:
258    llvm_unreachable("Unsupported calling convention");
259  case CallingConv::C:
260  case CallingConv::Fast:
261    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
262  case CallingConv::MSP430_INTR:
263   if (Ins.empty())
264     return Chain;
265   else {
266    report_fatal_error("ISRs cannot have arguments");
267    return SDValue();
268   }
269  }
270}
271
272SDValue
273MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
274                                CallingConv::ID CallConv, bool isVarArg,
275                                bool &isTailCall,
276                                const SmallVectorImpl<ISD::OutputArg> &Outs,
277                                const SmallVectorImpl<SDValue> &OutVals,
278                                const SmallVectorImpl<ISD::InputArg> &Ins,
279                                DebugLoc dl, SelectionDAG &DAG,
280                                SmallVectorImpl<SDValue> &InVals) const {
281  // MSP430 target does not yet support tail call optimization.
282  isTailCall = false;
283
284  switch (CallConv) {
285  default:
286    llvm_unreachable("Unsupported calling convention");
287  case CallingConv::Fast:
288  case CallingConv::C:
289    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
290                          Outs, OutVals, Ins, dl, DAG, InVals);
291  case CallingConv::MSP430_INTR:
292    report_fatal_error("ISRs cannot be called directly");
293    return SDValue();
294  }
295}
296
297/// LowerCCCArguments - transform physical registers into virtual registers and
298/// generate load operations for arguments places on the stack.
299// FIXME: struct return stuff
300// FIXME: varargs
301SDValue
302MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
303                                        CallingConv::ID CallConv,
304                                        bool isVarArg,
305                                        const SmallVectorImpl<ISD::InputArg>
306                                          &Ins,
307                                        DebugLoc dl,
308                                        SelectionDAG &DAG,
309                                        SmallVectorImpl<SDValue> &InVals)
310                                          const {
311  MachineFunction &MF = DAG.getMachineFunction();
312  MachineFrameInfo *MFI = MF.getFrameInfo();
313  MachineRegisterInfo &RegInfo = MF.getRegInfo();
314
315  // Assign locations to all of the incoming arguments.
316  SmallVector<CCValAssign, 16> ArgLocs;
317  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
318                 ArgLocs, *DAG.getContext());
319  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
320
321  assert(!isVarArg && "Varargs not supported yet");
322
323  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
324    CCValAssign &VA = ArgLocs[i];
325    if (VA.isRegLoc()) {
326      // Arguments passed in registers
327      EVT RegVT = VA.getLocVT();
328      switch (RegVT.getSimpleVT().SimpleTy) {
329      default:
330        {
331#ifndef NDEBUG
332          errs() << "LowerFormalArguments Unhandled argument type: "
333               << RegVT.getSimpleVT().SimpleTy << "\n";
334#endif
335          llvm_unreachable(0);
336        }
337      case MVT::i16:
338        unsigned VReg =
339          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
340        RegInfo.addLiveIn(VA.getLocReg(), VReg);
341        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
342
343        // If this is an 8-bit value, it is really passed promoted to 16
344        // bits. Insert an assert[sz]ext to capture this, then truncate to the
345        // right size.
346        if (VA.getLocInfo() == CCValAssign::SExt)
347          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
348                                 DAG.getValueType(VA.getValVT()));
349        else if (VA.getLocInfo() == CCValAssign::ZExt)
350          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
351                                 DAG.getValueType(VA.getValVT()));
352
353        if (VA.getLocInfo() != CCValAssign::Full)
354          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
355
356        InVals.push_back(ArgValue);
357      }
358    } else {
359      // Sanity check
360      assert(VA.isMemLoc());
361      // Load the argument to a virtual register
362      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
363      if (ObjSize > 2) {
364        errs() << "LowerFormalArguments Unhandled argument type: "
365             << EVT(VA.getLocVT()).getEVTString()
366             << "\n";
367      }
368      // Create the frame index object for this incoming parameter...
369      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
370
371      // Create the SelectionDAG nodes corresponding to a load
372      //from this parameter
373      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
374      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
375                                   MachinePointerInfo::getFixedStack(FI),
376                                   false, false, 0));
377    }
378  }
379
380  return Chain;
381}
382
383SDValue
384MSP430TargetLowering::LowerReturn(SDValue Chain,
385                                  CallingConv::ID CallConv, bool isVarArg,
386                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
387                                  const SmallVectorImpl<SDValue> &OutVals,
388                                  DebugLoc dl, SelectionDAG &DAG) const {
389
390  // CCValAssign - represent the assignment of the return value to a location
391  SmallVector<CCValAssign, 16> RVLocs;
392
393  // ISRs cannot return any value.
394  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
395    report_fatal_error("ISRs cannot return any value");
396    return SDValue();
397  }
398
399  // CCState - Info about the registers and stack slot.
400  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
401                 RVLocs, *DAG.getContext());
402
403  // Analize return values.
404  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
405
406  // If this is the first return lowered for this function, add the regs to the
407  // liveout set for the function.
408  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
409    for (unsigned i = 0; i != RVLocs.size(); ++i)
410      if (RVLocs[i].isRegLoc())
411        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
412  }
413
414  SDValue Flag;
415
416  // Copy the result values into the output registers.
417  for (unsigned i = 0; i != RVLocs.size(); ++i) {
418    CCValAssign &VA = RVLocs[i];
419    assert(VA.isRegLoc() && "Can only return in registers!");
420
421    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
422                             OutVals[i], Flag);
423
424    // Guarantee that all emitted copies are stuck together,
425    // avoiding something bad.
426    Flag = Chain.getValue(1);
427  }
428
429  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
430                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
431
432  if (Flag.getNode())
433    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
434
435  // Return Void
436  return DAG.getNode(Opc, dl, MVT::Other, Chain);
437}
438
439/// LowerCCCCallTo - functions arguments are copied from virtual regs to
440/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
441/// TODO: sret.
442SDValue
443MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
444                                     CallingConv::ID CallConv, bool isVarArg,
445                                     bool isTailCall,
446                                     const SmallVectorImpl<ISD::OutputArg>
447                                       &Outs,
448                                     const SmallVectorImpl<SDValue> &OutVals,
449                                     const SmallVectorImpl<ISD::InputArg> &Ins,
450                                     DebugLoc dl, SelectionDAG &DAG,
451                                     SmallVectorImpl<SDValue> &InVals) const {
452  // Analyze operands of the call, assigning locations to each operand.
453  SmallVector<CCValAssign, 16> ArgLocs;
454  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
455                 ArgLocs, *DAG.getContext());
456
457  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
458
459  // Get a count of how many bytes are to be pushed on the stack.
460  unsigned NumBytes = CCInfo.getNextStackOffset();
461
462  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
463                                                      getPointerTy(), true));
464
465  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
466  SmallVector<SDValue, 12> MemOpChains;
467  SDValue StackPtr;
468
469  // Walk the register/memloc assignments, inserting copies/loads.
470  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
471    CCValAssign &VA = ArgLocs[i];
472
473    SDValue Arg = OutVals[i];
474
475    // Promote the value if needed.
476    switch (VA.getLocInfo()) {
477      default: llvm_unreachable("Unknown loc info!");
478      case CCValAssign::Full: break;
479      case CCValAssign::SExt:
480        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
481        break;
482      case CCValAssign::ZExt:
483        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
484        break;
485      case CCValAssign::AExt:
486        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
487        break;
488    }
489
490    // Arguments that can be passed on register must be kept at RegsToPass
491    // vector
492    if (VA.isRegLoc()) {
493      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
494    } else {
495      assert(VA.isMemLoc());
496
497      if (StackPtr.getNode() == 0)
498        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
499
500      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
501                                   StackPtr,
502                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
503
504
505      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
506                                         MachinePointerInfo(),false, false, 0));
507    }
508  }
509
510  // Transform all store nodes into one single node because all store nodes are
511  // independent of each other.
512  if (!MemOpChains.empty())
513    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
514                        &MemOpChains[0], MemOpChains.size());
515
516  // Build a sequence of copy-to-reg nodes chained together with token chain and
517  // flag operands which copy the outgoing args into registers.  The InFlag in
518  // necessary since all emitted instructions must be stuck together.
519  SDValue InFlag;
520  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
521    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
522                             RegsToPass[i].second, InFlag);
523    InFlag = Chain.getValue(1);
524  }
525
526  // If the callee is a GlobalAddress node (quite common, every direct call is)
527  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
528  // Likewise ExternalSymbol -> TargetExternalSymbol.
529  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
530    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
531  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
532    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
533
534  // Returns a chain & a flag for retval copy to use.
535  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
536  SmallVector<SDValue, 8> Ops;
537  Ops.push_back(Chain);
538  Ops.push_back(Callee);
539
540  // Add argument registers to the end of the list so that they are
541  // known live into the call.
542  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
543    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
544                                  RegsToPass[i].second.getValueType()));
545
546  if (InFlag.getNode())
547    Ops.push_back(InFlag);
548
549  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
550  InFlag = Chain.getValue(1);
551
552  // Create the CALLSEQ_END node.
553  Chain = DAG.getCALLSEQ_END(Chain,
554                             DAG.getConstant(NumBytes, getPointerTy(), true),
555                             DAG.getConstant(0, getPointerTy(), true),
556                             InFlag);
557  InFlag = Chain.getValue(1);
558
559  // Handle result values, copying them out of physregs into vregs that we
560  // return.
561  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
562                         DAG, InVals);
563}
564
565/// LowerCallResult - Lower the result values of a call into the
566/// appropriate copies out of appropriate physical registers.
567///
568SDValue
569MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
570                                      CallingConv::ID CallConv, bool isVarArg,
571                                      const SmallVectorImpl<ISD::InputArg> &Ins,
572                                      DebugLoc dl, SelectionDAG &DAG,
573                                      SmallVectorImpl<SDValue> &InVals) const {
574
575  // Assign locations to each value returned by this call.
576  SmallVector<CCValAssign, 16> RVLocs;
577  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
578                 RVLocs, *DAG.getContext());
579
580  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
581
582  // Copy all of the result registers out of their specified physreg.
583  for (unsigned i = 0; i != RVLocs.size(); ++i) {
584    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
585                               RVLocs[i].getValVT(), InFlag).getValue(1);
586    InFlag = Chain.getValue(2);
587    InVals.push_back(Chain.getValue(0));
588  }
589
590  return Chain;
591}
592
593SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
594                                          SelectionDAG &DAG) const {
595  unsigned Opc = Op.getOpcode();
596  SDNode* N = Op.getNode();
597  EVT VT = Op.getValueType();
598  DebugLoc dl = N->getDebugLoc();
599
600  // Expand non-constant shifts to loops:
601  if (!isa<ConstantSDNode>(N->getOperand(1)))
602    switch (Opc) {
603    default:
604      assert(0 && "Invalid shift opcode!");
605    case ISD::SHL:
606      return DAG.getNode(MSP430ISD::SHL, dl,
607                         VT, N->getOperand(0), N->getOperand(1));
608    case ISD::SRA:
609      return DAG.getNode(MSP430ISD::SRA, dl,
610                         VT, N->getOperand(0), N->getOperand(1));
611    case ISD::SRL:
612      return DAG.getNode(MSP430ISD::SRL, dl,
613                         VT, N->getOperand(0), N->getOperand(1));
614    }
615
616  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
617
618  // Expand the stuff into sequence of shifts.
619  // FIXME: for some shift amounts this might be done better!
620  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
621  SDValue Victim = N->getOperand(0);
622
623  if (Opc == ISD::SRL && ShiftAmount) {
624    // Emit a special goodness here:
625    // srl A, 1 => clrc; rrc A
626    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
627    ShiftAmount -= 1;
628  }
629
630  while (ShiftAmount--)
631    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
632                         dl, VT, Victim);
633
634  return Victim;
635}
636
637SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
638                                                 SelectionDAG &DAG) const {
639  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
640  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
641
642  // Create the TargetGlobalAddress node, folding in the constant offset.
643  SDValue Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
644                                              getPointerTy(), Offset);
645  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
646                     getPointerTy(), Result);
647}
648
649SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
650                                                  SelectionDAG &DAG) const {
651  DebugLoc dl = Op.getDebugLoc();
652  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
653  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
654
655  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
656}
657
658SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
659                                                SelectionDAG &DAG) const {
660  DebugLoc dl = Op.getDebugLoc();
661  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
662  SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
663
664  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
665}
666
667static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
668                       ISD::CondCode CC,
669                       DebugLoc dl, SelectionDAG &DAG) {
670  // FIXME: Handle bittests someday
671  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
672
673  // FIXME: Handle jump negative someday
674  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
675  switch (CC) {
676  default: llvm_unreachable("Invalid integer condition!");
677  case ISD::SETEQ:
678    TCC = MSP430CC::COND_E;     // aka COND_Z
679    // Minor optimization: if LHS is a constant, swap operands, then the
680    // constant can be folded into comparison.
681    if (LHS.getOpcode() == ISD::Constant)
682      std::swap(LHS, RHS);
683    break;
684  case ISD::SETNE:
685    TCC = MSP430CC::COND_NE;    // aka COND_NZ
686    // Minor optimization: if LHS is a constant, swap operands, then the
687    // constant can be folded into comparison.
688    if (LHS.getOpcode() == ISD::Constant)
689      std::swap(LHS, RHS);
690    break;
691  case ISD::SETULE:
692    std::swap(LHS, RHS);        // FALLTHROUGH
693  case ISD::SETUGE:
694    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
695    // fold constant into instruction.
696    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
697      LHS = RHS;
698      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
699      TCC = MSP430CC::COND_LO;
700      break;
701    }
702    TCC = MSP430CC::COND_HS;    // aka COND_C
703    break;
704  case ISD::SETUGT:
705    std::swap(LHS, RHS);        // FALLTHROUGH
706  case ISD::SETULT:
707    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
708    // fold constant into instruction.
709    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
710      LHS = RHS;
711      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
712      TCC = MSP430CC::COND_HS;
713      break;
714    }
715    TCC = MSP430CC::COND_LO;    // aka COND_NC
716    break;
717  case ISD::SETLE:
718    std::swap(LHS, RHS);        // FALLTHROUGH
719  case ISD::SETGE:
720    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
721    // fold constant into instruction.
722    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
723      LHS = RHS;
724      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
725      TCC = MSP430CC::COND_L;
726      break;
727    }
728    TCC = MSP430CC::COND_GE;
729    break;
730  case ISD::SETGT:
731    std::swap(LHS, RHS);        // FALLTHROUGH
732  case ISD::SETLT:
733    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
734    // fold constant into instruction.
735    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
736      LHS = RHS;
737      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
738      TCC = MSP430CC::COND_GE;
739      break;
740    }
741    TCC = MSP430CC::COND_L;
742    break;
743  }
744
745  TargetCC = DAG.getConstant(TCC, MVT::i8);
746  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
747}
748
749
750SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
751  SDValue Chain = Op.getOperand(0);
752  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
753  SDValue LHS   = Op.getOperand(2);
754  SDValue RHS   = Op.getOperand(3);
755  SDValue Dest  = Op.getOperand(4);
756  DebugLoc dl   = Op.getDebugLoc();
757
758  SDValue TargetCC;
759  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
760
761  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
762                     Chain, Dest, TargetCC, Flag);
763}
764
765SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
766  SDValue LHS   = Op.getOperand(0);
767  SDValue RHS   = Op.getOperand(1);
768  DebugLoc dl   = Op.getDebugLoc();
769
770  // If we are doing an AND and testing against zero, then the CMP
771  // will not be generated.  The AND (or BIT) will generate the condition codes,
772  // but they are different from CMP.
773  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
774  // lowering & isel wouldn't diverge.
775  bool andCC = false;
776  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
777    if (RHSC->isNullValue() && LHS.hasOneUse() &&
778        (LHS.getOpcode() == ISD::AND ||
779         (LHS.getOpcode() == ISD::TRUNCATE &&
780          LHS.getOperand(0).getOpcode() == ISD::AND))) {
781      andCC = true;
782    }
783  }
784  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
785  SDValue TargetCC;
786  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
787
788  // Get the condition codes directly from the status register, if its easy.
789  // Otherwise a branch will be generated.  Note that the AND and BIT
790  // instructions generate different flags than CMP, the carry bit can be used
791  // for NE/EQ.
792  bool Invert = false;
793  bool Shift = false;
794  bool Convert = true;
795  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
796   default:
797    Convert = false;
798    break;
799   case MSP430CC::COND_HS:
800     // Res = SRW & 1, no processing is required
801     break;
802   case MSP430CC::COND_LO:
803     // Res = ~(SRW & 1)
804     Invert = true;
805     break;
806   case MSP430CC::COND_NE:
807     if (andCC) {
808       // C = ~Z, thus Res = SRW & 1, no processing is required
809     } else {
810       // Res = ~((SRW >> 1) & 1)
811       Shift = true;
812       Invert = true;
813     }
814     break;
815   case MSP430CC::COND_E:
816     Shift = true;
817     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
818     // Res = (SRW >> 1) & 1 is 1 word shorter.
819     break;
820  }
821  EVT VT = Op.getValueType();
822  SDValue One  = DAG.getConstant(1, VT);
823  if (Convert) {
824    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
825                                    MVT::i16, Flag);
826    if (Shift)
827      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
828      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
829    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
830    if (Invert)
831      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
832    return SR;
833  } else {
834    SDValue Zero = DAG.getConstant(0, VT);
835    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
836    SmallVector<SDValue, 4> Ops;
837    Ops.push_back(One);
838    Ops.push_back(Zero);
839    Ops.push_back(TargetCC);
840    Ops.push_back(Flag);
841    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
842  }
843}
844
845SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
846                                             SelectionDAG &DAG) const {
847  SDValue LHS    = Op.getOperand(0);
848  SDValue RHS    = Op.getOperand(1);
849  SDValue TrueV  = Op.getOperand(2);
850  SDValue FalseV = Op.getOperand(3);
851  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
852  DebugLoc dl    = Op.getDebugLoc();
853
854  SDValue TargetCC;
855  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
856
857  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
858  SmallVector<SDValue, 4> Ops;
859  Ops.push_back(TrueV);
860  Ops.push_back(FalseV);
861  Ops.push_back(TargetCC);
862  Ops.push_back(Flag);
863
864  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
865}
866
867SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
868                                               SelectionDAG &DAG) const {
869  SDValue Val = Op.getOperand(0);
870  EVT VT      = Op.getValueType();
871  DebugLoc dl = Op.getDebugLoc();
872
873  assert(VT == MVT::i16 && "Only support i16 for now!");
874
875  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
876                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
877                     DAG.getValueType(Val.getValueType()));
878}
879
880SDValue
881MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
882  MachineFunction &MF = DAG.getMachineFunction();
883  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
884  int ReturnAddrIndex = FuncInfo->getRAIndex();
885
886  if (ReturnAddrIndex == 0) {
887    // Set up a frame object for the return address.
888    uint64_t SlotSize = TD->getPointerSize();
889    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
890                                                           true);
891    FuncInfo->setRAIndex(ReturnAddrIndex);
892  }
893
894  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
895}
896
897SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
898                                              SelectionDAG &DAG) const {
899  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
900  MFI->setReturnAddressIsTaken(true);
901
902  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
903  DebugLoc dl = Op.getDebugLoc();
904
905  if (Depth > 0) {
906    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
907    SDValue Offset =
908      DAG.getConstant(TD->getPointerSize(), MVT::i16);
909    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
910                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
911                                   FrameAddr, Offset),
912                       MachinePointerInfo(), false, false, 0);
913  }
914
915  // Just load the return address.
916  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
917  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
918                     RetAddrFI, MachinePointerInfo(), false, false, 0);
919}
920
921SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
922                                             SelectionDAG &DAG) const {
923  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
924  MFI->setFrameAddressIsTaken(true);
925
926  EVT VT = Op.getValueType();
927  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
928  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
929  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
930                                         MSP430::FPW, VT);
931  while (Depth--)
932    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
933                            MachinePointerInfo(),
934                            false, false, 0);
935  return FrameAddr;
936}
937
938/// getPostIndexedAddressParts - returns true by value, base pointer and
939/// offset pointer and addressing mode by reference if this node can be
940/// combined with a load / store to form a post-indexed load / store.
941bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
942                                                      SDValue &Base,
943                                                      SDValue &Offset,
944                                                      ISD::MemIndexedMode &AM,
945                                                      SelectionDAG &DAG) const {
946
947  LoadSDNode *LD = cast<LoadSDNode>(N);
948  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
949    return false;
950
951  EVT VT = LD->getMemoryVT();
952  if (VT != MVT::i8 && VT != MVT::i16)
953    return false;
954
955  if (Op->getOpcode() != ISD::ADD)
956    return false;
957
958  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
959    uint64_t RHSC = RHS->getZExtValue();
960    if ((VT == MVT::i16 && RHSC != 2) ||
961        (VT == MVT::i8 && RHSC != 1))
962      return false;
963
964    Base = Op->getOperand(0);
965    Offset = DAG.getConstant(RHSC, VT);
966    AM = ISD::POST_INC;
967    return true;
968  }
969
970  return false;
971}
972
973
974const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
975  switch (Opcode) {
976  default: return NULL;
977  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
978  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
979  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
980  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
981  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
982  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
983  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
984  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
985  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
986  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
987  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
988  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
989  }
990}
991
992bool MSP430TargetLowering::isTruncateFree(const Type *Ty1,
993                                          const Type *Ty2) const {
994  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
995    return false;
996
997  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
998}
999
1000bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1001  if (!VT1.isInteger() || !VT2.isInteger())
1002    return false;
1003
1004  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1005}
1006
1007bool MSP430TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
1008  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1009  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1010}
1011
1012bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1013  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1014  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1015}
1016
1017//===----------------------------------------------------------------------===//
1018//  Other Lowering Code
1019//===----------------------------------------------------------------------===//
1020
1021MachineBasicBlock*
1022MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1023                                     MachineBasicBlock *BB) const {
1024  MachineFunction *F = BB->getParent();
1025  MachineRegisterInfo &RI = F->getRegInfo();
1026  DebugLoc dl = MI->getDebugLoc();
1027  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1028
1029  unsigned Opc;
1030  const TargetRegisterClass * RC;
1031  switch (MI->getOpcode()) {
1032  default:
1033    assert(0 && "Invalid shift opcode!");
1034  case MSP430::Shl8:
1035   Opc = MSP430::SHL8r1;
1036   RC = MSP430::GR8RegisterClass;
1037   break;
1038  case MSP430::Shl16:
1039   Opc = MSP430::SHL16r1;
1040   RC = MSP430::GR16RegisterClass;
1041   break;
1042  case MSP430::Sra8:
1043   Opc = MSP430::SAR8r1;
1044   RC = MSP430::GR8RegisterClass;
1045   break;
1046  case MSP430::Sra16:
1047   Opc = MSP430::SAR16r1;
1048   RC = MSP430::GR16RegisterClass;
1049   break;
1050  case MSP430::Srl8:
1051   Opc = MSP430::SAR8r1c;
1052   RC = MSP430::GR8RegisterClass;
1053   break;
1054  case MSP430::Srl16:
1055   Opc = MSP430::SAR16r1c;
1056   RC = MSP430::GR16RegisterClass;
1057   break;
1058  }
1059
1060  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1061  MachineFunction::iterator I = BB;
1062  ++I;
1063
1064  // Create loop block
1065  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1066  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1067
1068  F->insert(I, LoopBB);
1069  F->insert(I, RemBB);
1070
1071  // Update machine-CFG edges by transferring all successors of the current
1072  // block to the block containing instructions after shift.
1073  RemBB->splice(RemBB->begin(), BB,
1074                llvm::next(MachineBasicBlock::iterator(MI)),
1075                BB->end());
1076  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1077
1078  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1079  BB->addSuccessor(LoopBB);
1080  BB->addSuccessor(RemBB);
1081  LoopBB->addSuccessor(RemBB);
1082  LoopBB->addSuccessor(LoopBB);
1083
1084  unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1085  unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1086  unsigned ShiftReg = RI.createVirtualRegister(RC);
1087  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1088  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1089  unsigned SrcReg = MI->getOperand(1).getReg();
1090  unsigned DstReg = MI->getOperand(0).getReg();
1091
1092  // BB:
1093  // cmp 0, N
1094  // je RemBB
1095  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1096    .addReg(ShiftAmtSrcReg).addImm(0);
1097  BuildMI(BB, dl, TII.get(MSP430::JCC))
1098    .addMBB(RemBB)
1099    .addImm(MSP430CC::COND_E);
1100
1101  // LoopBB:
1102  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1103  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1104  // ShiftReg2 = shift ShiftReg
1105  // ShiftAmt2 = ShiftAmt - 1;
1106  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1107    .addReg(SrcReg).addMBB(BB)
1108    .addReg(ShiftReg2).addMBB(LoopBB);
1109  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1110    .addReg(ShiftAmtSrcReg).addMBB(BB)
1111    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1112  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1113    .addReg(ShiftReg);
1114  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1115    .addReg(ShiftAmtReg).addImm(1);
1116  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1117    .addMBB(LoopBB)
1118    .addImm(MSP430CC::COND_NE);
1119
1120  // RemBB:
1121  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1122  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1123    .addReg(SrcReg).addMBB(BB)
1124    .addReg(ShiftReg2).addMBB(LoopBB);
1125
1126  MI->eraseFromParent();   // The pseudo instruction is gone now.
1127  return RemBB;
1128}
1129
1130MachineBasicBlock*
1131MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1132                                                  MachineBasicBlock *BB) const {
1133  unsigned Opc = MI->getOpcode();
1134
1135  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1136      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1137      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1138    return EmitShiftInstr(MI, BB);
1139
1140  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1141  DebugLoc dl = MI->getDebugLoc();
1142
1143  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1144         "Unexpected instr type to insert");
1145
1146  // To "insert" a SELECT instruction, we actually have to insert the diamond
1147  // control-flow pattern.  The incoming instruction knows the destination vreg
1148  // to set, the condition code register to branch on, the true/false values to
1149  // select between, and a branch opcode to use.
1150  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1151  MachineFunction::iterator I = BB;
1152  ++I;
1153
1154  //  thisMBB:
1155  //  ...
1156  //   TrueVal = ...
1157  //   cmpTY ccX, r1, r2
1158  //   jCC copy1MBB
1159  //   fallthrough --> copy0MBB
1160  MachineBasicBlock *thisMBB = BB;
1161  MachineFunction *F = BB->getParent();
1162  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1163  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1164  F->insert(I, copy0MBB);
1165  F->insert(I, copy1MBB);
1166  // Update machine-CFG edges by transferring all successors of the current
1167  // block to the new block which will contain the Phi node for the select.
1168  copy1MBB->splice(copy1MBB->begin(), BB,
1169                   llvm::next(MachineBasicBlock::iterator(MI)),
1170                   BB->end());
1171  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1172  // Next, add the true and fallthrough blocks as its successors.
1173  BB->addSuccessor(copy0MBB);
1174  BB->addSuccessor(copy1MBB);
1175
1176  BuildMI(BB, dl, TII.get(MSP430::JCC))
1177    .addMBB(copy1MBB)
1178    .addImm(MI->getOperand(3).getImm());
1179
1180  //  copy0MBB:
1181  //   %FalseValue = ...
1182  //   # fallthrough to copy1MBB
1183  BB = copy0MBB;
1184
1185  // Update machine-CFG edges
1186  BB->addSuccessor(copy1MBB);
1187
1188  //  copy1MBB:
1189  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1190  //  ...
1191  BB = copy1MBB;
1192  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1193          MI->getOperand(0).getReg())
1194    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1195    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1196
1197  MI->eraseFromParent();   // The pseudo instruction is gone now.
1198  return BB;
1199}
1200