MipsAsmBackend.cpp revision fc54d9e47a1276650f14f38e7d037c9b58c8dc2d 
1//===-- MipsASMBackend.cpp - Mips Asm Backend  ----------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#include "MipsFixupKinds.h"
16#include "MCTargetDesc/MipsMCTargetDesc.h"
17#include "llvm/MC/MCAsmBackend.h"
18#include "llvm/MC/MCAssembler.h"
19#include "llvm/MC/MCDirectives.h"
20#include "llvm/MC/MCELFObjectWriter.h"
21#include "llvm/MC/MCFixupKindInfo.h"
22#include "llvm/MC/MCObjectWriter.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
26
27using namespace llvm;
28
29// Prepare value for the target space for it
30static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
31
32  // Add/subtract and shift
33  switch (Kind) {
34  default:
35    return 0;
36  case FK_GPRel_4:
37  case FK_Data_4:
38  case Mips::fixup_Mips_LO16:
39  case Mips::fixup_Mips_GPOFF_HI:
40  case Mips::fixup_Mips_GPOFF_LO:
41  case Mips::fixup_Mips_GOT_PAGE:
42  case Mips::fixup_Mips_GOT_OFST:
43  case Mips::fixup_Mips_GOT_DISP:
44    break;
45  case Mips::fixup_Mips_PC16:
46    // So far we are only using this type for branches.
47    // For branches we start 1 instruction after the branch
48    // so the displacement will be one instruction size less.
49    Value -= 4;
50    // The displacement is then divided by 4 to give us an 18 bit
51    // address range.
52    Value >>= 2;
53    break;
54  case Mips::fixup_Mips_26:
55    // So far we are only using this type for jumps.
56    // The displacement is then divided by 4 to give us an 28 bit
57    // address range.
58    Value >>= 2;
59    break;
60  case Mips::fixup_Mips_HI16:
61  case Mips::fixup_Mips_GOT_Local:
62    // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
63    Value = ((Value + 0x8000) >> 16) & 0xffff;
64    break;
65  case Mips::fixup_Mips_HIGHER:
66    // Get the 3rd 16-bits.
67    Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
68    break;
69  case Mips::fixup_Mips_HIGHEST:
70    // Get the 4th 16-bits.
71    Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
72    break;
73  }
74
75  return Value;
76}
77
78namespace {
79class MipsAsmBackend : public MCAsmBackend {
80  Triple::OSType OSType;
81  bool IsLittle; // Big or little endian
82  bool Is64Bit;  // 32 or 64 bit words
83
84public:
85  MipsAsmBackend(const Target &T,  Triple::OSType _OSType,
86                 bool _isLittle, bool _is64Bit)
87    :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {}
88
89  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
90    return createMipsELFObjectWriter(OS,
91      MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
92  }
93
94  /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
95  /// data fragment, at the offset specified by the fixup and following the
96  /// fixup kind as appropriate.
97  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
98                  uint64_t Value) const {
99    MCFixupKind Kind = Fixup.getKind();
100    Value = adjustFixupValue((unsigned)Kind, Value);
101
102    if (!Value)
103      return; // Doesn't change encoding.
104
105    // Where do we start in the object
106    unsigned Offset = Fixup.getOffset();
107    // Number of bytes we need to fixup
108    unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
109    // Used to point to big endian bytes
110    unsigned FullSize;
111
112    switch ((unsigned)Kind) {
113    case Mips::fixup_Mips_16:
114      FullSize = 2;
115      break;
116    case Mips::fixup_Mips_64:
117      FullSize = 8;
118      break;
119    default:
120      FullSize = 4;
121      break;
122    }
123
124    // Grab current value, if any, from bits.
125    uint64_t CurVal = 0;
126
127    for (unsigned i = 0; i != NumBytes; ++i) {
128      unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
129      CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
130    }
131
132    uint64_t Mask = ((uint64_t)(-1) >>
133                     (64 - getFixupKindInfo(Kind).TargetSize));
134    CurVal |= Value & Mask;
135
136    // Write out the fixed up bytes back to the code/data bits.
137    for (unsigned i = 0; i != NumBytes; ++i) {
138      unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
139      Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
140    }
141  }
142
143  unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
144
145  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
146    const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
147      // This table *must* be in same the order of fixup_* kinds in
148      // MipsFixupKinds.h.
149      //
150      // name                    offset  bits  flags
151      { "fixup_Mips_16",           0,     16,   0 },
152      { "fixup_Mips_32",           0,     32,   0 },
153      { "fixup_Mips_REL32",        0,     32,   0 },
154      { "fixup_Mips_26",           0,     26,   0 },
155      { "fixup_Mips_HI16",         0,     16,   0 },
156      { "fixup_Mips_LO16",         0,     16,   0 },
157      { "fixup_Mips_GPREL16",      0,     16,   0 },
158      { "fixup_Mips_LITERAL",      0,     16,   0 },
159      { "fixup_Mips_GOT_Global",   0,     16,   0 },
160      { "fixup_Mips_GOT_Local",    0,     16,   0 },
161      { "fixup_Mips_PC16",         0,     16,  MCFixupKindInfo::FKF_IsPCRel },
162      { "fixup_Mips_CALL16",       0,     16,   0 },
163      { "fixup_Mips_GPREL32",      0,     32,   0 },
164      { "fixup_Mips_SHIFT5",       6,      5,   0 },
165      { "fixup_Mips_SHIFT6",       6,      5,   0 },
166      { "fixup_Mips_64",           0,     64,   0 },
167      { "fixup_Mips_TLSGD",        0,     16,   0 },
168      { "fixup_Mips_GOTTPREL",     0,     16,   0 },
169      { "fixup_Mips_TPREL_HI",     0,     16,   0 },
170      { "fixup_Mips_TPREL_LO",     0,     16,   0 },
171      { "fixup_Mips_TLSLDM",       0,     16,   0 },
172      { "fixup_Mips_DTPREL_HI",    0,     16,   0 },
173      { "fixup_Mips_DTPREL_LO",    0,     16,   0 },
174      { "fixup_Mips_Branch_PCRel", 0,     16,  MCFixupKindInfo::FKF_IsPCRel },
175      { "fixup_Mips_GPOFF_HI",     0,     16,   0 },
176      { "fixup_Mips_GPOFF_LO",     0,     16,   0 },
177      { "fixup_Mips_GOT_PAGE",     0,     16,   0 },
178      { "fixup_Mips_GOT_OFST",     0,     16,   0 },
179      { "fixup_Mips_GOT_DISP",     0,     16,   0 },
180      { "fixup_Mips_HIGHER",       0,     16,   0 },
181      { "fixup_Mips_HIGHEST",      0,     16,   0 }
182    };
183
184    if (Kind < FirstTargetFixupKind)
185      return MCAsmBackend::getFixupKindInfo(Kind);
186
187    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
188           "Invalid kind!");
189    return Infos[Kind - FirstTargetFixupKind];
190  }
191
192  /// @name Target Relaxation Interfaces
193  /// @{
194
195  /// MayNeedRelaxation - Check whether the given instruction may need
196  /// relaxation.
197  ///
198  /// \param Inst - The instruction to test.
199  bool mayNeedRelaxation(const MCInst &Inst) const {
200    return false;
201  }
202
203  /// fixupNeedsRelaxation - Target specific predicate for whether a given
204  /// fixup requires the associated instruction to be relaxed.
205  bool fixupNeedsRelaxation(const MCFixup &Fixup,
206                            uint64_t Value,
207                            const MCInstFragment *DF,
208                            const MCAsmLayout &Layout) const {
209    // FIXME.
210    assert(0 && "RelaxInstruction() unimplemented");
211    return false;
212  }
213
214  /// RelaxInstruction - Relax the instruction in the given fragment
215  /// to the next wider instruction.
216  ///
217  /// \param Inst - The instruction to relax, which may be the same
218  /// as the output.
219  /// \parm Res [output] - On return, the relaxed instruction.
220  void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
221  }
222
223  /// @}
224
225  /// WriteNopData - Write an (optimal) nop sequence of Count bytes
226  /// to the given output. If the target cannot generate such a sequence,
227  /// it should return an error.
228  ///
229  /// \return - True on success.
230  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
231    // Check for a less than instruction size number of bytes
232    // FIXME: 16 bit instructions are not handled yet here.
233    // We shouldn't be using a hard coded number for instruction size.
234    if (Count % 4) return false;
235
236    uint64_t NumNops = Count / 4;
237    for (uint64_t i = 0; i != NumNops; ++i)
238      OW->Write32(0);
239    return true;
240  }
241}; // class MipsAsmBackend
242
243} // namespace
244
245// MCAsmBackend
246MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, StringRef TT) {
247  return new MipsAsmBackend(T, Triple(TT).getOS(),
248                            /*IsLittle*/true, /*Is64Bit*/false);
249}
250
251MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, StringRef TT) {
252  return new MipsAsmBackend(T, Triple(TT).getOS(),
253                            /*IsLittle*/false, /*Is64Bit*/false);
254}
255
256MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, StringRef TT) {
257  return new MipsAsmBackend(T, Triple(TT).getOS(),
258                            /*IsLittle*/true, /*Is64Bit*/true);
259}
260
261MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT) {
262  return new MipsAsmBackend(T, Triple(TT).getOS(),
263                            /*IsLittle*/false, /*Is64Bit*/true);
264}
265
266