r600_pipe.c revision 15146fd1bcbb08e44a1cbb984440ee1a5de63d48
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include <stdio.h> 24#include <errno.h> 25#include "pipe/p_defines.h" 26#include "pipe/p_state.h" 27#include "pipe/p_context.h" 28#include "tgsi/tgsi_scan.h" 29#include "tgsi/tgsi_parse.h" 30#include "tgsi/tgsi_util.h" 31#include "util/u_blitter.h" 32#include "util/u_double_list.h" 33#include "util/u_format.h" 34#include "util/u_format_s3tc.h" 35#include "util/u_transfer.h" 36#include "util/u_surface.h" 37#include "util/u_pack_color.h" 38#include "util/u_memory.h" 39#include "util/u_inlines.h" 40#include "util/u_upload_mgr.h" 41#include "vl/vl_decoder.h" 42#include "vl/vl_video_buffer.h" 43#include "os/os_time.h" 44#include "pipebuffer/pb_buffer.h" 45#include "r600.h" 46#include "r600d.h" 47#include "r600_resource.h" 48#include "r600_shader.h" 49#include "r600_pipe.h" 50 51/* 52 * pipe_context 53 */ 54static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx) 55{ 56 struct r600_screen *rscreen = ctx->screen; 57 struct r600_fence *fence = NULL; 58 59 pipe_mutex_lock(rscreen->fences.mutex); 60 61 if (!rscreen->fences.bo) { 62 /* Create the shared buffer object */ 63 rscreen->fences.bo = (struct r600_resource*) 64 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM, 65 PIPE_USAGE_STAGING, 4096); 66 if (!rscreen->fences.bo) { 67 R600_ERR("r600: failed to create bo for fence objects\n"); 68 goto out; 69 } 70 rscreen->fences.data = ctx->ws->buffer_map(rscreen->fences.bo->buf, 71 ctx->ctx.cs, 72 PIPE_TRANSFER_READ_WRITE); 73 } 74 75 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) { 76 struct r600_fence *entry; 77 78 /* Try to find a freed fence that has been signalled */ 79 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) { 80 if (rscreen->fences.data[entry->index] != 0) { 81 LIST_DELINIT(&entry->head); 82 fence = entry; 83 break; 84 } 85 } 86 } 87 88 if (!fence) { 89 /* Allocate a new fence */ 90 struct r600_fence_block *block; 91 unsigned index; 92 93 if ((rscreen->fences.next_index + 1) >= 1024) { 94 R600_ERR("r600: too many concurrent fences\n"); 95 goto out; 96 } 97 98 index = rscreen->fences.next_index++; 99 100 if (!(index % FENCE_BLOCK_SIZE)) { 101 /* Allocate a new block */ 102 block = CALLOC_STRUCT(r600_fence_block); 103 if (block == NULL) 104 goto out; 105 106 LIST_ADD(&block->head, &rscreen->fences.blocks); 107 } else { 108 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head); 109 } 110 111 fence = &block->fences[index % FENCE_BLOCK_SIZE]; 112 fence->index = index; 113 } 114 115 pipe_reference_init(&fence->reference, 1); 116 117 rscreen->fences.data[fence->index] = 0; 118 r600_context_emit_fence(&ctx->ctx, rscreen->fences.bo, fence->index, 1); 119out: 120 pipe_mutex_unlock(rscreen->fences.mutex); 121 return fence; 122} 123 124 125void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 126 unsigned flags) 127{ 128 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 129 struct r600_fence **rfence = (struct r600_fence**)fence; 130 struct pipe_query *render_cond = NULL; 131 unsigned render_cond_mode = 0; 132 133 if (rfence) 134 *rfence = r600_create_fence(rctx); 135 136 /* Disable render condition. */ 137 if (rctx->current_render_cond) { 138 render_cond = rctx->current_render_cond; 139 render_cond_mode = rctx->current_render_cond_mode; 140 ctx->render_condition(ctx, NULL, 0); 141 } 142 143 r600_context_flush(&rctx->ctx, flags); 144 145 /* Re-enable render condition. */ 146 if (render_cond) { 147 ctx->render_condition(ctx, render_cond, render_cond_mode); 148 } 149} 150 151static void r600_flush_from_st(struct pipe_context *ctx, 152 struct pipe_fence_handle **fence) 153{ 154 r600_flush(ctx, fence, 0); 155} 156 157static void r600_flush_from_winsys(void *ctx, unsigned flags) 158{ 159 r600_flush((struct pipe_context*)ctx, NULL, flags); 160} 161 162static void r600_update_num_contexts(struct r600_screen *rscreen, int diff) 163{ 164 pipe_mutex_lock(rscreen->mutex_num_contexts); 165 if (diff > 0) { 166 rscreen->num_contexts++; 167 168 if (rscreen->num_contexts > 1) 169 util_slab_set_thread_safety(&rscreen->pool_buffers, 170 UTIL_SLAB_MULTITHREADED); 171 } else { 172 rscreen->num_contexts--; 173 174 if (rscreen->num_contexts <= 1) 175 util_slab_set_thread_safety(&rscreen->pool_buffers, 176 UTIL_SLAB_SINGLETHREADED); 177 } 178 pipe_mutex_unlock(rscreen->mutex_num_contexts); 179} 180 181static void r600_destroy_context(struct pipe_context *context) 182{ 183 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context; 184 185 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 186 util_unreference_framebuffer_state(&rctx->framebuffer); 187 188 r600_context_fini(&rctx->ctx); 189 190 util_blitter_destroy(rctx->blitter); 191 192 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 193 free(rctx->states[i]); 194 } 195 196 u_vbuf_destroy(rctx->vbuf_mgr); 197 util_slab_destroy(&rctx->pool_transfers); 198 199 r600_update_num_contexts(rctx->screen, -1); 200 201 FREE(rctx); 202} 203 204static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 205{ 206 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context); 207 struct r600_screen* rscreen = (struct r600_screen *)screen; 208 209 if (rctx == NULL) 210 return NULL; 211 212 r600_update_num_contexts(rscreen, 1); 213 214 rctx->context.winsys = rscreen->screen.winsys; 215 rctx->context.screen = screen; 216 rctx->context.priv = priv; 217 rctx->context.destroy = r600_destroy_context; 218 rctx->context.flush = r600_flush_from_st; 219 220 /* Easy accessing of screen/winsys. */ 221 rctx->screen = rscreen; 222 rctx->ws = rscreen->ws; 223 rctx->family = rscreen->family; 224 rctx->chip_class = rscreen->chip_class; 225 226 r600_init_blit_functions(rctx); 227 r600_init_query_functions(rctx); 228 r600_init_context_resource_functions(rctx); 229 r600_init_surface_functions(rctx); 230 rctx->context.draw_vbo = r600_draw_vbo; 231 232 rctx->context.create_video_decoder = vl_create_decoder; 233 rctx->context.create_video_buffer = vl_video_buffer_create; 234 235 switch (rctx->chip_class) { 236 case R600: 237 case R700: 238 r600_init_state_functions(rctx); 239 if (r600_context_init(&rctx->ctx, rctx->screen)) { 240 r600_destroy_context(&rctx->context); 241 return NULL; 242 } 243 r600_init_config(rctx); 244 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 245 break; 246 case EVERGREEN: 247 case CAYMAN: 248 evergreen_init_state_functions(rctx); 249 if (evergreen_context_init(&rctx->ctx, rctx->screen)) { 250 r600_destroy_context(&rctx->context); 251 return NULL; 252 } 253 evergreen_init_config(rctx); 254 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 255 break; 256 default: 257 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); 258 r600_destroy_context(&rctx->context); 259 return NULL; 260 } 261 262 rctx->ctx.pipe = &rctx->context; 263 rctx->ctx.flush = r600_flush_from_winsys; 264 rctx->ws->cs_set_flush_callback(rctx->ctx.cs, r600_flush_from_winsys, rctx); 265 266 util_slab_create(&rctx->pool_transfers, 267 sizeof(struct pipe_transfer), 64, 268 UTIL_SLAB_SINGLETHREADED); 269 270 rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256, 271 PIPE_BIND_VERTEX_BUFFER | 272 PIPE_BIND_INDEX_BUFFER | 273 PIPE_BIND_CONSTANT_BUFFER, 274 U_VERTEX_FETCH_DWORD_ALIGNED); 275 if (!rctx->vbuf_mgr) { 276 r600_destroy_context(&rctx->context); 277 return NULL; 278 } 279 rctx->vbuf_mgr->caps.format_fixed32 = 0; 280 281 rctx->blitter = util_blitter_create(&rctx->context); 282 if (rctx->blitter == NULL) { 283 r600_destroy_context(&rctx->context); 284 return NULL; 285 } 286 287 r600_get_backend_mask(&rctx->ctx); /* this emits commands and must be last */ 288 289 return &rctx->context; 290} 291 292/* 293 * pipe_screen 294 */ 295static const char* r600_get_vendor(struct pipe_screen* pscreen) 296{ 297 return "X.Org"; 298} 299 300static const char *r600_get_family_name(enum radeon_family family) 301{ 302 switch(family) { 303 case CHIP_R600: return "AMD R600"; 304 case CHIP_RV610: return "AMD RV610"; 305 case CHIP_RV630: return "AMD RV630"; 306 case CHIP_RV670: return "AMD RV670"; 307 case CHIP_RV620: return "AMD RV620"; 308 case CHIP_RV635: return "AMD RV635"; 309 case CHIP_RS780: return "AMD RS780"; 310 case CHIP_RS880: return "AMD RS880"; 311 case CHIP_RV770: return "AMD RV770"; 312 case CHIP_RV730: return "AMD RV730"; 313 case CHIP_RV710: return "AMD RV710"; 314 case CHIP_RV740: return "AMD RV740"; 315 case CHIP_CEDAR: return "AMD CEDAR"; 316 case CHIP_REDWOOD: return "AMD REDWOOD"; 317 case CHIP_JUNIPER: return "AMD JUNIPER"; 318 case CHIP_CYPRESS: return "AMD CYPRESS"; 319 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 320 case CHIP_PALM: return "AMD PALM"; 321 case CHIP_SUMO: return "AMD SUMO"; 322 case CHIP_SUMO2: return "AMD SUMO2"; 323 case CHIP_BARTS: return "AMD BARTS"; 324 case CHIP_TURKS: return "AMD TURKS"; 325 case CHIP_CAICOS: return "AMD CAICOS"; 326 case CHIP_CAYMAN: return "AMD CAYMAN"; 327 default: return "AMD unknown"; 328 } 329} 330 331static const char* r600_get_name(struct pipe_screen* pscreen) 332{ 333 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 334 335 return r600_get_family_name(rscreen->family); 336} 337 338static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 339{ 340 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 341 enum radeon_family family = rscreen->family; 342 343 switch (param) { 344 /* Supported features (boolean caps). */ 345 case PIPE_CAP_NPOT_TEXTURES: 346 case PIPE_CAP_TWO_SIDED_STENCIL: 347 case PIPE_CAP_DUAL_SOURCE_BLEND: 348 case PIPE_CAP_ANISOTROPIC_FILTER: 349 case PIPE_CAP_POINT_SPRITE: 350 case PIPE_CAP_OCCLUSION_QUERY: 351 case PIPE_CAP_TEXTURE_SHADOW_MAP: 352 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 353 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 354 case PIPE_CAP_TEXTURE_SWIZZLE: 355 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 356 case PIPE_CAP_DEPTH_CLIP_DISABLE: 357 case PIPE_CAP_SHADER_STENCIL_EXPORT: 358 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 359 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 360 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 361 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 362 case PIPE_CAP_SM3: 363 case PIPE_CAP_SEAMLESS_CUBE_MAP: 364 case PIPE_CAP_PRIMITIVE_RESTART: 365 case PIPE_CAP_CONDITIONAL_RENDER: 366 case PIPE_CAP_TEXTURE_BARRIER: 367 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 368 return 1; 369 370 /* Supported except the original R600. */ 371 case PIPE_CAP_INDEP_BLEND_ENABLE: 372 case PIPE_CAP_INDEP_BLEND_FUNC: 373 /* R600 doesn't support per-MRT blends */ 374 return family == CHIP_R600 ? 0 : 1; 375 376 /* Supported on Evergreen. */ 377 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 378 return family >= CHIP_CEDAR ? 1 : 0; 379 380 /* Unsupported features. */ 381 case PIPE_CAP_TGSI_INSTANCEID: 382 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 383 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 384 case PIPE_CAP_SCALED_RESOLVE: 385 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 386 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 387 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 388 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 389 return 0; 390 391 /* Stream output. */ 392 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 393 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0; 394 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 395 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0; 396 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 397 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 398 return 16*4; 399 400 /* Texturing. */ 401 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 402 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 403 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 404 if (family >= CHIP_CEDAR) 405 return 15; 406 else 407 return 14; 408 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 409 return rscreen->info.drm_minor >= 9 ? 410 (family >= CHIP_CEDAR ? 16384 : 8192) : 0; 411 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 412 return 32; 413 414 /* Render targets. */ 415 case PIPE_CAP_MAX_RENDER_TARGETS: 416 /* FIXME some r6xx are buggy and can only do 4 */ 417 return 8; 418 419 /* Timer queries, present when the clock frequency is non zero. */ 420 case PIPE_CAP_TIMER_QUERY: 421 return rscreen->info.r600_clock_crystal_freq != 0; 422 423 case PIPE_CAP_MIN_TEXEL_OFFSET: 424 return -8; 425 426 case PIPE_CAP_MAX_TEXEL_OFFSET: 427 return 7; 428 } 429 return 0; 430} 431 432static float r600_get_paramf(struct pipe_screen* pscreen, 433 enum pipe_capf param) 434{ 435 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 436 enum radeon_family family = rscreen->family; 437 438 switch (param) { 439 case PIPE_CAPF_MAX_LINE_WIDTH: 440 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 441 case PIPE_CAPF_MAX_POINT_WIDTH: 442 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 443 if (family >= CHIP_CEDAR) 444 return 16384.0f; 445 else 446 return 8192.0f; 447 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 448 return 16.0f; 449 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 450 return 16.0f; 451 case PIPE_CAPF_GUARD_BAND_LEFT: 452 case PIPE_CAPF_GUARD_BAND_TOP: 453 case PIPE_CAPF_GUARD_BAND_RIGHT: 454 case PIPE_CAPF_GUARD_BAND_BOTTOM: 455 return 0.0f; 456 } 457 return 0.0f; 458} 459 460static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 461{ 462 switch(shader) 463 { 464 case PIPE_SHADER_FRAGMENT: 465 case PIPE_SHADER_VERTEX: 466 break; 467 case PIPE_SHADER_GEOMETRY: 468 /* TODO: support and enable geometry programs */ 469 return 0; 470 default: 471 /* TODO: support tessellation on Evergreen */ 472 return 0; 473 } 474 475 /* TODO: all these should be fixed, since r600 surely supports much more! */ 476 switch (param) { 477 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 478 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 479 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 480 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 481 return 16384; 482 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 483 return 8; /* FIXME */ 484 case PIPE_SHADER_CAP_MAX_INPUTS: 485 if(shader == PIPE_SHADER_FRAGMENT) 486 return 34; 487 else 488 return 32; 489 case PIPE_SHADER_CAP_MAX_TEMPS: 490 return 256; /* Max native temporaries. */ 491 case PIPE_SHADER_CAP_MAX_ADDRS: 492 /* FIXME Isn't this equal to TEMPS? */ 493 return 1; /* Max native address registers */ 494 case PIPE_SHADER_CAP_MAX_CONSTS: 495 return R600_MAX_CONST_BUFFER_SIZE; 496 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 497 return R600_MAX_CONST_BUFFERS-1; 498 case PIPE_SHADER_CAP_MAX_PREDS: 499 return 0; /* FIXME */ 500 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 501 return 1; 502 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 503 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 504 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 505 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 506 return 1; 507 case PIPE_SHADER_CAP_SUBROUTINES: 508 return 0; 509 case PIPE_SHADER_CAP_INTEGERS: 510 return 0; 511 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 512 return 16; 513 case PIPE_SHADER_CAP_OUTPUT_READ: 514 return 1; 515 } 516 return 0; 517} 518 519static int r600_get_video_param(struct pipe_screen *screen, 520 enum pipe_video_profile profile, 521 enum pipe_video_cap param) 522{ 523 switch (param) { 524 case PIPE_VIDEO_CAP_SUPPORTED: 525 return vl_profile_supported(screen, profile); 526 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 527 return 1; 528 case PIPE_VIDEO_CAP_MAX_WIDTH: 529 case PIPE_VIDEO_CAP_MAX_HEIGHT: 530 return vl_video_buffer_max_size(screen); 531 case PIPE_VIDEO_CAP_PREFERED_FORMAT: 532 return PIPE_FORMAT_NV12; 533 default: 534 return 0; 535 } 536} 537 538static void r600_destroy_screen(struct pipe_screen* pscreen) 539{ 540 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 541 542 if (rscreen == NULL) 543 return; 544 545 if (rscreen->fences.bo) { 546 struct r600_fence_block *entry, *tmp; 547 548 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) { 549 LIST_DEL(&entry->head); 550 FREE(entry); 551 } 552 553 rscreen->ws->buffer_unmap(rscreen->fences.bo->buf); 554 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL); 555 } 556 pipe_mutex_destroy(rscreen->fences.mutex); 557 558 rscreen->ws->destroy(rscreen->ws); 559 560 util_slab_destroy(&rscreen->pool_buffers); 561 pipe_mutex_destroy(rscreen->mutex_num_contexts); 562 FREE(rscreen); 563} 564 565static void r600_fence_reference(struct pipe_screen *pscreen, 566 struct pipe_fence_handle **ptr, 567 struct pipe_fence_handle *fence) 568{ 569 struct r600_fence **oldf = (struct r600_fence**)ptr; 570 struct r600_fence *newf = (struct r600_fence*)fence; 571 572 if (pipe_reference(&(*oldf)->reference, &newf->reference)) { 573 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 574 pipe_mutex_lock(rscreen->fences.mutex); 575 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool); 576 pipe_mutex_unlock(rscreen->fences.mutex); 577 } 578 579 *ptr = fence; 580} 581 582static boolean r600_fence_signalled(struct pipe_screen *pscreen, 583 struct pipe_fence_handle *fence) 584{ 585 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 586 struct r600_fence *rfence = (struct r600_fence*)fence; 587 588 return rscreen->fences.data[rfence->index]; 589} 590 591static boolean r600_fence_finish(struct pipe_screen *pscreen, 592 struct pipe_fence_handle *fence, 593 uint64_t timeout) 594{ 595 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 596 struct r600_fence *rfence = (struct r600_fence*)fence; 597 int64_t start_time = 0; 598 unsigned spins = 0; 599 600 if (timeout != PIPE_TIMEOUT_INFINITE) { 601 start_time = os_time_get(); 602 603 /* Convert to microseconds. */ 604 timeout /= 1000; 605 } 606 607 while (rscreen->fences.data[rfence->index] == 0) { 608 if (++spins % 256) 609 continue; 610#ifdef PIPE_OS_UNIX 611 sched_yield(); 612#else 613 os_time_sleep(10); 614#endif 615 if (timeout != PIPE_TIMEOUT_INFINITE && 616 os_time_get() - start_time >= timeout) { 617 return FALSE; 618 } 619 } 620 621 return TRUE; 622} 623 624static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 625{ 626 switch ((tiling_config & 0xe) >> 1) { 627 case 0: 628 rscreen->tiling_info.num_channels = 1; 629 break; 630 case 1: 631 rscreen->tiling_info.num_channels = 2; 632 break; 633 case 2: 634 rscreen->tiling_info.num_channels = 4; 635 break; 636 case 3: 637 rscreen->tiling_info.num_channels = 8; 638 break; 639 default: 640 return -EINVAL; 641 } 642 643 switch ((tiling_config & 0x30) >> 4) { 644 case 0: 645 rscreen->tiling_info.num_banks = 4; 646 break; 647 case 1: 648 rscreen->tiling_info.num_banks = 8; 649 break; 650 default: 651 return -EINVAL; 652 653 } 654 switch ((tiling_config & 0xc0) >> 6) { 655 case 0: 656 rscreen->tiling_info.group_bytes = 256; 657 break; 658 case 1: 659 rscreen->tiling_info.group_bytes = 512; 660 break; 661 default: 662 return -EINVAL; 663 } 664 return 0; 665} 666 667static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 668{ 669 switch (tiling_config & 0xf) { 670 case 0: 671 rscreen->tiling_info.num_channels = 1; 672 break; 673 case 1: 674 rscreen->tiling_info.num_channels = 2; 675 break; 676 case 2: 677 rscreen->tiling_info.num_channels = 4; 678 break; 679 case 3: 680 rscreen->tiling_info.num_channels = 8; 681 break; 682 default: 683 return -EINVAL; 684 } 685 686 switch ((tiling_config & 0xf0) >> 4) { 687 case 0: 688 rscreen->tiling_info.num_banks = 4; 689 break; 690 case 1: 691 rscreen->tiling_info.num_banks = 8; 692 break; 693 case 2: 694 rscreen->tiling_info.num_banks = 16; 695 break; 696 default: 697 return -EINVAL; 698 } 699 700 switch ((tiling_config & 0xf00) >> 8) { 701 case 0: 702 rscreen->tiling_info.group_bytes = 256; 703 break; 704 case 1: 705 rscreen->tiling_info.group_bytes = 512; 706 break; 707 default: 708 return -EINVAL; 709 } 710 return 0; 711} 712 713static int r600_init_tiling(struct r600_screen *rscreen) 714{ 715 uint32_t tiling_config = rscreen->info.r600_tiling_config; 716 717 /* set default group bytes, overridden by tiling info ioctl */ 718 if (rscreen->chip_class <= R700) { 719 rscreen->tiling_info.group_bytes = 256; 720 } else { 721 rscreen->tiling_info.group_bytes = 512; 722 } 723 724 if (!tiling_config) 725 return 0; 726 727 if (rscreen->chip_class <= R700) { 728 return r600_interpret_tiling(rscreen, tiling_config); 729 } else { 730 return evergreen_interpret_tiling(rscreen, tiling_config); 731 } 732} 733 734static unsigned radeon_family_from_device(unsigned device) 735{ 736 switch (device) { 737#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family; 738#include "pci_ids/r600_pci_ids.h" 739#undef CHIPSET 740 default: 741 return CHIP_UNKNOWN; 742 } 743} 744 745struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) 746{ 747 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen); 748 if (rscreen == NULL) { 749 return NULL; 750 } 751 752 rscreen->ws = ws; 753 ws->query_info(ws, &rscreen->info); 754 755 rscreen->family = radeon_family_from_device(rscreen->info.pci_id); 756 if (rscreen->family == CHIP_UNKNOWN) { 757 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); 758 FREE(rscreen); 759 return NULL; 760 } 761 762 /* setup class */ 763 if (rscreen->family == CHIP_CAYMAN) { 764 rscreen->chip_class = CAYMAN; 765 } else if (rscreen->family >= CHIP_CEDAR) { 766 rscreen->chip_class = EVERGREEN; 767 } else if (rscreen->family >= CHIP_RV770) { 768 rscreen->chip_class = R700; 769 } else { 770 rscreen->chip_class = R600; 771 } 772 773 if (r600_init_tiling(rscreen)) { 774 FREE(rscreen); 775 return NULL; 776 } 777 778 rscreen->screen.winsys = (struct pipe_winsys*)ws; 779 rscreen->screen.destroy = r600_destroy_screen; 780 rscreen->screen.get_name = r600_get_name; 781 rscreen->screen.get_vendor = r600_get_vendor; 782 rscreen->screen.get_param = r600_get_param; 783 rscreen->screen.get_shader_param = r600_get_shader_param; 784 rscreen->screen.get_paramf = r600_get_paramf; 785 rscreen->screen.get_video_param = r600_get_video_param; 786 if (rscreen->chip_class >= EVERGREEN) { 787 rscreen->screen.is_format_supported = evergreen_is_format_supported; 788 } else { 789 rscreen->screen.is_format_supported = r600_is_format_supported; 790 } 791 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; 792 rscreen->screen.context_create = r600_create_context; 793 rscreen->screen.fence_reference = r600_fence_reference; 794 rscreen->screen.fence_signalled = r600_fence_signalled; 795 rscreen->screen.fence_finish = r600_fence_finish; 796 r600_init_screen_resource_functions(&rscreen->screen); 797 798 util_format_s3tc_init(); 799 800 util_slab_create(&rscreen->pool_buffers, 801 sizeof(struct r600_resource), 64, 802 UTIL_SLAB_SINGLETHREADED); 803 804 pipe_mutex_init(rscreen->mutex_num_contexts); 805 806 rscreen->fences.bo = NULL; 807 rscreen->fences.data = NULL; 808 rscreen->fences.next_index = 0; 809 LIST_INITHEAD(&rscreen->fences.pool); 810 LIST_INITHEAD(&rscreen->fences.blocks); 811 pipe_mutex_init(rscreen->fences.mutex); 812 813 return &rscreen->screen; 814} 815