r600_pipe.c revision 1e5cef96d184b00eb588b48ecd02386998077d82
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include <stdio.h> 24#include <errno.h> 25#include <pipe/p_defines.h> 26#include <pipe/p_state.h> 27#include <pipe/p_context.h> 28#include <tgsi/tgsi_scan.h> 29#include <tgsi/tgsi_parse.h> 30#include <tgsi/tgsi_util.h> 31#include <util/u_blitter.h> 32#include <util/u_double_list.h> 33#include "util/u_format.h" 34#include <util/u_format_s3tc.h> 35#include <util/u_transfer.h> 36#include <util/u_surface.h> 37#include <util/u_pack_color.h> 38#include <util/u_memory.h> 39#include <util/u_inlines.h> 40#include "util/u_upload_mgr.h" 41#include "os/os_time.h" 42#include <pipebuffer/pb_buffer.h> 43#include "r600.h" 44#include "r600d.h" 45#include "r600_resource.h" 46#include "r600_shader.h" 47#include "r600_pipe.h" 48#include "r600_state_inlines.h" 49 50/* 51 * pipe_context 52 */ 53static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx) 54{ 55 struct r600_fence *fence = NULL; 56 57 if (!ctx->fences.bo) { 58 /* Create the shared buffer object */ 59 ctx->fences.bo = r600_bo(ctx->radeon, 4096, 0, 0, 0); 60 if (!ctx->fences.bo) { 61 R600_ERR("r600: failed to create bo for fence objects\n"); 62 return NULL; 63 } 64 ctx->fences.data = r600_bo_map(ctx->radeon, ctx->fences.bo, PB_USAGE_UNSYNCHRONIZED, NULL); 65 } 66 67 if (!LIST_IS_EMPTY(&ctx->fences.pool)) { 68 struct r600_fence *entry; 69 70 /* Try to find a freed fence that has been signalled */ 71 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) { 72 if (ctx->fences.data[entry->index] != 0) { 73 LIST_DELINIT(&entry->head); 74 fence = entry; 75 break; 76 } 77 } 78 } 79 80 if (!fence) { 81 /* Allocate a new fence */ 82 struct r600_fence_block *block; 83 unsigned index; 84 85 if ((ctx->fences.next_index + 1) >= 1024) { 86 R600_ERR("r600: too many concurrent fences\n"); 87 return NULL; 88 } 89 90 index = ctx->fences.next_index++; 91 92 if (!(index % FENCE_BLOCK_SIZE)) { 93 /* Allocate a new block */ 94 block = CALLOC_STRUCT(r600_fence_block); 95 if (block == NULL) 96 return NULL; 97 98 LIST_ADD(&block->head, &ctx->fences.blocks); 99 } else { 100 block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head); 101 } 102 103 fence = &block->fences[index % FENCE_BLOCK_SIZE]; 104 fence->ctx = ctx; 105 fence->index = index; 106 } 107 108 pipe_reference_init(&fence->reference, 1); 109 110 ctx->fences.data[fence->index] = 0; 111 r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1); 112 return fence; 113} 114 115static void r600_flush(struct pipe_context *ctx, 116 struct pipe_fence_handle **fence) 117{ 118 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 119 struct r600_fence **rfence = (struct r600_fence**)fence; 120 121#if 0 122 static int dc = 0; 123 char dname[256]; 124#endif 125 126 if (rfence) 127 *rfence = r600_create_fence(rctx); 128 129 if (!rctx->ctx.pm4_cdwords) 130 return; 131 132#if 0 133 sprintf(dname, "gallium-%08d.bof", dc); 134 if (dc < 20) { 135 r600_context_dump_bof(&rctx->ctx, dname); 136 R600_ERR("dumped %s\n", dname); 137 } 138 dc++; 139#endif 140 r600_context_flush(&rctx->ctx); 141} 142 143static void r600_update_num_contexts(struct r600_screen *rscreen, int diff) 144{ 145 pipe_mutex_lock(rscreen->mutex_num_contexts); 146 if (diff > 0) { 147 rscreen->num_contexts++; 148 149 if (rscreen->num_contexts > 1) 150 util_slab_set_thread_safety(&rscreen->pool_buffers, 151 UTIL_SLAB_MULTITHREADED); 152 } else { 153 rscreen->num_contexts--; 154 155 if (rscreen->num_contexts <= 1) 156 util_slab_set_thread_safety(&rscreen->pool_buffers, 157 UTIL_SLAB_SINGLETHREADED); 158 } 159 pipe_mutex_unlock(rscreen->mutex_num_contexts); 160} 161 162static void r600_destroy_context(struct pipe_context *context) 163{ 164 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context; 165 166 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 167 util_unreference_framebuffer_state(&rctx->framebuffer); 168 169 r600_context_fini(&rctx->ctx); 170 171 util_blitter_destroy(rctx->blitter); 172 173 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 174 free(rctx->states[i]); 175 } 176 177 u_vbuf_mgr_destroy(rctx->vbuf_mgr); 178 util_slab_destroy(&rctx->pool_transfers); 179 180 if (rctx->fences.bo) { 181 struct r600_fence_block *entry, *tmp; 182 183 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) { 184 LIST_DEL(&entry->head); 185 FREE(entry); 186 } 187 188 r600_bo_unmap(rctx->radeon, rctx->fences.bo); 189 r600_bo_reference(rctx->radeon, &rctx->fences.bo, NULL); 190 } 191 192 r600_update_num_contexts(rctx->screen, -1); 193 194 FREE(rctx); 195} 196 197static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 198{ 199 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context); 200 struct r600_screen* rscreen = (struct r600_screen *)screen; 201 enum chip_class class; 202 203 if (rctx == NULL) 204 return NULL; 205 206 r600_update_num_contexts(rscreen, 1); 207 208 rctx->context.winsys = rscreen->screen.winsys; 209 rctx->context.screen = screen; 210 rctx->context.priv = priv; 211 rctx->context.destroy = r600_destroy_context; 212 rctx->context.flush = r600_flush; 213 214 /* Easy accessing of screen/winsys. */ 215 rctx->screen = rscreen; 216 rctx->radeon = rscreen->radeon; 217 rctx->family = r600_get_family(rctx->radeon); 218 219 rctx->fences.bo = NULL; 220 rctx->fences.data = NULL; 221 rctx->fences.next_index = 0; 222 LIST_INITHEAD(&rctx->fences.pool); 223 LIST_INITHEAD(&rctx->fences.blocks); 224 225 r600_init_blit_functions(rctx); 226 r600_init_query_functions(rctx); 227 r600_init_context_resource_functions(rctx); 228 r600_init_surface_functions(rctx); 229 rctx->context.draw_vbo = r600_draw_vbo; 230 231 switch (r600_get_family(rctx->radeon)) { 232 case CHIP_R600: 233 case CHIP_RV610: 234 case CHIP_RV630: 235 case CHIP_RV670: 236 case CHIP_RV620: 237 case CHIP_RV635: 238 case CHIP_RS780: 239 case CHIP_RS880: 240 case CHIP_RV770: 241 case CHIP_RV730: 242 case CHIP_RV710: 243 case CHIP_RV740: 244 r600_init_state_functions(rctx); 245 if (r600_context_init(&rctx->ctx, rctx->radeon)) { 246 r600_destroy_context(&rctx->context); 247 return NULL; 248 } 249 r600_init_config(rctx); 250 break; 251 case CHIP_CEDAR: 252 case CHIP_REDWOOD: 253 case CHIP_JUNIPER: 254 case CHIP_CYPRESS: 255 case CHIP_HEMLOCK: 256 case CHIP_PALM: 257 case CHIP_SUMO: 258 case CHIP_SUMO2: 259 case CHIP_BARTS: 260 case CHIP_TURKS: 261 case CHIP_CAICOS: 262 case CHIP_CAYMAN: 263 evergreen_init_state_functions(rctx); 264 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) { 265 r600_destroy_context(&rctx->context); 266 return NULL; 267 } 268 evergreen_init_config(rctx); 269 break; 270 default: 271 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon)); 272 r600_destroy_context(&rctx->context); 273 return NULL; 274 } 275 276 util_slab_create(&rctx->pool_transfers, 277 sizeof(struct pipe_transfer), 64, 278 UTIL_SLAB_SINGLETHREADED); 279 280 rctx->vbuf_mgr = u_vbuf_mgr_create(&rctx->context, 1024 * 1024, 256, 281 PIPE_BIND_VERTEX_BUFFER | 282 PIPE_BIND_INDEX_BUFFER | 283 PIPE_BIND_CONSTANT_BUFFER, 284 U_VERTEX_FETCH_DWORD_ALIGNED); 285 if (!rctx->vbuf_mgr) { 286 r600_destroy_context(&rctx->context); 287 return NULL; 288 } 289 290 rctx->blitter = util_blitter_create(&rctx->context); 291 if (rctx->blitter == NULL) { 292 r600_destroy_context(&rctx->context); 293 return NULL; 294 } 295 296 class = r600_get_family_class(rctx->radeon); 297 if (class == R600 || class == R700) 298 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 299 else 300 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 301 302 return &rctx->context; 303} 304 305/* 306 * pipe_screen 307 */ 308static const char* r600_get_vendor(struct pipe_screen* pscreen) 309{ 310 return "X.Org"; 311} 312 313static const char *r600_get_family_name(enum radeon_family family) 314{ 315 switch(family) { 316 case CHIP_R600: return "AMD R600"; 317 case CHIP_RV610: return "AMD RV610"; 318 case CHIP_RV630: return "AMD RV630"; 319 case CHIP_RV670: return "AMD RV670"; 320 case CHIP_RV620: return "AMD RV620"; 321 case CHIP_RV635: return "AMD RV635"; 322 case CHIP_RS780: return "AMD RS780"; 323 case CHIP_RS880: return "AMD RS880"; 324 case CHIP_RV770: return "AMD RV770"; 325 case CHIP_RV730: return "AMD RV730"; 326 case CHIP_RV710: return "AMD RV710"; 327 case CHIP_RV740: return "AMD RV740"; 328 case CHIP_CEDAR: return "AMD CEDAR"; 329 case CHIP_REDWOOD: return "AMD REDWOOD"; 330 case CHIP_JUNIPER: return "AMD JUNIPER"; 331 case CHIP_CYPRESS: return "AMD CYPRESS"; 332 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 333 case CHIP_PALM: return "AMD PALM"; 334 case CHIP_SUMO: return "AMD SUMO"; 335 case CHIP_SUMO2: return "AMD SUMO2"; 336 case CHIP_BARTS: return "AMD BARTS"; 337 case CHIP_TURKS: return "AMD TURKS"; 338 case CHIP_CAICOS: return "AMD CAICOS"; 339 case CHIP_CAYMAN: return "AMD CAYMAN"; 340 default: return "AMD unknown"; 341 } 342} 343 344static const char* r600_get_name(struct pipe_screen* pscreen) 345{ 346 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 347 enum radeon_family family = r600_get_family(rscreen->radeon); 348 349 return r600_get_family_name(family); 350} 351 352static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 353{ 354 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 355 enum radeon_family family = r600_get_family(rscreen->radeon); 356 357 switch (param) { 358 /* Supported features (boolean caps). */ 359 case PIPE_CAP_NPOT_TEXTURES: 360 case PIPE_CAP_TWO_SIDED_STENCIL: 361 case PIPE_CAP_GLSL: 362 case PIPE_CAP_DUAL_SOURCE_BLEND: 363 case PIPE_CAP_ANISOTROPIC_FILTER: 364 case PIPE_CAP_POINT_SPRITE: 365 case PIPE_CAP_OCCLUSION_QUERY: 366 case PIPE_CAP_TEXTURE_SHADOW_MAP: 367 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 368 case PIPE_CAP_TEXTURE_MIRROR_REPEAT: 369 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 370 case PIPE_CAP_TEXTURE_SWIZZLE: 371 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 372 case PIPE_CAP_DEPTH_CLAMP: 373 case PIPE_CAP_SHADER_STENCIL_EXPORT: 374 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 375 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 376 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 377 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 378 case PIPE_CAP_SM3: 379 case PIPE_CAP_SEAMLESS_CUBE_MAP: 380 return 1; 381 382 /* Supported except the original R600. */ 383 case PIPE_CAP_INDEP_BLEND_ENABLE: 384 case PIPE_CAP_INDEP_BLEND_FUNC: 385 /* R600 doesn't support per-MRT blends */ 386 return family == CHIP_R600 ? 0 : 1; 387 388 /* Supported on Evergreen. */ 389 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 390 return family >= CHIP_CEDAR ? 1 : 0; 391 392 /* Unsupported features. */ 393 case PIPE_CAP_STREAM_OUTPUT: 394 case PIPE_CAP_PRIMITIVE_RESTART: 395 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL: 396 case PIPE_CAP_TGSI_INSTANCEID: 397 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 398 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 399 return 0; 400 401 case PIPE_CAP_ARRAY_TEXTURES: 402 /* fix once the CS checker upstream is fixed */ 403 return debug_get_bool_option("R600_ARRAY_TEXTURE", FALSE); 404 405 /* Texturing. */ 406 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 407 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 408 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 409 if (family >= CHIP_CEDAR) 410 return 15; 411 else 412 return 14; 413 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS: 414 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS: 415 return 16; 416 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 417 return 32; 418 419 /* Render targets. */ 420 case PIPE_CAP_MAX_RENDER_TARGETS: 421 /* FIXME some r6xx are buggy and can only do 4 */ 422 return 8; 423 424 /* Timer queries, present when the clock frequency is non zero. */ 425 case PIPE_CAP_TIMER_QUERY: 426 return r600_get_clock_crystal_freq(rscreen->radeon) != 0; 427 428 default: 429 R600_ERR("r600: unknown param %d\n", param); 430 return 0; 431 } 432} 433 434static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param) 435{ 436 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 437 enum radeon_family family = r600_get_family(rscreen->radeon); 438 439 switch (param) { 440 case PIPE_CAP_MAX_LINE_WIDTH: 441 case PIPE_CAP_MAX_LINE_WIDTH_AA: 442 case PIPE_CAP_MAX_POINT_WIDTH: 443 case PIPE_CAP_MAX_POINT_WIDTH_AA: 444 if (family >= CHIP_CEDAR) 445 return 16384.0f; 446 else 447 return 8192.0f; 448 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: 449 return 16.0f; 450 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: 451 return 16.0f; 452 default: 453 R600_ERR("r600: unsupported paramf %d\n", param); 454 return 0.0f; 455 } 456} 457 458static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 459{ 460 switch(shader) 461 { 462 case PIPE_SHADER_FRAGMENT: 463 case PIPE_SHADER_VERTEX: 464 break; 465 case PIPE_SHADER_GEOMETRY: 466 /* TODO: support and enable geometry programs */ 467 return 0; 468 default: 469 /* TODO: support tessellation on Evergreen */ 470 return 0; 471 } 472 473 /* TODO: all these should be fixed, since r600 surely supports much more! */ 474 switch (param) { 475 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 476 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 477 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 478 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 479 return 16384; 480 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 481 return 8; /* FIXME */ 482 case PIPE_SHADER_CAP_MAX_INPUTS: 483 if(shader == PIPE_SHADER_FRAGMENT) 484 return 34; 485 else 486 return 32; 487 case PIPE_SHADER_CAP_MAX_TEMPS: 488 return 256; /* Max native temporaries. */ 489 case PIPE_SHADER_CAP_MAX_ADDRS: 490 /* FIXME Isn't this equal to TEMPS? */ 491 return 1; /* Max native address registers */ 492 case PIPE_SHADER_CAP_MAX_CONSTS: 493 return R600_MAX_CONST_BUFFER_SIZE; 494 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 495 return R600_MAX_CONST_BUFFERS; 496 case PIPE_SHADER_CAP_MAX_PREDS: 497 return 0; /* FIXME */ 498 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 499 return 1; 500 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 501 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 502 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 503 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 504 return 1; 505 case PIPE_SHADER_CAP_SUBROUTINES: 506 return 0; 507 default: 508 return 0; 509 } 510} 511 512static boolean r600_is_format_supported(struct pipe_screen* screen, 513 enum pipe_format format, 514 enum pipe_texture_target target, 515 unsigned sample_count, 516 unsigned usage) 517{ 518 unsigned retval = 0; 519 if (target >= PIPE_MAX_TEXTURE_TYPES) { 520 R600_ERR("r600: unsupported texture type %d\n", target); 521 return FALSE; 522 } 523 524 if (!util_format_is_supported(format, usage)) 525 return FALSE; 526 527 /* Multisample */ 528 if (sample_count > 1) 529 return FALSE; 530 531 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 532 r600_is_sampler_format_supported(screen, format)) { 533 retval |= PIPE_BIND_SAMPLER_VIEW; 534 } 535 536 if ((usage & (PIPE_BIND_RENDER_TARGET | 537 PIPE_BIND_DISPLAY_TARGET | 538 PIPE_BIND_SCANOUT | 539 PIPE_BIND_SHARED)) && 540 r600_is_colorbuffer_format_supported(format)) { 541 retval |= usage & 542 (PIPE_BIND_RENDER_TARGET | 543 PIPE_BIND_DISPLAY_TARGET | 544 PIPE_BIND_SCANOUT | 545 PIPE_BIND_SHARED); 546 } 547 548 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 549 r600_is_zs_format_supported(format)) { 550 retval |= PIPE_BIND_DEPTH_STENCIL; 551 } 552 553 if (usage & PIPE_BIND_VERTEX_BUFFER) { 554 struct r600_screen *rscreen = (struct r600_screen *)screen; 555 enum radeon_family family = r600_get_family(rscreen->radeon); 556 557 if (r600_is_vertex_format_supported(format, family)) { 558 retval |= PIPE_BIND_VERTEX_BUFFER; 559 } 560 } 561 562 if (usage & PIPE_BIND_TRANSFER_READ) 563 retval |= PIPE_BIND_TRANSFER_READ; 564 if (usage & PIPE_BIND_TRANSFER_WRITE) 565 retval |= PIPE_BIND_TRANSFER_WRITE; 566 567 return retval == usage; 568} 569 570static void r600_destroy_screen(struct pipe_screen* pscreen) 571{ 572 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 573 574 if (rscreen == NULL) 575 return; 576 577 radeon_decref(rscreen->radeon); 578 579 util_slab_destroy(&rscreen->pool_buffers); 580 pipe_mutex_destroy(rscreen->mutex_num_contexts); 581 FREE(rscreen); 582} 583 584static void r600_fence_reference(struct pipe_screen *pscreen, 585 struct pipe_fence_handle **ptr, 586 struct pipe_fence_handle *fence) 587{ 588 struct r600_fence **oldf = (struct r600_fence**)ptr; 589 struct r600_fence *newf = (struct r600_fence*)fence; 590 591 if (pipe_reference(&(*oldf)->reference, &newf->reference)) { 592 struct r600_pipe_context *ctx = (*oldf)->ctx; 593 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool); 594 } 595 596 *ptr = fence; 597} 598 599static boolean r600_fence_signalled(struct pipe_screen *pscreen, 600 struct pipe_fence_handle *fence) 601{ 602 struct r600_fence *rfence = (struct r600_fence*)fence; 603 struct r600_pipe_context *ctx = rfence->ctx; 604 605 return ctx->fences.data[rfence->index]; 606} 607 608static boolean r600_fence_finish(struct pipe_screen *pscreen, 609 struct pipe_fence_handle *fence, 610 uint64_t timeout) 611{ 612 struct r600_fence *rfence = (struct r600_fence*)fence; 613 struct r600_pipe_context *ctx = rfence->ctx; 614 int64_t start_time = 0; 615 unsigned spins = 0; 616 617 if (timeout != PIPE_TIMEOUT_INFINITE) { 618 start_time = os_time_get(); 619 620 /* Convert to microseconds. */ 621 timeout /= 1000; 622 } 623 624 while (ctx->fences.data[rfence->index] == 0) { 625 if (++spins % 256) 626 continue; 627#ifdef PIPE_OS_UNIX 628 sched_yield(); 629#else 630 os_time_sleep(10); 631#endif 632 if (timeout != PIPE_TIMEOUT_INFINITE && 633 os_time_get() - start_time >= timeout) { 634 return FALSE; 635 } 636 } 637 638 return TRUE; 639} 640 641struct pipe_screen *r600_screen_create(struct radeon *radeon) 642{ 643 struct r600_screen *rscreen; 644 645 rscreen = CALLOC_STRUCT(r600_screen); 646 if (rscreen == NULL) { 647 return NULL; 648 } 649 650 rscreen->radeon = radeon; 651 rscreen->screen.winsys = (struct pipe_winsys*)radeon; 652 rscreen->screen.destroy = r600_destroy_screen; 653 rscreen->screen.get_name = r600_get_name; 654 rscreen->screen.get_vendor = r600_get_vendor; 655 rscreen->screen.get_param = r600_get_param; 656 rscreen->screen.get_shader_param = r600_get_shader_param; 657 rscreen->screen.get_paramf = r600_get_paramf; 658 rscreen->screen.is_format_supported = r600_is_format_supported; 659 rscreen->screen.context_create = r600_create_context; 660 rscreen->screen.fence_reference = r600_fence_reference; 661 rscreen->screen.fence_signalled = r600_fence_signalled; 662 rscreen->screen.fence_finish = r600_fence_finish; 663 r600_init_screen_resource_functions(&rscreen->screen); 664 665 rscreen->tiling_info = r600_get_tiling_info(radeon); 666 util_format_s3tc_init(); 667 668 util_slab_create(&rscreen->pool_buffers, 669 sizeof(struct r600_resource_buffer), 64, 670 UTIL_SLAB_SINGLETHREADED); 671 672 pipe_mutex_init(rscreen->mutex_num_contexts); 673 674 return &rscreen->screen; 675} 676