r600_pipe.c revision 2a0126932b320806e030c1c085791e257516e0cd
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include <stdio.h> 24#include <errno.h> 25#include "pipe/p_defines.h" 26#include "pipe/p_state.h" 27#include "pipe/p_context.h" 28#include "tgsi/tgsi_scan.h" 29#include "tgsi/tgsi_parse.h" 30#include "tgsi/tgsi_util.h" 31#include "util/u_blitter.h" 32#include "util/u_double_list.h" 33#include "util/u_format.h" 34#include "util/u_format_s3tc.h" 35#include "util/u_transfer.h" 36#include "util/u_surface.h" 37#include "util/u_pack_color.h" 38#include "util/u_memory.h" 39#include "util/u_inlines.h" 40#include "util/u_upload_mgr.h" 41#include "vl/vl_decoder.h" 42#include "vl/vl_video_buffer.h" 43#include "os/os_time.h" 44#include "pipebuffer/pb_buffer.h" 45#include "r600.h" 46#include "r600d.h" 47#include "r600_resource.h" 48#include "r600_shader.h" 49#include "r600_pipe.h" 50 51/* 52 * pipe_context 53 */ 54static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx) 55{ 56 struct r600_fence *fence = NULL; 57 58 if (!ctx->fences.bo) { 59 /* Create the shared buffer object */ 60 ctx->fences.bo = (struct r600_resource*) 61 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, 62 PIPE_USAGE_STAGING, 4096); 63 if (!ctx->fences.bo) { 64 R600_ERR("r600: failed to create bo for fence objects\n"); 65 return NULL; 66 } 67 ctx->fences.data = ctx->ws->buffer_map(ctx->fences.bo->buf, ctx->ctx.cs, 68 PIPE_TRANSFER_WRITE); 69 } 70 71 if (!LIST_IS_EMPTY(&ctx->fences.pool)) { 72 struct r600_fence *entry; 73 74 /* Try to find a freed fence that has been signalled */ 75 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) { 76 if (ctx->fences.data[entry->index] != 0) { 77 LIST_DELINIT(&entry->head); 78 fence = entry; 79 break; 80 } 81 } 82 } 83 84 if (!fence) { 85 /* Allocate a new fence */ 86 struct r600_fence_block *block; 87 unsigned index; 88 89 if ((ctx->fences.next_index + 1) >= 1024) { 90 R600_ERR("r600: too many concurrent fences\n"); 91 return NULL; 92 } 93 94 index = ctx->fences.next_index++; 95 96 if (!(index % FENCE_BLOCK_SIZE)) { 97 /* Allocate a new block */ 98 block = CALLOC_STRUCT(r600_fence_block); 99 if (block == NULL) 100 return NULL; 101 102 LIST_ADD(&block->head, &ctx->fences.blocks); 103 } else { 104 block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head); 105 } 106 107 fence = &block->fences[index % FENCE_BLOCK_SIZE]; 108 fence->ctx = ctx; 109 fence->index = index; 110 } 111 112 pipe_reference_init(&fence->reference, 1); 113 114 ctx->fences.data[fence->index] = 0; 115 r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1); 116 return fence; 117} 118 119 120void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 121 unsigned flags) 122{ 123 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 124 struct r600_fence **rfence = (struct r600_fence**)fence; 125 struct pipe_query *render_cond = NULL; 126 unsigned render_cond_mode = 0; 127 128 if (rfence) 129 *rfence = r600_create_fence(rctx); 130 131 /* Disable render condition. */ 132 if (rctx->current_render_cond) { 133 render_cond = rctx->current_render_cond; 134 render_cond_mode = rctx->current_render_cond_mode; 135 ctx->render_condition(ctx, NULL, 0); 136 } 137 138 r600_context_flush(&rctx->ctx, flags); 139 140 /* Re-enable render condition. */ 141 if (render_cond) { 142 ctx->render_condition(ctx, render_cond, render_cond_mode); 143 } 144} 145 146static void r600_flush_from_st(struct pipe_context *ctx, 147 struct pipe_fence_handle **fence) 148{ 149 r600_flush(ctx, fence, 0); 150} 151 152static void r600_flush_from_winsys(void *ctx, unsigned flags) 153{ 154 r600_flush((struct pipe_context*)ctx, NULL, flags); 155} 156 157static void r600_update_num_contexts(struct r600_screen *rscreen, int diff) 158{ 159 pipe_mutex_lock(rscreen->mutex_num_contexts); 160 if (diff > 0) { 161 rscreen->num_contexts++; 162 163 if (rscreen->num_contexts > 1) 164 util_slab_set_thread_safety(&rscreen->pool_buffers, 165 UTIL_SLAB_MULTITHREADED); 166 } else { 167 rscreen->num_contexts--; 168 169 if (rscreen->num_contexts <= 1) 170 util_slab_set_thread_safety(&rscreen->pool_buffers, 171 UTIL_SLAB_SINGLETHREADED); 172 } 173 pipe_mutex_unlock(rscreen->mutex_num_contexts); 174} 175 176static void r600_destroy_context(struct pipe_context *context) 177{ 178 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context; 179 180 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 181 util_unreference_framebuffer_state(&rctx->framebuffer); 182 183 r600_context_fini(&rctx->ctx); 184 185 util_blitter_destroy(rctx->blitter); 186 187 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 188 free(rctx->states[i]); 189 } 190 191 u_vbuf_destroy(rctx->vbuf_mgr); 192 util_slab_destroy(&rctx->pool_transfers); 193 194 if (rctx->fences.bo) { 195 struct r600_fence_block *entry, *tmp; 196 197 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) { 198 LIST_DEL(&entry->head); 199 FREE(entry); 200 } 201 202 rctx->ws->buffer_unmap(rctx->fences.bo->buf); 203 pipe_resource_reference((struct pipe_resource**)&rctx->fences.bo, NULL); 204 } 205 206 r600_update_num_contexts(rctx->screen, -1); 207 208 FREE(rctx); 209} 210 211static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 212{ 213 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context); 214 struct r600_screen* rscreen = (struct r600_screen *)screen; 215 216 if (rctx == NULL) 217 return NULL; 218 219 r600_update_num_contexts(rscreen, 1); 220 221 rctx->context.winsys = rscreen->screen.winsys; 222 rctx->context.screen = screen; 223 rctx->context.priv = priv; 224 rctx->context.destroy = r600_destroy_context; 225 rctx->context.flush = r600_flush_from_st; 226 227 /* Easy accessing of screen/winsys. */ 228 rctx->screen = rscreen; 229 rctx->ws = rscreen->ws; 230 rctx->family = rscreen->family; 231 rctx->chip_class = rscreen->chip_class; 232 233 rctx->fences.bo = NULL; 234 rctx->fences.data = NULL; 235 rctx->fences.next_index = 0; 236 LIST_INITHEAD(&rctx->fences.pool); 237 LIST_INITHEAD(&rctx->fences.blocks); 238 239 r600_init_blit_functions(rctx); 240 r600_init_query_functions(rctx); 241 r600_init_context_resource_functions(rctx); 242 r600_init_surface_functions(rctx); 243 rctx->context.draw_vbo = r600_draw_vbo; 244 245 rctx->context.create_video_decoder = vl_create_decoder; 246 rctx->context.create_video_buffer = vl_video_buffer_create; 247 248 switch (rctx->chip_class) { 249 case R600: 250 case R700: 251 r600_init_state_functions(rctx); 252 if (r600_context_init(&rctx->ctx, rctx->screen)) { 253 r600_destroy_context(&rctx->context); 254 return NULL; 255 } 256 r600_init_config(rctx); 257 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 258 break; 259 case EVERGREEN: 260 case CAYMAN: 261 evergreen_init_state_functions(rctx); 262 if (evergreen_context_init(&rctx->ctx, rctx->screen)) { 263 r600_destroy_context(&rctx->context); 264 return NULL; 265 } 266 evergreen_init_config(rctx); 267 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 268 break; 269 default: 270 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); 271 r600_destroy_context(&rctx->context); 272 return NULL; 273 } 274 275 rctx->ctx.pipe = &rctx->context; 276 rctx->ctx.flush = r600_flush_from_winsys; 277 rctx->ws->cs_set_flush_callback(rctx->ctx.cs, r600_flush_from_winsys, rctx); 278 279 util_slab_create(&rctx->pool_transfers, 280 sizeof(struct pipe_transfer), 64, 281 UTIL_SLAB_SINGLETHREADED); 282 283 rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256, 284 PIPE_BIND_VERTEX_BUFFER | 285 PIPE_BIND_INDEX_BUFFER | 286 PIPE_BIND_CONSTANT_BUFFER, 287 U_VERTEX_FETCH_DWORD_ALIGNED); 288 if (!rctx->vbuf_mgr) { 289 r600_destroy_context(&rctx->context); 290 return NULL; 291 } 292 rctx->vbuf_mgr->caps.format_fixed32 = 0; 293 294 rctx->blitter = util_blitter_create(&rctx->context); 295 if (rctx->blitter == NULL) { 296 r600_destroy_context(&rctx->context); 297 return NULL; 298 } 299 300 r600_get_backend_mask(&rctx->ctx); /* this emits commands and must be last */ 301 302 return &rctx->context; 303} 304 305/* 306 * pipe_screen 307 */ 308static const char* r600_get_vendor(struct pipe_screen* pscreen) 309{ 310 return "X.Org"; 311} 312 313static const char *r600_get_family_name(enum radeon_family family) 314{ 315 switch(family) { 316 case CHIP_R600: return "AMD R600"; 317 case CHIP_RV610: return "AMD RV610"; 318 case CHIP_RV630: return "AMD RV630"; 319 case CHIP_RV670: return "AMD RV670"; 320 case CHIP_RV620: return "AMD RV620"; 321 case CHIP_RV635: return "AMD RV635"; 322 case CHIP_RS780: return "AMD RS780"; 323 case CHIP_RS880: return "AMD RS880"; 324 case CHIP_RV770: return "AMD RV770"; 325 case CHIP_RV730: return "AMD RV730"; 326 case CHIP_RV710: return "AMD RV710"; 327 case CHIP_RV740: return "AMD RV740"; 328 case CHIP_CEDAR: return "AMD CEDAR"; 329 case CHIP_REDWOOD: return "AMD REDWOOD"; 330 case CHIP_JUNIPER: return "AMD JUNIPER"; 331 case CHIP_CYPRESS: return "AMD CYPRESS"; 332 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 333 case CHIP_PALM: return "AMD PALM"; 334 case CHIP_SUMO: return "AMD SUMO"; 335 case CHIP_SUMO2: return "AMD SUMO2"; 336 case CHIP_BARTS: return "AMD BARTS"; 337 case CHIP_TURKS: return "AMD TURKS"; 338 case CHIP_CAICOS: return "AMD CAICOS"; 339 case CHIP_CAYMAN: return "AMD CAYMAN"; 340 default: return "AMD unknown"; 341 } 342} 343 344static const char* r600_get_name(struct pipe_screen* pscreen) 345{ 346 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 347 348 return r600_get_family_name(rscreen->family); 349} 350 351static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 352{ 353 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 354 enum radeon_family family = rscreen->family; 355 356 switch (param) { 357 /* Supported features (boolean caps). */ 358 case PIPE_CAP_NPOT_TEXTURES: 359 case PIPE_CAP_TWO_SIDED_STENCIL: 360 case PIPE_CAP_DUAL_SOURCE_BLEND: 361 case PIPE_CAP_ANISOTROPIC_FILTER: 362 case PIPE_CAP_POINT_SPRITE: 363 case PIPE_CAP_OCCLUSION_QUERY: 364 case PIPE_CAP_TEXTURE_SHADOW_MAP: 365 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 366 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 367 case PIPE_CAP_TEXTURE_SWIZZLE: 368 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 369 case PIPE_CAP_DEPTH_CLAMP: 370 case PIPE_CAP_SHADER_STENCIL_EXPORT: 371 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 372 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 373 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 374 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 375 case PIPE_CAP_SM3: 376 case PIPE_CAP_SEAMLESS_CUBE_MAP: 377 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL: 378 case PIPE_CAP_PRIMITIVE_RESTART: 379 case PIPE_CAP_CONDITIONAL_RENDER: 380 case PIPE_CAP_TEXTURE_BARRIER: 381 return 1; 382 383 /* Supported except the original R600. */ 384 case PIPE_CAP_INDEP_BLEND_ENABLE: 385 case PIPE_CAP_INDEP_BLEND_FUNC: 386 /* R600 doesn't support per-MRT blends */ 387 return family == CHIP_R600 ? 0 : 1; 388 389 /* Supported on Evergreen. */ 390 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 391 return family >= CHIP_CEDAR ? 1 : 0; 392 393 /* Unsupported features. */ 394 case PIPE_CAP_STREAM_OUTPUT: 395 case PIPE_CAP_TGSI_INSTANCEID: 396 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 397 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 398 return 0; 399 400 /* Texturing. */ 401 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 402 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 403 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 404 if (family >= CHIP_CEDAR) 405 return 15; 406 else 407 return 14; 408 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 409 return rscreen->info.drm_minor >= 9 ? 410 (family >= CHIP_CEDAR ? 16384 : 8192) : 0; 411 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 412 return 32; 413 414 /* Render targets. */ 415 case PIPE_CAP_MAX_RENDER_TARGETS: 416 /* FIXME some r6xx are buggy and can only do 4 */ 417 return 8; 418 419 /* Timer queries, present when the clock frequency is non zero. */ 420 case PIPE_CAP_TIMER_QUERY: 421 return rscreen->info.r600_clock_crystal_freq != 0; 422 423 case PIPE_CAP_MIN_TEXEL_OFFSET: 424 return -8; 425 426 case PIPE_CAP_MAX_TEXEL_OFFSET: 427 return 7; 428 429 default: 430 R600_ERR("r600: unknown param %d\n", param); 431 return 0; 432 } 433} 434 435static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param) 436{ 437 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 438 enum radeon_family family = rscreen->family; 439 440 switch (param) { 441 case PIPE_CAP_MAX_LINE_WIDTH: 442 case PIPE_CAP_MAX_LINE_WIDTH_AA: 443 case PIPE_CAP_MAX_POINT_WIDTH: 444 case PIPE_CAP_MAX_POINT_WIDTH_AA: 445 if (family >= CHIP_CEDAR) 446 return 16384.0f; 447 else 448 return 8192.0f; 449 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: 450 return 16.0f; 451 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: 452 return 16.0f; 453 default: 454 R600_ERR("r600: unsupported paramf %d\n", param); 455 return 0.0f; 456 } 457} 458 459static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 460{ 461 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 462 switch(shader) 463 { 464 case PIPE_SHADER_FRAGMENT: 465 case PIPE_SHADER_VERTEX: 466 break; 467 case PIPE_SHADER_GEOMETRY: 468 /* TODO: support and enable geometry programs */ 469 return 0; 470 default: 471 /* TODO: support tessellation on Evergreen */ 472 return 0; 473 } 474 475 /* TODO: all these should be fixed, since r600 surely supports much more! */ 476 switch (param) { 477 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 478 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 479 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 480 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 481 return 16384; 482 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 483 return 8; /* FIXME */ 484 case PIPE_SHADER_CAP_MAX_INPUTS: 485 if(shader == PIPE_SHADER_FRAGMENT) 486 return 34; 487 else 488 return 32; 489 case PIPE_SHADER_CAP_MAX_TEMPS: 490 return 256; /* Max native temporaries. */ 491 case PIPE_SHADER_CAP_MAX_ADDRS: 492 /* FIXME Isn't this equal to TEMPS? */ 493 return 1; /* Max native address registers */ 494 case PIPE_SHADER_CAP_MAX_CONSTS: 495 return R600_MAX_CONST_BUFFER_SIZE; 496 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 497 return R600_MAX_CONST_BUFFERS; 498 case PIPE_SHADER_CAP_MAX_PREDS: 499 return 0; /* FIXME */ 500 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 501 return 1; 502 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 503 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 504 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 505 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 506 return 1; 507 case PIPE_SHADER_CAP_SUBROUTINES: 508 return 0; 509 case PIPE_SHADER_CAP_INTEGERS: 510 if (rscreen->chip_class == EVERGREEN) 511 return 1; 512 return 0; 513 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 514 return 16; 515 case PIPE_SHADER_CAP_OUTPUT_READ: 516 return 1; 517 default: 518 return 0; 519 } 520} 521 522static int r600_get_video_param(struct pipe_screen *screen, 523 enum pipe_video_profile profile, 524 enum pipe_video_cap param) 525{ 526 switch (param) { 527 case PIPE_VIDEO_CAP_SUPPORTED: 528 return vl_profile_supported(screen, profile); 529 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 530 return 1; 531 case PIPE_VIDEO_CAP_MAX_WIDTH: 532 case PIPE_VIDEO_CAP_MAX_HEIGHT: 533 return vl_video_buffer_max_size(screen); 534 case PIPE_VIDEO_CAP_NUM_BUFFERS_DESIRED: 535 return vl_num_buffers_desired(screen, profile); 536 default: 537 return 0; 538 } 539} 540 541static void r600_destroy_screen(struct pipe_screen* pscreen) 542{ 543 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 544 545 if (rscreen == NULL) 546 return; 547 548 rscreen->ws->destroy(rscreen->ws); 549 550 util_slab_destroy(&rscreen->pool_buffers); 551 pipe_mutex_destroy(rscreen->mutex_num_contexts); 552 FREE(rscreen); 553} 554 555static void r600_fence_reference(struct pipe_screen *pscreen, 556 struct pipe_fence_handle **ptr, 557 struct pipe_fence_handle *fence) 558{ 559 struct r600_fence **oldf = (struct r600_fence**)ptr; 560 struct r600_fence *newf = (struct r600_fence*)fence; 561 562 if (pipe_reference(&(*oldf)->reference, &newf->reference)) { 563 struct r600_pipe_context *ctx = (*oldf)->ctx; 564 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool); 565 } 566 567 *ptr = fence; 568} 569 570static boolean r600_fence_signalled(struct pipe_screen *pscreen, 571 struct pipe_fence_handle *fence) 572{ 573 struct r600_fence *rfence = (struct r600_fence*)fence; 574 struct r600_pipe_context *ctx = rfence->ctx; 575 576 return ctx->fences.data[rfence->index]; 577} 578 579static boolean r600_fence_finish(struct pipe_screen *pscreen, 580 struct pipe_fence_handle *fence, 581 uint64_t timeout) 582{ 583 struct r600_fence *rfence = (struct r600_fence*)fence; 584 struct r600_pipe_context *ctx = rfence->ctx; 585 int64_t start_time = 0; 586 unsigned spins = 0; 587 588 if (timeout != PIPE_TIMEOUT_INFINITE) { 589 start_time = os_time_get(); 590 591 /* Convert to microseconds. */ 592 timeout /= 1000; 593 } 594 595 while (ctx->fences.data[rfence->index] == 0) { 596 if (++spins % 256) 597 continue; 598#ifdef PIPE_OS_UNIX 599 sched_yield(); 600#else 601 os_time_sleep(10); 602#endif 603 if (timeout != PIPE_TIMEOUT_INFINITE && 604 os_time_get() - start_time >= timeout) { 605 return FALSE; 606 } 607 } 608 609 return TRUE; 610} 611 612static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 613{ 614 switch ((tiling_config & 0xe) >> 1) { 615 case 0: 616 rscreen->tiling_info.num_channels = 1; 617 break; 618 case 1: 619 rscreen->tiling_info.num_channels = 2; 620 break; 621 case 2: 622 rscreen->tiling_info.num_channels = 4; 623 break; 624 case 3: 625 rscreen->tiling_info.num_channels = 8; 626 break; 627 default: 628 return -EINVAL; 629 } 630 631 switch ((tiling_config & 0x30) >> 4) { 632 case 0: 633 rscreen->tiling_info.num_banks = 4; 634 break; 635 case 1: 636 rscreen->tiling_info.num_banks = 8; 637 break; 638 default: 639 return -EINVAL; 640 641 } 642 switch ((tiling_config & 0xc0) >> 6) { 643 case 0: 644 rscreen->tiling_info.group_bytes = 256; 645 break; 646 case 1: 647 rscreen->tiling_info.group_bytes = 512; 648 break; 649 default: 650 return -EINVAL; 651 } 652 return 0; 653} 654 655static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 656{ 657 switch (tiling_config & 0xf) { 658 case 0: 659 rscreen->tiling_info.num_channels = 1; 660 break; 661 case 1: 662 rscreen->tiling_info.num_channels = 2; 663 break; 664 case 2: 665 rscreen->tiling_info.num_channels = 4; 666 break; 667 case 3: 668 rscreen->tiling_info.num_channels = 8; 669 break; 670 default: 671 return -EINVAL; 672 } 673 674 switch ((tiling_config & 0xf0) >> 4) { 675 case 0: 676 rscreen->tiling_info.num_banks = 4; 677 break; 678 case 1: 679 rscreen->tiling_info.num_banks = 8; 680 break; 681 case 2: 682 rscreen->tiling_info.num_banks = 16; 683 break; 684 default: 685 return -EINVAL; 686 } 687 688 switch ((tiling_config & 0xf00) >> 8) { 689 case 0: 690 rscreen->tiling_info.group_bytes = 256; 691 break; 692 case 1: 693 rscreen->tiling_info.group_bytes = 512; 694 break; 695 default: 696 return -EINVAL; 697 } 698 return 0; 699} 700 701static int r600_init_tiling(struct r600_screen *rscreen) 702{ 703 uint32_t tiling_config = rscreen->info.r600_tiling_config; 704 705 /* set default group bytes, overridden by tiling info ioctl */ 706 if (rscreen->chip_class <= R700) { 707 rscreen->tiling_info.group_bytes = 256; 708 } else { 709 rscreen->tiling_info.group_bytes = 512; 710 } 711 712 if (!tiling_config) 713 return 0; 714 715 if (rscreen->chip_class <= R700) { 716 return r600_interpret_tiling(rscreen, tiling_config); 717 } else { 718 return evergreen_interpret_tiling(rscreen, tiling_config); 719 } 720} 721 722static unsigned radeon_family_from_device(unsigned device) 723{ 724 switch (device) { 725#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family; 726#include "pci_ids/r600_pci_ids.h" 727#undef CHIPSET 728 default: 729 return CHIP_UNKNOWN; 730 } 731} 732 733struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) 734{ 735 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen); 736 if (rscreen == NULL) { 737 return NULL; 738 } 739 740 rscreen->ws = ws; 741 ws->query_info(ws, &rscreen->info); 742 743 rscreen->family = radeon_family_from_device(rscreen->info.pci_id); 744 if (rscreen->family == CHIP_UNKNOWN) { 745 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); 746 FREE(rscreen); 747 return NULL; 748 } 749 750 /* setup class */ 751 if (rscreen->family == CHIP_CAYMAN) { 752 rscreen->chip_class = CAYMAN; 753 } else if (rscreen->family >= CHIP_CEDAR) { 754 rscreen->chip_class = EVERGREEN; 755 } else if (rscreen->family >= CHIP_RV770) { 756 rscreen->chip_class = R700; 757 } else { 758 rscreen->chip_class = R600; 759 } 760 761 if (r600_init_tiling(rscreen)) { 762 FREE(rscreen); 763 return NULL; 764 } 765 766 rscreen->screen.winsys = (struct pipe_winsys*)ws; 767 rscreen->screen.destroy = r600_destroy_screen; 768 rscreen->screen.get_name = r600_get_name; 769 rscreen->screen.get_vendor = r600_get_vendor; 770 rscreen->screen.get_param = r600_get_param; 771 rscreen->screen.get_shader_param = r600_get_shader_param; 772 rscreen->screen.get_paramf = r600_get_paramf; 773 rscreen->screen.get_video_param = r600_get_video_param; 774 if (rscreen->chip_class >= EVERGREEN) { 775 rscreen->screen.is_format_supported = evergreen_is_format_supported; 776 } else { 777 rscreen->screen.is_format_supported = r600_is_format_supported; 778 } 779 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; 780 rscreen->screen.context_create = r600_create_context; 781 rscreen->screen.fence_reference = r600_fence_reference; 782 rscreen->screen.fence_signalled = r600_fence_signalled; 783 rscreen->screen.fence_finish = r600_fence_finish; 784 r600_init_screen_resource_functions(&rscreen->screen); 785 786 util_format_s3tc_init(); 787 788 util_slab_create(&rscreen->pool_buffers, 789 sizeof(struct r600_resource), 64, 790 UTIL_SLAB_SINGLETHREADED); 791 792 pipe_mutex_init(rscreen->mutex_num_contexts); 793 794 return &rscreen->screen; 795} 796