r600_pipe.c revision 2d7738eb2bee41656953d1173926f546c6711bad
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include <stdio.h> 24#include <errno.h> 25#include <pipe/p_defines.h> 26#include <pipe/p_state.h> 27#include <pipe/p_context.h> 28#include <tgsi/tgsi_scan.h> 29#include <tgsi/tgsi_parse.h> 30#include <tgsi/tgsi_util.h> 31#include <util/u_blitter.h> 32#include <util/u_double_list.h> 33#include <util/u_transfer.h> 34#include <util/u_surface.h> 35#include <util/u_pack_color.h> 36#include <util/u_memory.h> 37#include <util/u_inlines.h> 38#include "util/u_upload_mgr.h" 39#include <pipebuffer/pb_buffer.h> 40#include "r600.h" 41#include "r600d.h" 42#include "r600_resource.h" 43#include "r600_shader.h" 44#include "r600_pipe.h" 45#include "r600_state_inlines.h" 46 47/* 48 * pipe_context 49 */ 50static void r600_flush(struct pipe_context *ctx, unsigned flags, 51 struct pipe_fence_handle **fence) 52{ 53 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 54#if 0 55 static int dc = 0; 56 char dname[256]; 57#endif 58 59 if (!rctx->ctx.pm4_cdwords) 60 return; 61 62#if 0 63 sprintf(dname, "gallium-%08d.bof", dc); 64 if (dc < 20) { 65 r600_context_dump_bof(&rctx->ctx, dname); 66 R600_ERR("dumped %s\n", dname); 67 } 68 dc++; 69#endif 70 r600_context_flush(&rctx->ctx); 71 72 u_upload_flush(rctx->upload_vb); 73 u_upload_flush(rctx->upload_const); 74} 75 76static void r600_destroy_context(struct pipe_context *context) 77{ 78 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context; 79 80 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 81 82 r600_end_vertex_translate(rctx); 83 84 r600_context_fini(&rctx->ctx); 85 86 util_blitter_destroy(rctx->blitter); 87 88 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 89 free(rctx->states[i]); 90 } 91 92 u_upload_destroy(rctx->upload_vb); 93 u_upload_destroy(rctx->upload_const); 94 95 if (rctx->tran.translate_cache) 96 translate_cache_destroy(rctx->tran.translate_cache); 97 98 FREE(rctx->ps_resource); 99 FREE(rctx->vs_resource); 100 FREE(rctx); 101} 102 103static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 104{ 105 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context); 106 struct r600_screen* rscreen = (struct r600_screen *)screen; 107 enum chip_class class; 108 109 if (rctx == NULL) 110 return NULL; 111 rctx->context.winsys = rscreen->screen.winsys; 112 rctx->context.screen = screen; 113 rctx->context.priv = priv; 114 rctx->context.destroy = r600_destroy_context; 115 rctx->context.flush = r600_flush; 116 117 /* Easy accessing of screen/winsys. */ 118 rctx->screen = rscreen; 119 rctx->radeon = rscreen->radeon; 120 rctx->family = r600_get_family(rctx->radeon); 121 122 r600_init_blit_functions(rctx); 123 r600_init_query_functions(rctx); 124 r600_init_context_resource_functions(rctx); 125 r600_init_surface_functions(rctx); 126 rctx->context.draw_vbo = r600_draw_vbo; 127 128 switch (r600_get_family(rctx->radeon)) { 129 case CHIP_R600: 130 case CHIP_RV610: 131 case CHIP_RV630: 132 case CHIP_RV670: 133 case CHIP_RV620: 134 case CHIP_RV635: 135 case CHIP_RS780: 136 case CHIP_RS880: 137 case CHIP_RV770: 138 case CHIP_RV730: 139 case CHIP_RV710: 140 case CHIP_RV740: 141 r600_init_state_functions(rctx); 142 if (r600_context_init(&rctx->ctx, rctx->radeon)) { 143 r600_destroy_context(&rctx->context); 144 return NULL; 145 } 146 r600_init_config(rctx); 147 break; 148 case CHIP_CEDAR: 149 case CHIP_REDWOOD: 150 case CHIP_JUNIPER: 151 case CHIP_CYPRESS: 152 case CHIP_HEMLOCK: 153 case CHIP_PALM: 154 case CHIP_BARTS: 155 case CHIP_TURKS: 156 case CHIP_CAICOS: 157 evergreen_init_state_functions(rctx); 158 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) { 159 r600_destroy_context(&rctx->context); 160 return NULL; 161 } 162 evergreen_init_config(rctx); 163 break; 164 default: 165 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon)); 166 r600_destroy_context(&rctx->context); 167 return NULL; 168 } 169 170 rctx->upload_vb = u_upload_create(&rctx->context, 1024 * 1024, 16, 171 PIPE_BIND_VERTEX_BUFFER | 172 PIPE_BIND_INDEX_BUFFER); 173 if (rctx->upload_vb == NULL) { 174 r600_destroy_context(&rctx->context); 175 return NULL; 176 } 177 178 rctx->upload_const = u_upload_create(&rctx->context, 1024 * 1024, 256, 179 PIPE_BIND_CONSTANT_BUFFER); 180 if (rctx->upload_const == NULL) { 181 r600_destroy_context(&rctx->context); 182 return NULL; 183 } 184 185 rctx->blitter = util_blitter_create(&rctx->context); 186 if (rctx->blitter == NULL) { 187 FREE(rctx); 188 return NULL; 189 } 190 191 rctx->tran.translate_cache = translate_cache_create(); 192 if (rctx->tran.translate_cache == NULL) { 193 FREE(rctx); 194 return NULL; 195 } 196 197 rctx->vs_resource = CALLOC(R600_RESOURCE_ARRAY_SIZE, sizeof(struct r600_pipe_state)); 198 if (!rctx->vs_resource) { 199 FREE(rctx); 200 return NULL; 201 } 202 203 rctx->ps_resource = CALLOC(R600_RESOURCE_ARRAY_SIZE, sizeof(struct r600_pipe_state)); 204 if (!rctx->ps_resource) { 205 FREE(rctx); 206 return NULL; 207 } 208 209 class = r600_get_family_class(rctx->radeon); 210 if (class == R600 || class == R700) 211 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 212 else 213 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 214 215 return &rctx->context; 216} 217 218/* 219 * pipe_screen 220 */ 221static const char* r600_get_vendor(struct pipe_screen* pscreen) 222{ 223 return "X.Org"; 224} 225 226static const char *r600_get_family_name(enum radeon_family family) 227{ 228 switch(family) { 229 case CHIP_R600: return "AMD R600"; 230 case CHIP_RV610: return "AMD RV610"; 231 case CHIP_RV630: return "AMD RV630"; 232 case CHIP_RV670: return "AMD RV670"; 233 case CHIP_RV620: return "AMD RV620"; 234 case CHIP_RV635: return "AMD RV635"; 235 case CHIP_RS780: return "AMD RS780"; 236 case CHIP_RS880: return "AMD RS880"; 237 case CHIP_RV770: return "AMD RV770"; 238 case CHIP_RV730: return "AMD RV730"; 239 case CHIP_RV710: return "AMD RV710"; 240 case CHIP_RV740: return "AMD RV740"; 241 case CHIP_CEDAR: return "AMD CEDAR"; 242 case CHIP_REDWOOD: return "AMD REDWOOD"; 243 case CHIP_JUNIPER: return "AMD JUNIPER"; 244 case CHIP_CYPRESS: return "AMD CYPRESS"; 245 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 246 case CHIP_PALM: return "AMD PALM"; 247 case CHIP_BARTS: return "AMD BARTS"; 248 case CHIP_TURKS: return "AMD TURKS"; 249 case CHIP_CAICOS: return "AMD CAICOS"; 250 default: return "AMD unknown"; 251 } 252} 253 254static const char* r600_get_name(struct pipe_screen* pscreen) 255{ 256 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 257 enum radeon_family family = r600_get_family(rscreen->radeon); 258 259 return r600_get_family_name(family); 260} 261 262static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 263{ 264 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 265 enum radeon_family family = r600_get_family(rscreen->radeon); 266 267 switch (param) { 268 /* Supported features (boolean caps). */ 269 case PIPE_CAP_NPOT_TEXTURES: 270 case PIPE_CAP_TWO_SIDED_STENCIL: 271 case PIPE_CAP_GLSL: 272 case PIPE_CAP_DUAL_SOURCE_BLEND: 273 case PIPE_CAP_ANISOTROPIC_FILTER: 274 case PIPE_CAP_POINT_SPRITE: 275 case PIPE_CAP_OCCLUSION_QUERY: 276 case PIPE_CAP_TEXTURE_SHADOW_MAP: 277 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 278 case PIPE_CAP_TEXTURE_MIRROR_REPEAT: 279 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 280 case PIPE_CAP_SM3: 281 case PIPE_CAP_TEXTURE_SWIZZLE: 282 case PIPE_CAP_INDEP_BLEND_ENABLE: 283 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 284 case PIPE_CAP_DEPTH_CLAMP: 285 case PIPE_CAP_SHADER_STENCIL_EXPORT: 286 return 1; 287 288 /* Unsupported features (boolean caps). */ 289 case PIPE_CAP_STREAM_OUTPUT: 290 case PIPE_CAP_PRIMITIVE_RESTART: 291 case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */ 292 case PIPE_CAP_INSTANCED_DRAWING: 293 case PIPE_CAP_ARRAY_TEXTURES: 294 return 0; 295 296 /* Texturing. */ 297 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 298 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 299 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 300 if (family >= CHIP_CEDAR) 301 return 15; 302 else 303 return 14; 304 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS: 305 /* FIXME allow this once infrastructure is there */ 306 return 16; 307 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS: 308 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 309 return 16; 310 311 /* Render targets. */ 312 case PIPE_CAP_MAX_RENDER_TARGETS: 313 /* FIXME some r6xx are buggy and can only do 4 */ 314 return 8; 315 316 /* Fragment coordinate conventions. */ 317 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 318 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 319 return 1; 320 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 321 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 322 return 0; 323 324 /* Timer queries, present when the clock frequency is non zero. */ 325 case PIPE_CAP_TIMER_QUERY: 326 return r600_get_clock_crystal_freq(rscreen->radeon) != 0; 327 328 default: 329 R600_ERR("r600: unknown param %d\n", param); 330 return 0; 331 } 332} 333 334static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param) 335{ 336 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 337 enum radeon_family family = r600_get_family(rscreen->radeon); 338 339 switch (param) { 340 case PIPE_CAP_MAX_LINE_WIDTH: 341 case PIPE_CAP_MAX_LINE_WIDTH_AA: 342 case PIPE_CAP_MAX_POINT_WIDTH: 343 case PIPE_CAP_MAX_POINT_WIDTH_AA: 344 if (family >= CHIP_CEDAR) 345 return 16384.0f; 346 else 347 return 8192.0f; 348 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: 349 return 16.0f; 350 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: 351 return 16.0f; 352 default: 353 R600_ERR("r600: unsupported paramf %d\n", param); 354 return 0.0f; 355 } 356} 357 358static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 359{ 360 switch(shader) 361 { 362 case PIPE_SHADER_FRAGMENT: 363 case PIPE_SHADER_VERTEX: 364 break; 365 case PIPE_SHADER_GEOMETRY: 366 /* TODO: support and enable geometry programs */ 367 return 0; 368 default: 369 /* TODO: support tessellation on Evergreen */ 370 return 0; 371 } 372 373 /* TODO: all these should be fixed, since r600 surely supports much more! */ 374 switch (param) { 375 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 376 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 377 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 378 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 379 return 16384; 380 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 381 return 8; /* FIXME */ 382 case PIPE_SHADER_CAP_MAX_INPUTS: 383 if(shader == PIPE_SHADER_FRAGMENT) 384 return 10; 385 else 386 return 16; 387 case PIPE_SHADER_CAP_MAX_TEMPS: 388 return 256; //max native temporaries 389 case PIPE_SHADER_CAP_MAX_ADDRS: 390 return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */ 391 case PIPE_SHADER_CAP_MAX_CONSTS: 392 return 256; //max native parameters 393 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 394 return 1; 395 case PIPE_SHADER_CAP_MAX_PREDS: 396 return 0; /* FIXME */ 397 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 398 return 1; 399 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 400 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 401 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 402 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 403 return 1; 404 case PIPE_SHADER_CAP_SUBROUTINES: 405 return 0; 406 default: 407 return 0; 408 } 409} 410 411static boolean r600_is_format_supported(struct pipe_screen* screen, 412 enum pipe_format format, 413 enum pipe_texture_target target, 414 unsigned sample_count, 415 unsigned usage, 416 unsigned geom_flags) 417{ 418 unsigned retval = 0; 419 if (target >= PIPE_MAX_TEXTURE_TYPES) { 420 R600_ERR("r600: unsupported texture type %d\n", target); 421 return FALSE; 422 } 423 424 /* Multisample */ 425 if (sample_count > 1) 426 return FALSE; 427 428 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 429 r600_is_sampler_format_supported(format)) { 430 retval |= PIPE_BIND_SAMPLER_VIEW; 431 } 432 433 if ((usage & (PIPE_BIND_RENDER_TARGET | 434 PIPE_BIND_DISPLAY_TARGET | 435 PIPE_BIND_SCANOUT | 436 PIPE_BIND_SHARED)) && 437 r600_is_colorbuffer_format_supported(format)) { 438 retval |= usage & 439 (PIPE_BIND_RENDER_TARGET | 440 PIPE_BIND_DISPLAY_TARGET | 441 PIPE_BIND_SCANOUT | 442 PIPE_BIND_SHARED); 443 } 444 445 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 446 r600_is_zs_format_supported(format)) { 447 retval |= PIPE_BIND_DEPTH_STENCIL; 448 } 449 450 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 451 r600_is_vertex_format_supported(format)) 452 retval |= PIPE_BIND_VERTEX_BUFFER; 453 454 if (usage & PIPE_BIND_TRANSFER_READ) 455 retval |= PIPE_BIND_TRANSFER_READ; 456 if (usage & PIPE_BIND_TRANSFER_WRITE) 457 retval |= PIPE_BIND_TRANSFER_WRITE; 458 459 return retval == usage; 460} 461 462static void r600_destroy_screen(struct pipe_screen* pscreen) 463{ 464 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 465 466 if (rscreen == NULL) 467 return; 468 469 radeon_decref(rscreen->radeon); 470 471 FREE(rscreen); 472} 473 474 475struct pipe_screen *r600_screen_create(struct radeon *radeon) 476{ 477 struct r600_screen *rscreen; 478 479 rscreen = CALLOC_STRUCT(r600_screen); 480 if (rscreen == NULL) { 481 return NULL; 482 } 483 484 rscreen->radeon = radeon; 485 rscreen->screen.winsys = (struct pipe_winsys*)radeon; 486 rscreen->screen.destroy = r600_destroy_screen; 487 rscreen->screen.get_name = r600_get_name; 488 rscreen->screen.get_vendor = r600_get_vendor; 489 rscreen->screen.get_param = r600_get_param; 490 rscreen->screen.get_shader_param = r600_get_shader_param; 491 rscreen->screen.get_paramf = r600_get_paramf; 492 rscreen->screen.is_format_supported = r600_is_format_supported; 493 rscreen->screen.context_create = r600_create_context; 494 r600_init_screen_resource_functions(&rscreen->screen); 495 496 rscreen->tiling_info = r600_get_tiling_info(radeon); 497 498 return &rscreen->screen; 499} 500