r600_pipe.c revision 320adb93a137a733da4b44f41e2d8ba01f164568
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include <stdio.h> 24#include <errno.h> 25#include <pipe/p_defines.h> 26#include <pipe/p_state.h> 27#include <pipe/p_context.h> 28#include <tgsi/tgsi_scan.h> 29#include <tgsi/tgsi_parse.h> 30#include <tgsi/tgsi_util.h> 31#include <util/u_blitter.h> 32#include <util/u_double_list.h> 33#include "util/u_format.h" 34#include <util/u_format_s3tc.h> 35#include <util/u_transfer.h> 36#include <util/u_surface.h> 37#include <util/u_pack_color.h> 38#include <util/u_memory.h> 39#include <util/u_inlines.h> 40#include "util/u_upload_mgr.h" 41#include "os/os_time.h" 42#include <pipebuffer/pb_buffer.h> 43#include "r600.h" 44#include "r600d.h" 45#include "r600_resource.h" 46#include "r600_shader.h" 47#include "r600_pipe.h" 48#include "r600_state_inlines.h" 49 50/* 51 * pipe_context 52 */ 53static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx) 54{ 55 struct r600_fence *fence = NULL; 56 57 if (!ctx->fences.bo) { 58 /* Create the shared buffer object */ 59 ctx->fences.bo = r600_bo(ctx->radeon, 4096, 0, 0, 0); 60 if (!ctx->fences.bo) { 61 R600_ERR("r600: failed to create bo for fence objects\n"); 62 return NULL; 63 } 64 ctx->fences.data = r600_bo_map(ctx->radeon, ctx->fences.bo, PB_USAGE_UNSYNCHRONIZED, NULL); 65 } 66 67 if (!LIST_IS_EMPTY(&ctx->fences.pool)) { 68 struct r600_fence *entry; 69 70 /* Try to find a freed fence that has been signalled */ 71 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) { 72 if (ctx->fences.data[entry->index] != 0) { 73 LIST_DELINIT(&entry->head); 74 fence = entry; 75 break; 76 } 77 } 78 } 79 80 if (!fence) { 81 /* Allocate a new fence */ 82 struct r600_fence_block *block; 83 unsigned index; 84 85 if ((ctx->fences.next_index + 1) >= 1024) { 86 R600_ERR("r600: too many concurrent fences\n"); 87 return NULL; 88 } 89 90 index = ctx->fences.next_index++; 91 92 if (!(index % FENCE_BLOCK_SIZE)) { 93 /* Allocate a new block */ 94 block = CALLOC_STRUCT(r600_fence_block); 95 if (block == NULL) 96 return NULL; 97 98 LIST_ADD(&block->head, &ctx->fences.blocks); 99 } else { 100 block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head); 101 } 102 103 fence = &block->fences[index % FENCE_BLOCK_SIZE]; 104 fence->ctx = ctx; 105 fence->index = index; 106 } 107 108 pipe_reference_init(&fence->reference, 1); 109 110 ctx->fences.data[fence->index] = 0; 111 r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1); 112 return fence; 113} 114 115static void r600_flush(struct pipe_context *ctx, 116 struct pipe_fence_handle **fence) 117{ 118 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 119 struct r600_fence **rfence = (struct r600_fence**)fence; 120 121#if 0 122 static int dc = 0; 123 char dname[256]; 124#endif 125 126 if (rfence) 127 *rfence = r600_create_fence(rctx); 128 129 if (!rctx->ctx.pm4_cdwords) 130 return; 131 132#if 0 133 sprintf(dname, "gallium-%08d.bof", dc); 134 if (dc < 20) { 135 r600_context_dump_bof(&rctx->ctx, dname); 136 R600_ERR("dumped %s\n", dname); 137 } 138 dc++; 139#endif 140 r600_context_flush(&rctx->ctx); 141 142 /* XXX This shouldn't be really necessary, but removing it breaks some tests. 143 * Needless buffer reallocations may significantly increase memory consumption, 144 * so getting rid of this call is important. */ 145 u_upload_flush(rctx->vbuf_mgr->uploader); 146} 147 148static void r600_update_num_contexts(struct r600_screen *rscreen, int diff) 149{ 150 pipe_mutex_lock(rscreen->mutex_num_contexts); 151 if (diff > 0) { 152 rscreen->num_contexts++; 153 154 if (rscreen->num_contexts > 1) 155 util_slab_set_thread_safety(&rscreen->pool_buffers, 156 UTIL_SLAB_MULTITHREADED); 157 } else { 158 rscreen->num_contexts--; 159 160 if (rscreen->num_contexts <= 1) 161 util_slab_set_thread_safety(&rscreen->pool_buffers, 162 UTIL_SLAB_SINGLETHREADED); 163 } 164 pipe_mutex_unlock(rscreen->mutex_num_contexts); 165} 166 167static void r600_destroy_context(struct pipe_context *context) 168{ 169 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context; 170 171 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 172 util_unreference_framebuffer_state(&rctx->framebuffer); 173 174 r600_context_fini(&rctx->ctx); 175 176 util_blitter_destroy(rctx->blitter); 177 178 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 179 free(rctx->states[i]); 180 } 181 182 u_vbuf_mgr_destroy(rctx->vbuf_mgr); 183 util_slab_destroy(&rctx->pool_transfers); 184 185 if (rctx->fences.bo) { 186 struct r600_fence_block *entry, *tmp; 187 188 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) { 189 LIST_DEL(&entry->head); 190 FREE(entry); 191 } 192 193 r600_bo_unmap(rctx->radeon, rctx->fences.bo); 194 r600_bo_reference(rctx->radeon, &rctx->fences.bo, NULL); 195 } 196 197 r600_update_num_contexts(rctx->screen, -1); 198 199 FREE(rctx); 200} 201 202static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 203{ 204 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context); 205 struct r600_screen* rscreen = (struct r600_screen *)screen; 206 enum chip_class class; 207 208 if (rctx == NULL) 209 return NULL; 210 211 r600_update_num_contexts(rscreen, 1); 212 213 rctx->context.winsys = rscreen->screen.winsys; 214 rctx->context.screen = screen; 215 rctx->context.priv = priv; 216 rctx->context.destroy = r600_destroy_context; 217 rctx->context.flush = r600_flush; 218 219 /* Easy accessing of screen/winsys. */ 220 rctx->screen = rscreen; 221 rctx->radeon = rscreen->radeon; 222 rctx->family = r600_get_family(rctx->radeon); 223 224 rctx->fences.bo = NULL; 225 rctx->fences.data = NULL; 226 rctx->fences.next_index = 0; 227 LIST_INITHEAD(&rctx->fences.pool); 228 LIST_INITHEAD(&rctx->fences.blocks); 229 230 r600_init_blit_functions(rctx); 231 r600_init_query_functions(rctx); 232 r600_init_context_resource_functions(rctx); 233 r600_init_surface_functions(rctx); 234 rctx->context.draw_vbo = r600_draw_vbo; 235 236 switch (r600_get_family(rctx->radeon)) { 237 case CHIP_R600: 238 case CHIP_RV610: 239 case CHIP_RV630: 240 case CHIP_RV670: 241 case CHIP_RV620: 242 case CHIP_RV635: 243 case CHIP_RS780: 244 case CHIP_RS880: 245 case CHIP_RV770: 246 case CHIP_RV730: 247 case CHIP_RV710: 248 case CHIP_RV740: 249 r600_init_state_functions(rctx); 250 if (r600_context_init(&rctx->ctx, rctx->radeon)) { 251 r600_destroy_context(&rctx->context); 252 return NULL; 253 } 254 r600_init_config(rctx); 255 break; 256 case CHIP_CEDAR: 257 case CHIP_REDWOOD: 258 case CHIP_JUNIPER: 259 case CHIP_CYPRESS: 260 case CHIP_HEMLOCK: 261 case CHIP_PALM: 262 case CHIP_BARTS: 263 case CHIP_TURKS: 264 case CHIP_CAICOS: 265 evergreen_init_state_functions(rctx); 266 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) { 267 r600_destroy_context(&rctx->context); 268 return NULL; 269 } 270 evergreen_init_config(rctx); 271 break; 272 default: 273 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon)); 274 r600_destroy_context(&rctx->context); 275 return NULL; 276 } 277 278 util_slab_create(&rctx->pool_transfers, 279 sizeof(struct pipe_transfer), 64, 280 UTIL_SLAB_SINGLETHREADED); 281 282 rctx->vbuf_mgr = u_vbuf_mgr_create(&rctx->context, 1024 * 1024, 256, 283 PIPE_BIND_VERTEX_BUFFER | 284 PIPE_BIND_INDEX_BUFFER | 285 PIPE_BIND_CONSTANT_BUFFER, 286 U_VERTEX_FETCH_DWORD_ALIGNED); 287 if (!rctx->vbuf_mgr) { 288 r600_destroy_context(&rctx->context); 289 return NULL; 290 } 291 292 rctx->blitter = util_blitter_create(&rctx->context); 293 if (rctx->blitter == NULL) { 294 r600_destroy_context(&rctx->context); 295 return NULL; 296 } 297 298 class = r600_get_family_class(rctx->radeon); 299 if (class == R600 || class == R700) 300 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 301 else 302 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 303 304 return &rctx->context; 305} 306 307/* 308 * pipe_screen 309 */ 310static const char* r600_get_vendor(struct pipe_screen* pscreen) 311{ 312 return "X.Org"; 313} 314 315static const char *r600_get_family_name(enum radeon_family family) 316{ 317 switch(family) { 318 case CHIP_R600: return "AMD R600"; 319 case CHIP_RV610: return "AMD RV610"; 320 case CHIP_RV630: return "AMD RV630"; 321 case CHIP_RV670: return "AMD RV670"; 322 case CHIP_RV620: return "AMD RV620"; 323 case CHIP_RV635: return "AMD RV635"; 324 case CHIP_RS780: return "AMD RS780"; 325 case CHIP_RS880: return "AMD RS880"; 326 case CHIP_RV770: return "AMD RV770"; 327 case CHIP_RV730: return "AMD RV730"; 328 case CHIP_RV710: return "AMD RV710"; 329 case CHIP_RV740: return "AMD RV740"; 330 case CHIP_CEDAR: return "AMD CEDAR"; 331 case CHIP_REDWOOD: return "AMD REDWOOD"; 332 case CHIP_JUNIPER: return "AMD JUNIPER"; 333 case CHIP_CYPRESS: return "AMD CYPRESS"; 334 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 335 case CHIP_PALM: return "AMD PALM"; 336 case CHIP_BARTS: return "AMD BARTS"; 337 case CHIP_TURKS: return "AMD TURKS"; 338 case CHIP_CAICOS: return "AMD CAICOS"; 339 default: return "AMD unknown"; 340 } 341} 342 343static const char* r600_get_name(struct pipe_screen* pscreen) 344{ 345 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 346 enum radeon_family family = r600_get_family(rscreen->radeon); 347 348 return r600_get_family_name(family); 349} 350 351static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 352{ 353 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 354 enum radeon_family family = r600_get_family(rscreen->radeon); 355 356 switch (param) { 357 /* Supported features (boolean caps). */ 358 case PIPE_CAP_NPOT_TEXTURES: 359 case PIPE_CAP_TWO_SIDED_STENCIL: 360 case PIPE_CAP_GLSL: 361 case PIPE_CAP_DUAL_SOURCE_BLEND: 362 case PIPE_CAP_ANISOTROPIC_FILTER: 363 case PIPE_CAP_POINT_SPRITE: 364 case PIPE_CAP_OCCLUSION_QUERY: 365 case PIPE_CAP_TEXTURE_SHADOW_MAP: 366 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 367 case PIPE_CAP_TEXTURE_MIRROR_REPEAT: 368 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 369 case PIPE_CAP_SM3: 370 case PIPE_CAP_TEXTURE_SWIZZLE: 371 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 372 case PIPE_CAP_DEPTH_CLAMP: 373 case PIPE_CAP_SHADER_STENCIL_EXPORT: 374 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 375 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 376 return 1; 377 case PIPE_CAP_INDEP_BLEND_ENABLE: 378 case PIPE_CAP_INDEP_BLEND_FUNC: 379 /* R600 doesn't support per-MRT blends */ 380 if (family == CHIP_R600) 381 return 0; 382 else 383 return 1; 384 385 case PIPE_CAP_TGSI_INSTANCEID: 386 return 0; 387 388 /* Unsupported features (boolean caps). */ 389 case PIPE_CAP_STREAM_OUTPUT: 390 case PIPE_CAP_PRIMITIVE_RESTART: 391 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL: 392 return 0; 393 394 case PIPE_CAP_ARRAY_TEXTURES: 395 /* fix once the CS checker upstream is fixed */ 396 return debug_get_bool_option("R600_ARRAY_TEXTURE", FALSE); 397 398 /* Texturing. */ 399 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 400 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 401 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 402 if (family >= CHIP_CEDAR) 403 return 15; 404 else 405 return 14; 406 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS: 407 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS: 408 return 16; 409 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 410 return 32; 411 412 /* Render targets. */ 413 case PIPE_CAP_MAX_RENDER_TARGETS: 414 /* FIXME some r6xx are buggy and can only do 4 */ 415 return 8; 416 417 /* Fragment coordinate conventions. */ 418 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 419 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 420 return 1; 421 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 422 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 423 return 0; 424 425 /* Timer queries, present when the clock frequency is non zero. */ 426 case PIPE_CAP_TIMER_QUERY: 427 return r600_get_clock_crystal_freq(rscreen->radeon) != 0; 428 429 default: 430 R600_ERR("r600: unknown param %d\n", param); 431 return 0; 432 } 433} 434 435static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param) 436{ 437 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 438 enum radeon_family family = r600_get_family(rscreen->radeon); 439 440 switch (param) { 441 case PIPE_CAP_MAX_LINE_WIDTH: 442 case PIPE_CAP_MAX_LINE_WIDTH_AA: 443 case PIPE_CAP_MAX_POINT_WIDTH: 444 case PIPE_CAP_MAX_POINT_WIDTH_AA: 445 if (family >= CHIP_CEDAR) 446 return 16384.0f; 447 else 448 return 8192.0f; 449 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: 450 return 16.0f; 451 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: 452 return 16.0f; 453 default: 454 R600_ERR("r600: unsupported paramf %d\n", param); 455 return 0.0f; 456 } 457} 458 459static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 460{ 461 switch(shader) 462 { 463 case PIPE_SHADER_FRAGMENT: 464 case PIPE_SHADER_VERTEX: 465 break; 466 case PIPE_SHADER_GEOMETRY: 467 /* TODO: support and enable geometry programs */ 468 return 0; 469 default: 470 /* TODO: support tessellation on Evergreen */ 471 return 0; 472 } 473 474 /* TODO: all these should be fixed, since r600 surely supports much more! */ 475 switch (param) { 476 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 477 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 478 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 479 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 480 return 16384; 481 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 482 return 8; /* FIXME */ 483 case PIPE_SHADER_CAP_MAX_INPUTS: 484 if(shader == PIPE_SHADER_FRAGMENT) 485 return 10; 486 else 487 return 16; 488 case PIPE_SHADER_CAP_MAX_TEMPS: 489 return 256; /* Max native temporaries. */ 490 case PIPE_SHADER_CAP_MAX_ADDRS: 491 /* FIXME Isn't this equal to TEMPS? */ 492 return 1; /* Max native address registers */ 493 case PIPE_SHADER_CAP_MAX_CONSTS: 494 return R600_MAX_CONST_BUFFER_SIZE; 495 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 496 return R600_MAX_CONST_BUFFERS; 497 case PIPE_SHADER_CAP_MAX_PREDS: 498 return 0; /* FIXME */ 499 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 500 return 1; 501 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 502 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 503 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 504 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 505 return 1; 506 case PIPE_SHADER_CAP_SUBROUTINES: 507 return 0; 508 default: 509 return 0; 510 } 511} 512 513static boolean r600_is_format_supported(struct pipe_screen* screen, 514 enum pipe_format format, 515 enum pipe_texture_target target, 516 unsigned sample_count, 517 unsigned usage) 518{ 519 unsigned retval = 0; 520 if (target >= PIPE_MAX_TEXTURE_TYPES) { 521 R600_ERR("r600: unsupported texture type %d\n", target); 522 return FALSE; 523 } 524 525 if (!util_format_is_supported(format, usage)) 526 return FALSE; 527 528 /* Multisample */ 529 if (sample_count > 1) 530 return FALSE; 531 532 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 533 r600_is_sampler_format_supported(screen, format)) { 534 retval |= PIPE_BIND_SAMPLER_VIEW; 535 } 536 537 if ((usage & (PIPE_BIND_RENDER_TARGET | 538 PIPE_BIND_DISPLAY_TARGET | 539 PIPE_BIND_SCANOUT | 540 PIPE_BIND_SHARED)) && 541 r600_is_colorbuffer_format_supported(format)) { 542 retval |= usage & 543 (PIPE_BIND_RENDER_TARGET | 544 PIPE_BIND_DISPLAY_TARGET | 545 PIPE_BIND_SCANOUT | 546 PIPE_BIND_SHARED); 547 } 548 549 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 550 r600_is_zs_format_supported(format)) { 551 retval |= PIPE_BIND_DEPTH_STENCIL; 552 } 553 554 if (usage & PIPE_BIND_VERTEX_BUFFER) { 555 struct r600_screen *rscreen = (struct r600_screen *)screen; 556 enum radeon_family family = r600_get_family(rscreen->radeon); 557 558 if (r600_is_vertex_format_supported(format, family)) { 559 retval |= PIPE_BIND_VERTEX_BUFFER; 560 } 561 } 562 563 if (usage & PIPE_BIND_TRANSFER_READ) 564 retval |= PIPE_BIND_TRANSFER_READ; 565 if (usage & PIPE_BIND_TRANSFER_WRITE) 566 retval |= PIPE_BIND_TRANSFER_WRITE; 567 568 return retval == usage; 569} 570 571static void r600_destroy_screen(struct pipe_screen* pscreen) 572{ 573 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 574 575 if (rscreen == NULL) 576 return; 577 578 radeon_decref(rscreen->radeon); 579 580 util_slab_destroy(&rscreen->pool_buffers); 581 pipe_mutex_destroy(rscreen->mutex_num_contexts); 582 FREE(rscreen); 583} 584 585static void r600_fence_reference(struct pipe_screen *pscreen, 586 struct pipe_fence_handle **ptr, 587 struct pipe_fence_handle *fence) 588{ 589 struct r600_fence **oldf = (struct r600_fence**)ptr; 590 struct r600_fence *newf = (struct r600_fence*)fence; 591 592 if (pipe_reference(&(*oldf)->reference, &newf->reference)) { 593 struct r600_pipe_context *ctx = (*oldf)->ctx; 594 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool); 595 } 596 597 *ptr = fence; 598} 599 600static boolean r600_fence_signalled(struct pipe_screen *pscreen, 601 struct pipe_fence_handle *fence) 602{ 603 struct r600_fence *rfence = (struct r600_fence*)fence; 604 struct r600_pipe_context *ctx = rfence->ctx; 605 606 return ctx->fences.data[rfence->index]; 607} 608 609static boolean r600_fence_finish(struct pipe_screen *pscreen, 610 struct pipe_fence_handle *fence, 611 uint64_t timeout) 612{ 613 struct r600_fence *rfence = (struct r600_fence*)fence; 614 struct r600_pipe_context *ctx = rfence->ctx; 615 int64_t start_time = 0; 616 unsigned spins = 0; 617 618 if (timeout != PIPE_TIMEOUT_INFINITE) { 619 start_time = os_time_get(); 620 621 /* Convert to microseconds. */ 622 timeout /= 1000; 623 } 624 625 while (ctx->fences.data[rfence->index] == 0) { 626 if (++spins % 256) 627 continue; 628#ifdef PIPE_OS_UNIX 629 sched_yield(); 630#else 631 os_time_sleep(10); 632#endif 633 if (timeout != PIPE_TIMEOUT_INFINITE && 634 os_time_get() - start_time >= timeout) { 635 return FALSE; 636 } 637 } 638 639 return TRUE; 640} 641 642struct pipe_screen *r600_screen_create(struct radeon *radeon) 643{ 644 struct r600_screen *rscreen; 645 646 rscreen = CALLOC_STRUCT(r600_screen); 647 if (rscreen == NULL) { 648 return NULL; 649 } 650 651 rscreen->radeon = radeon; 652 rscreen->screen.winsys = (struct pipe_winsys*)radeon; 653 rscreen->screen.destroy = r600_destroy_screen; 654 rscreen->screen.get_name = r600_get_name; 655 rscreen->screen.get_vendor = r600_get_vendor; 656 rscreen->screen.get_param = r600_get_param; 657 rscreen->screen.get_shader_param = r600_get_shader_param; 658 rscreen->screen.get_paramf = r600_get_paramf; 659 rscreen->screen.is_format_supported = r600_is_format_supported; 660 rscreen->screen.context_create = r600_create_context; 661 rscreen->screen.fence_reference = r600_fence_reference; 662 rscreen->screen.fence_signalled = r600_fence_signalled; 663 rscreen->screen.fence_finish = r600_fence_finish; 664 r600_init_screen_resource_functions(&rscreen->screen); 665 666 rscreen->tiling_info = r600_get_tiling_info(radeon); 667 util_format_s3tc_init(); 668 669 util_slab_create(&rscreen->pool_buffers, 670 sizeof(struct r600_resource_buffer), 64, 671 UTIL_SLAB_SINGLETHREADED); 672 673 pipe_mutex_init(rscreen->mutex_num_contexts); 674 675 return &rscreen->screen; 676} 677