r600_pipe.c revision 9d699cd845f3544fa6e149fa4ffb1d131d32b482
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_pipe.h" 24#include "r600_public.h" 25 26#include <errno.h> 27#include "pipe/p_shader_tokens.h" 28#include "util/u_blitter.h" 29#include "util/u_format_s3tc.h" 30#include "util/u_simple_shaders.h" 31#include "util/u_upload_mgr.h" 32#include "vl/vl_decoder.h" 33#include "vl/vl_video_buffer.h" 34#include "os/os_time.h" 35 36/* 37 * pipe_context 38 */ 39static struct r600_fence *r600_create_fence(struct r600_context *rctx) 40{ 41 struct r600_screen *rscreen = rctx->screen; 42 struct r600_fence *fence = NULL; 43 44 pipe_mutex_lock(rscreen->fences.mutex); 45 46 if (!rscreen->fences.bo) { 47 /* Create the shared buffer object */ 48 rscreen->fences.bo = (struct r600_resource*) 49 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM, 50 PIPE_USAGE_STAGING, 4096); 51 if (!rscreen->fences.bo) { 52 R600_ERR("r600: failed to create bo for fence objects\n"); 53 goto out; 54 } 55 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf, 56 rctx->cs, 57 PIPE_TRANSFER_READ_WRITE); 58 } 59 60 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) { 61 struct r600_fence *entry; 62 63 /* Try to find a freed fence that has been signalled */ 64 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) { 65 if (rscreen->fences.data[entry->index] != 0) { 66 LIST_DELINIT(&entry->head); 67 fence = entry; 68 break; 69 } 70 } 71 } 72 73 if (!fence) { 74 /* Allocate a new fence */ 75 struct r600_fence_block *block; 76 unsigned index; 77 78 if ((rscreen->fences.next_index + 1) >= 1024) { 79 R600_ERR("r600: too many concurrent fences\n"); 80 goto out; 81 } 82 83 index = rscreen->fences.next_index++; 84 85 if (!(index % FENCE_BLOCK_SIZE)) { 86 /* Allocate a new block */ 87 block = CALLOC_STRUCT(r600_fence_block); 88 if (block == NULL) 89 goto out; 90 91 LIST_ADD(&block->head, &rscreen->fences.blocks); 92 } else { 93 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head); 94 } 95 96 fence = &block->fences[index % FENCE_BLOCK_SIZE]; 97 fence->index = index; 98 } 99 100 pipe_reference_init(&fence->reference, 1); 101 102 rscreen->fences.data[fence->index] = 0; 103 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1); 104 105 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */ 106 fence->sleep_bo = (struct r600_resource*) 107 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM, 108 PIPE_USAGE_STAGING, 1); 109 /* Add the fence as a dummy relocation. */ 110 r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE); 111 112out: 113 pipe_mutex_unlock(rscreen->fences.mutex); 114 return fence; 115} 116 117 118void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 119 unsigned flags) 120{ 121 struct r600_context *rctx = (struct r600_context *)ctx; 122 struct r600_fence **rfence = (struct r600_fence**)fence; 123 struct pipe_query *render_cond = NULL; 124 unsigned render_cond_mode = 0; 125 126 if (rfence) 127 *rfence = r600_create_fence(rctx); 128 129 /* Disable render condition. */ 130 if (rctx->current_render_cond) { 131 render_cond = rctx->current_render_cond; 132 render_cond_mode = rctx->current_render_cond_mode; 133 ctx->render_condition(ctx, NULL, 0); 134 } 135 136 r600_context_flush(rctx, flags); 137 138 /* Re-enable render condition. */ 139 if (render_cond) { 140 ctx->render_condition(ctx, render_cond, render_cond_mode); 141 } 142} 143 144static void r600_flush_from_st(struct pipe_context *ctx, 145 struct pipe_fence_handle **fence) 146{ 147 r600_flush(ctx, fence, 0); 148} 149 150static void r600_flush_from_winsys(void *ctx, unsigned flags) 151{ 152 r600_flush((struct pipe_context*)ctx, NULL, flags); 153} 154 155static void r600_destroy_context(struct pipe_context *context) 156{ 157 struct r600_context *rctx = (struct r600_context *)context; 158 159 if (rctx->dummy_pixel_shader) { 160 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader); 161 } 162 if (rctx->custom_dsa_flush) { 163 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 164 } 165 util_unreference_framebuffer_state(&rctx->framebuffer); 166 167 r600_context_fini(rctx); 168 169 if (rctx->blitter) { 170 util_blitter_destroy(rctx->blitter); 171 } 172 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 173 free(rctx->states[i]); 174 } 175 176 if (rctx->uploader) { 177 u_upload_destroy(rctx->uploader); 178 } 179 util_slab_destroy(&rctx->pool_transfers); 180 181 r600_release_command_buffer(&rctx->start_cs_cmd); 182 183 if (rctx->cs) { 184 rctx->ws->cs_destroy(rctx->cs); 185 } 186 187 FREE(rctx->range); 188 FREE(rctx); 189} 190 191static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 192{ 193 struct r600_context *rctx = CALLOC_STRUCT(r600_context); 194 struct r600_screen* rscreen = (struct r600_screen *)screen; 195 196 if (rctx == NULL) 197 return NULL; 198 199 util_slab_create(&rctx->pool_transfers, 200 sizeof(struct pipe_transfer), 64, 201 UTIL_SLAB_SINGLETHREADED); 202 203 rctx->context.screen = screen; 204 rctx->context.priv = priv; 205 rctx->context.destroy = r600_destroy_context; 206 rctx->context.flush = r600_flush_from_st; 207 208 /* Easy accessing of screen/winsys. */ 209 rctx->screen = rscreen; 210 rctx->ws = rscreen->ws; 211 rctx->family = rscreen->family; 212 rctx->chip_class = rscreen->chip_class; 213 214 LIST_INITHEAD(&rctx->dirty_states); 215 LIST_INITHEAD(&rctx->active_timer_queries); 216 LIST_INITHEAD(&rctx->active_nontimer_queries); 217 LIST_INITHEAD(&rctx->dirty); 218 LIST_INITHEAD(&rctx->enable_list); 219 220 rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range)); 221 if (!rctx->range) 222 goto fail; 223 224 r600_init_blit_functions(rctx); 225 r600_init_query_functions(rctx); 226 r600_init_context_resource_functions(rctx); 227 r600_init_surface_functions(rctx); 228 rctx->context.draw_vbo = r600_draw_vbo; 229 230 rctx->context.create_video_decoder = vl_create_decoder; 231 rctx->context.create_video_buffer = vl_video_buffer_create; 232 233 r600_init_common_atoms(rctx); 234 235 switch (rctx->chip_class) { 236 case R600: 237 case R700: 238 r600_init_state_functions(rctx); 239 r600_init_atom_start_cs(rctx); 240 if (r600_context_init(rctx)) 241 goto fail; 242 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 243 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 || 244 rctx->family == CHIP_RV620 || 245 rctx->family == CHIP_RS780 || 246 rctx->family == CHIP_RS880 || 247 rctx->family == CHIP_RV710); 248 break; 249 case EVERGREEN: 250 case CAYMAN: 251 evergreen_init_state_functions(rctx); 252 evergreen_init_atom_start_cs(rctx); 253 evergreen_init_atom_start_compute_cs(rctx); 254 if (evergreen_context_init(rctx)) 255 goto fail; 256 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 257 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR || 258 rctx->family == CHIP_PALM || 259 rctx->family == CHIP_SUMO || 260 rctx->family == CHIP_SUMO2 || 261 rctx->family == CHIP_CAICOS || 262 rctx->family == CHIP_CAYMAN || 263 rctx->family == CHIP_ARUBA); 264 break; 265 default: 266 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); 267 goto fail; 268 } 269 270 rctx->cs = rctx->ws->cs_create(rctx->ws); 271 rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx); 272 r600_emit_atom(rctx, &rctx->start_cs_cmd.atom); 273 274 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256, 275 PIPE_BIND_INDEX_BUFFER | 276 PIPE_BIND_CONSTANT_BUFFER); 277 if (!rctx->uploader) 278 goto fail; 279 280 rctx->blitter = util_blitter_create(&rctx->context); 281 if (rctx->blitter == NULL) 282 goto fail; 283 284 r600_get_backend_mask(rctx); /* this emits commands and must be last */ 285 286 if (rctx->chip_class == R600) 287 r600_set_max_scissor(rctx); 288 289 rctx->dummy_pixel_shader = 290 util_make_fragment_cloneinput_shader(&rctx->context, 0, 291 TGSI_SEMANTIC_GENERIC, 292 TGSI_INTERPOLATE_CONSTANT); 293 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader); 294 295 return &rctx->context; 296 297fail: 298 r600_destroy_context(&rctx->context); 299 return NULL; 300} 301 302/* 303 * pipe_screen 304 */ 305static const char* r600_get_vendor(struct pipe_screen* pscreen) 306{ 307 return "X.Org"; 308} 309 310static const char *r600_get_family_name(enum radeon_family family) 311{ 312 switch(family) { 313 case CHIP_R600: return "AMD R600"; 314 case CHIP_RV610: return "AMD RV610"; 315 case CHIP_RV630: return "AMD RV630"; 316 case CHIP_RV670: return "AMD RV670"; 317 case CHIP_RV620: return "AMD RV620"; 318 case CHIP_RV635: return "AMD RV635"; 319 case CHIP_RS780: return "AMD RS780"; 320 case CHIP_RS880: return "AMD RS880"; 321 case CHIP_RV770: return "AMD RV770"; 322 case CHIP_RV730: return "AMD RV730"; 323 case CHIP_RV710: return "AMD RV710"; 324 case CHIP_RV740: return "AMD RV740"; 325 case CHIP_CEDAR: return "AMD CEDAR"; 326 case CHIP_REDWOOD: return "AMD REDWOOD"; 327 case CHIP_JUNIPER: return "AMD JUNIPER"; 328 case CHIP_CYPRESS: return "AMD CYPRESS"; 329 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 330 case CHIP_PALM: return "AMD PALM"; 331 case CHIP_SUMO: return "AMD SUMO"; 332 case CHIP_SUMO2: return "AMD SUMO2"; 333 case CHIP_BARTS: return "AMD BARTS"; 334 case CHIP_TURKS: return "AMD TURKS"; 335 case CHIP_CAICOS: return "AMD CAICOS"; 336 case CHIP_CAYMAN: return "AMD CAYMAN"; 337 case CHIP_ARUBA: return "AMD ARUBA"; 338 default: return "AMD unknown"; 339 } 340} 341 342static const char* r600_get_name(struct pipe_screen* pscreen) 343{ 344 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 345 346 return r600_get_family_name(rscreen->family); 347} 348 349static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 350{ 351 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 352 enum radeon_family family = rscreen->family; 353 354 switch (param) { 355 /* Supported features (boolean caps). */ 356 case PIPE_CAP_NPOT_TEXTURES: 357 case PIPE_CAP_TWO_SIDED_STENCIL: 358 case PIPE_CAP_ANISOTROPIC_FILTER: 359 case PIPE_CAP_POINT_SPRITE: 360 case PIPE_CAP_OCCLUSION_QUERY: 361 case PIPE_CAP_TEXTURE_SHADOW_MAP: 362 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 363 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 364 case PIPE_CAP_TEXTURE_SWIZZLE: 365 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 366 case PIPE_CAP_DEPTH_CLIP_DISABLE: 367 case PIPE_CAP_SHADER_STENCIL_EXPORT: 368 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 369 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 370 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 371 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 372 case PIPE_CAP_SM3: 373 case PIPE_CAP_SEAMLESS_CUBE_MAP: 374 case PIPE_CAP_PRIMITIVE_RESTART: 375 case PIPE_CAP_CONDITIONAL_RENDER: 376 case PIPE_CAP_TEXTURE_BARRIER: 377 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 378 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 379 case PIPE_CAP_TGSI_INSTANCEID: 380 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 381 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 382 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 383 case PIPE_CAP_USER_INDEX_BUFFERS: 384 case PIPE_CAP_USER_CONSTANT_BUFFERS: 385 case PIPE_CAP_COMPUTE: 386 case PIPE_CAP_START_INSTANCE: 387 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 388 return 1; 389 390 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 391 return 256; 392 393 case PIPE_CAP_GLSL_FEATURE_LEVEL: 394 return 130; 395 396 /* Supported except the original R600. */ 397 case PIPE_CAP_INDEP_BLEND_ENABLE: 398 case PIPE_CAP_INDEP_BLEND_FUNC: 399 /* R600 doesn't support per-MRT blends */ 400 return family == CHIP_R600 ? 0 : 1; 401 402 /* Supported on Evergreen. */ 403 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 404 return family >= CHIP_CEDAR ? 1 : 0; 405 406 /* Unsupported features. */ 407 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 408 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 409 case PIPE_CAP_SCALED_RESOLVE: 410 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 411 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 412 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 413 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 414 case PIPE_CAP_USER_VERTEX_BUFFERS: 415 case PIPE_CAP_QUERY_TIMESTAMP: 416 return 0; 417 418 /* Stream output. */ 419 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 420 return rscreen->has_streamout ? 4 : 0; 421 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 422 return rscreen->has_streamout ? 1 : 0; 423 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 424 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 425 return 16*4; 426 427 /* Texturing. */ 428 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 429 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 430 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 431 if (family >= CHIP_CEDAR) 432 return 15; 433 else 434 return 14; 435 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 436 return rscreen->info.drm_minor >= 9 ? 437 (family >= CHIP_CEDAR ? 16384 : 8192) : 0; 438 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 439 return 32; 440 441 /* Render targets. */ 442 case PIPE_CAP_MAX_RENDER_TARGETS: 443 /* XXX some r6xx are buggy and can only do 4 */ 444 return 8; 445 446 /* Timer queries, present when the clock frequency is non zero. */ 447 case PIPE_CAP_TIMER_QUERY: 448 return rscreen->info.r600_clock_crystal_freq != 0; 449 450 case PIPE_CAP_MIN_TEXEL_OFFSET: 451 return -8; 452 453 case PIPE_CAP_MAX_TEXEL_OFFSET: 454 return 7; 455 } 456 return 0; 457} 458 459static float r600_get_paramf(struct pipe_screen* pscreen, 460 enum pipe_capf param) 461{ 462 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 463 enum radeon_family family = rscreen->family; 464 465 switch (param) { 466 case PIPE_CAPF_MAX_LINE_WIDTH: 467 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 468 case PIPE_CAPF_MAX_POINT_WIDTH: 469 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 470 if (family >= CHIP_CEDAR) 471 return 16384.0f; 472 else 473 return 8192.0f; 474 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 475 return 16.0f; 476 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 477 return 16.0f; 478 case PIPE_CAPF_GUARD_BAND_LEFT: 479 case PIPE_CAPF_GUARD_BAND_TOP: 480 case PIPE_CAPF_GUARD_BAND_RIGHT: 481 case PIPE_CAPF_GUARD_BAND_BOTTOM: 482 return 0.0f; 483 } 484 return 0.0f; 485} 486 487static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 488{ 489 switch(shader) 490 { 491 case PIPE_SHADER_FRAGMENT: 492 case PIPE_SHADER_VERTEX: 493 case PIPE_SHADER_COMPUTE: 494 break; 495 case PIPE_SHADER_GEOMETRY: 496 /* XXX: support and enable geometry programs */ 497 return 0; 498 default: 499 /* XXX: support tessellation on Evergreen */ 500 return 0; 501 } 502 503 /* XXX: all these should be fixed, since r600 surely supports much more! */ 504 switch (param) { 505 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 506 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 507 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 508 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 509 return 16384; 510 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 511 return 8; /* XXX */ 512 case PIPE_SHADER_CAP_MAX_INPUTS: 513 if(shader == PIPE_SHADER_FRAGMENT) 514 return 34; 515 else 516 return 32; 517 case PIPE_SHADER_CAP_MAX_TEMPS: 518 return 256; /* Max native temporaries. */ 519 case PIPE_SHADER_CAP_MAX_ADDRS: 520 /* XXX Isn't this equal to TEMPS? */ 521 return 1; /* Max native address registers */ 522 case PIPE_SHADER_CAP_MAX_CONSTS: 523 return R600_MAX_CONST_BUFFER_SIZE; 524 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 525 return R600_MAX_CONST_BUFFERS-1; 526 case PIPE_SHADER_CAP_MAX_PREDS: 527 return 0; /* nothing uses this */ 528 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 529 return 1; 530 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 531 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 532 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 533 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 534 return 1; 535 case PIPE_SHADER_CAP_SUBROUTINES: 536 return 0; 537 case PIPE_SHADER_CAP_INTEGERS: 538 return 1; 539 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 540 return 16; 541 case PIPE_SHADER_CAP_PREFERRED_IR: 542 if (shader == PIPE_SHADER_COMPUTE) { 543 return PIPE_SHADER_IR_LLVM; 544 } else { 545 return PIPE_SHADER_IR_TGSI; 546 } 547 } 548 return 0; 549} 550 551static int r600_get_video_param(struct pipe_screen *screen, 552 enum pipe_video_profile profile, 553 enum pipe_video_cap param) 554{ 555 switch (param) { 556 case PIPE_VIDEO_CAP_SUPPORTED: 557 return vl_profile_supported(screen, profile); 558 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 559 return 1; 560 case PIPE_VIDEO_CAP_MAX_WIDTH: 561 case PIPE_VIDEO_CAP_MAX_HEIGHT: 562 return vl_video_buffer_max_size(screen); 563 case PIPE_VIDEO_CAP_PREFERED_FORMAT: 564 return PIPE_FORMAT_NV12; 565 case PIPE_VIDEO_CAP_PREFERS_INTERLACED: 566 return false; 567 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: 568 return false; 569 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: 570 return true; 571 default: 572 return 0; 573 } 574} 575 576static int r600_get_compute_param(struct pipe_screen *screen, 577 enum pipe_compute_cap param, 578 void *ret) 579{ 580 //TODO: select these params by asic 581 switch (param) { 582 case PIPE_COMPUTE_CAP_IR_TARGET: 583 if (ret) { 584 strcpy(ret, "r600--"); 585 } 586 return 7 * sizeof(char); 587 588 case PIPE_COMPUTE_CAP_GRID_DIMENSION: 589 if (ret) { 590 uint64_t * grid_dimension = ret; 591 grid_dimension[0] = 3; 592 } 593 return 1 * sizeof(uint64_t); 594 595 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: 596 if (ret) { 597 uint64_t * grid_size = ret; 598 grid_size[0] = 65535; 599 grid_size[1] = 65535; 600 grid_size[2] = 1; 601 } 602 return 3 * sizeof(uint64_t) ; 603 604 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: 605 if (ret) { 606 uint64_t * block_size = ret; 607 block_size[0] = 256; 608 block_size[1] = 256; 609 block_size[2] = 256; 610 } 611 return 3 * sizeof(uint64_t); 612 613 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: 614 if (ret) { 615 uint64_t * max_threads_per_block = ret; 616 *max_threads_per_block = 256; 617 } 618 return sizeof(uint64_t); 619 620 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: 621 if (ret) { 622 uint64_t * max_global_size = ret; 623 /* XXX: This is 64kb for now until we get the 624 * compute memory pool working correctly. 625 */ 626 *max_global_size = 1024 * 16 * 4; 627 } 628 return sizeof(uint64_t); 629 630 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: 631 if (ret) { 632 uint64_t * max_input_size = ret; 633 *max_input_size = 1024; 634 } 635 return sizeof(uint64_t); 636 637 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: 638 if (ret) { 639 uint64_t * max_local_size = ret; 640 /* XXX: This is what the proprietary driver reports, we 641 * may want to use a different value. */ 642 *max_local_size = 32768; 643 } 644 return sizeof(uint64_t); 645 646 default: 647 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param); 648 return 0; 649 } 650} 651 652static void r600_destroy_screen(struct pipe_screen* pscreen) 653{ 654 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 655 656 if (rscreen == NULL) 657 return; 658 659 if (rscreen->global_pool) { 660 compute_memory_pool_delete(rscreen->global_pool); 661 } 662 663 if (rscreen->fences.bo) { 664 struct r600_fence_block *entry, *tmp; 665 666 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) { 667 LIST_DEL(&entry->head); 668 FREE(entry); 669 } 670 671 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf); 672 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL); 673 } 674 pipe_mutex_destroy(rscreen->fences.mutex); 675 676 rscreen->ws->destroy(rscreen->ws); 677 FREE(rscreen); 678} 679 680static void r600_fence_reference(struct pipe_screen *pscreen, 681 struct pipe_fence_handle **ptr, 682 struct pipe_fence_handle *fence) 683{ 684 struct r600_fence **oldf = (struct r600_fence**)ptr; 685 struct r600_fence *newf = (struct r600_fence*)fence; 686 687 if (pipe_reference(&(*oldf)->reference, &newf->reference)) { 688 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 689 pipe_mutex_lock(rscreen->fences.mutex); 690 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL); 691 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool); 692 pipe_mutex_unlock(rscreen->fences.mutex); 693 } 694 695 *ptr = fence; 696} 697 698static boolean r600_fence_signalled(struct pipe_screen *pscreen, 699 struct pipe_fence_handle *fence) 700{ 701 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 702 struct r600_fence *rfence = (struct r600_fence*)fence; 703 704 return rscreen->fences.data[rfence->index]; 705} 706 707static boolean r600_fence_finish(struct pipe_screen *pscreen, 708 struct pipe_fence_handle *fence, 709 uint64_t timeout) 710{ 711 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 712 struct r600_fence *rfence = (struct r600_fence*)fence; 713 int64_t start_time = 0; 714 unsigned spins = 0; 715 716 if (timeout != PIPE_TIMEOUT_INFINITE) { 717 start_time = os_time_get(); 718 719 /* Convert to microseconds. */ 720 timeout /= 1000; 721 } 722 723 while (rscreen->fences.data[rfence->index] == 0) { 724 /* Special-case infinite timeout - wait for the dummy BO to become idle */ 725 if (timeout == PIPE_TIMEOUT_INFINITE) { 726 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE); 727 break; 728 } 729 730 /* The dummy BO will be busy until the CS including the fence has completed, or 731 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */ 732 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE)) 733 break; 734 735 if (++spins % 256) 736 continue; 737#ifdef PIPE_OS_UNIX 738 sched_yield(); 739#else 740 os_time_sleep(10); 741#endif 742 if (timeout != PIPE_TIMEOUT_INFINITE && 743 os_time_get() - start_time >= timeout) { 744 break; 745 } 746 } 747 748 return rscreen->fences.data[rfence->index] != 0; 749} 750 751static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 752{ 753 switch ((tiling_config & 0xe) >> 1) { 754 case 0: 755 rscreen->tiling_info.num_channels = 1; 756 break; 757 case 1: 758 rscreen->tiling_info.num_channels = 2; 759 break; 760 case 2: 761 rscreen->tiling_info.num_channels = 4; 762 break; 763 case 3: 764 rscreen->tiling_info.num_channels = 8; 765 break; 766 default: 767 return -EINVAL; 768 } 769 770 switch ((tiling_config & 0x30) >> 4) { 771 case 0: 772 rscreen->tiling_info.num_banks = 4; 773 break; 774 case 1: 775 rscreen->tiling_info.num_banks = 8; 776 break; 777 default: 778 return -EINVAL; 779 780 } 781 switch ((tiling_config & 0xc0) >> 6) { 782 case 0: 783 rscreen->tiling_info.group_bytes = 256; 784 break; 785 case 1: 786 rscreen->tiling_info.group_bytes = 512; 787 break; 788 default: 789 return -EINVAL; 790 } 791 return 0; 792} 793 794static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 795{ 796 switch (tiling_config & 0xf) { 797 case 0: 798 rscreen->tiling_info.num_channels = 1; 799 break; 800 case 1: 801 rscreen->tiling_info.num_channels = 2; 802 break; 803 case 2: 804 rscreen->tiling_info.num_channels = 4; 805 break; 806 case 3: 807 rscreen->tiling_info.num_channels = 8; 808 break; 809 default: 810 return -EINVAL; 811 } 812 813 switch ((tiling_config & 0xf0) >> 4) { 814 case 0: 815 rscreen->tiling_info.num_banks = 4; 816 break; 817 case 1: 818 rscreen->tiling_info.num_banks = 8; 819 break; 820 case 2: 821 rscreen->tiling_info.num_banks = 16; 822 break; 823 default: 824 return -EINVAL; 825 } 826 827 switch ((tiling_config & 0xf00) >> 8) { 828 case 0: 829 rscreen->tiling_info.group_bytes = 256; 830 break; 831 case 1: 832 rscreen->tiling_info.group_bytes = 512; 833 break; 834 default: 835 return -EINVAL; 836 } 837 return 0; 838} 839 840static int r600_init_tiling(struct r600_screen *rscreen) 841{ 842 uint32_t tiling_config = rscreen->info.r600_tiling_config; 843 844 /* set default group bytes, overridden by tiling info ioctl */ 845 if (rscreen->chip_class <= R700) { 846 rscreen->tiling_info.group_bytes = 256; 847 } else { 848 rscreen->tiling_info.group_bytes = 512; 849 } 850 851 if (!tiling_config) 852 return 0; 853 854 if (rscreen->chip_class <= R700) { 855 return r600_interpret_tiling(rscreen, tiling_config); 856 } else { 857 return evergreen_interpret_tiling(rscreen, tiling_config); 858 } 859} 860 861static unsigned radeon_family_from_device(unsigned device) 862{ 863 switch (device) { 864#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family; 865#include "pci_ids/r600_pci_ids.h" 866#undef CHIPSET 867 default: 868 return CHIP_UNKNOWN; 869 } 870} 871 872struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) 873{ 874 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen); 875 876 if (rscreen == NULL) { 877 return NULL; 878 } 879 880 rscreen->ws = ws; 881 ws->query_info(ws, &rscreen->info); 882 883 rscreen->family = radeon_family_from_device(rscreen->info.pci_id); 884 if (rscreen->family == CHIP_UNKNOWN) { 885 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); 886 FREE(rscreen); 887 return NULL; 888 } 889 890 /* setup class */ 891 if (rscreen->family >= CHIP_CAYMAN) { 892 rscreen->chip_class = CAYMAN; 893 } else if (rscreen->family >= CHIP_CEDAR) { 894 rscreen->chip_class = EVERGREEN; 895 } else if (rscreen->family >= CHIP_RV770) { 896 rscreen->chip_class = R700; 897 } else { 898 rscreen->chip_class = R600; 899 } 900 901 /* Figure out streamout kernel support. */ 902 switch (rscreen->chip_class) { 903 case R600: 904 case EVERGREEN: 905 rscreen->has_streamout = rscreen->info.drm_minor >= 13; 906 break; 907 case R700: 908 rscreen->has_streamout = rscreen->info.drm_minor >= 17; 909 break; 910 /* TODO: Cayman */ 911 default: 912 rscreen->has_streamout = debug_get_bool_option("R600_STREAMOUT", FALSE); 913 } 914 915 if (r600_init_tiling(rscreen)) { 916 FREE(rscreen); 917 return NULL; 918 } 919 920 rscreen->screen.destroy = r600_destroy_screen; 921 rscreen->screen.get_name = r600_get_name; 922 rscreen->screen.get_vendor = r600_get_vendor; 923 rscreen->screen.get_param = r600_get_param; 924 rscreen->screen.get_shader_param = r600_get_shader_param; 925 rscreen->screen.get_paramf = r600_get_paramf; 926 rscreen->screen.get_video_param = r600_get_video_param; 927 rscreen->screen.get_compute_param = r600_get_compute_param; 928 929 if (rscreen->chip_class >= EVERGREEN) { 930 rscreen->screen.is_format_supported = evergreen_is_format_supported; 931 } else { 932 rscreen->screen.is_format_supported = r600_is_format_supported; 933 } 934 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; 935 rscreen->screen.context_create = r600_create_context; 936 rscreen->screen.fence_reference = r600_fence_reference; 937 rscreen->screen.fence_signalled = r600_fence_signalled; 938 rscreen->screen.fence_finish = r600_fence_finish; 939 r600_init_screen_resource_functions(&rscreen->screen); 940 941 util_format_s3tc_init(); 942 943 rscreen->fences.bo = NULL; 944 rscreen->fences.data = NULL; 945 rscreen->fences.next_index = 0; 946 LIST_INITHEAD(&rscreen->fences.pool); 947 LIST_INITHEAD(&rscreen->fences.blocks); 948 pipe_mutex_init(rscreen->fences.mutex); 949 950 rscreen->use_surface_alloc = debug_get_bool_option("R600_SURF", TRUE); 951 952 rscreen->global_pool = compute_memory_pool_new(rscreen); 953 954 return &rscreen->screen; 955} 956