r600_pipe.c revision b87bc2eb44cd605f2992335b5649ca907ba0c55d
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include <stdio.h> 24#include <errno.h> 25#include "pipe/p_defines.h" 26#include "pipe/p_state.h" 27#include "pipe/p_context.h" 28#include "tgsi/tgsi_scan.h" 29#include "tgsi/tgsi_parse.h" 30#include "tgsi/tgsi_util.h" 31#include "util/u_blitter.h" 32#include "util/u_double_list.h" 33#include "util/u_format.h" 34#include "util/u_format_s3tc.h" 35#include "util/u_transfer.h" 36#include "util/u_surface.h" 37#include "util/u_pack_color.h" 38#include "util/u_memory.h" 39#include "util/u_inlines.h" 40#include "util/u_upload_mgr.h" 41#include "vl/vl_decoder.h" 42#include "vl/vl_video_buffer.h" 43#include "os/os_time.h" 44#include "pipebuffer/pb_buffer.h" 45#include "r600.h" 46#include "r600d.h" 47#include "r600_resource.h" 48#include "r600_shader.h" 49#include "r600_pipe.h" 50 51/* 52 * pipe_context 53 */ 54static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx) 55{ 56 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 57 struct r600_fence *fence = NULL; 58 59 if (!ctx->fences.bo) { 60 /* Create the shared buffer object */ 61 ctx->fences.bo = r600_bo(ctx->radeon, 4096, 0, 0, 0); 62 if (!ctx->fences.bo) { 63 R600_ERR("r600: failed to create bo for fence objects\n"); 64 return NULL; 65 } 66 ctx->fences.data = r600_bo_map(ctx->radeon, ctx->fences.bo, rctx->ctx.cs, 67 PIPE_TRANSFER_UNSYNCHRONIZED | PIPE_TRANSFER_WRITE); 68 } 69 70 if (!LIST_IS_EMPTY(&ctx->fences.pool)) { 71 struct r600_fence *entry; 72 73 /* Try to find a freed fence that has been signalled */ 74 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) { 75 if (ctx->fences.data[entry->index] != 0) { 76 LIST_DELINIT(&entry->head); 77 fence = entry; 78 break; 79 } 80 } 81 } 82 83 if (!fence) { 84 /* Allocate a new fence */ 85 struct r600_fence_block *block; 86 unsigned index; 87 88 if ((ctx->fences.next_index + 1) >= 1024) { 89 R600_ERR("r600: too many concurrent fences\n"); 90 return NULL; 91 } 92 93 index = ctx->fences.next_index++; 94 95 if (!(index % FENCE_BLOCK_SIZE)) { 96 /* Allocate a new block */ 97 block = CALLOC_STRUCT(r600_fence_block); 98 if (block == NULL) 99 return NULL; 100 101 LIST_ADD(&block->head, &ctx->fences.blocks); 102 } else { 103 block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head); 104 } 105 106 fence = &block->fences[index % FENCE_BLOCK_SIZE]; 107 fence->ctx = ctx; 108 fence->index = index; 109 } 110 111 pipe_reference_init(&fence->reference, 1); 112 113 ctx->fences.data[fence->index] = 0; 114 r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1); 115 return fence; 116} 117 118 119void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 120 unsigned flags) 121{ 122 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 123 struct r600_fence **rfence = (struct r600_fence**)fence; 124 125 if (rfence) 126 *rfence = r600_create_fence(rctx); 127 128 r600_context_flush(&rctx->ctx, flags); 129} 130 131static void r600_flush_from_st(struct pipe_context *ctx, 132 struct pipe_fence_handle **fence) 133{ 134 r600_flush(ctx, fence, 0); 135} 136 137static void r600_flush_from_winsys(void *ctx, unsigned flags) 138{ 139 r600_flush((struct pipe_context*)ctx, NULL, flags); 140} 141 142static void r600_update_num_contexts(struct r600_screen *rscreen, int diff) 143{ 144 pipe_mutex_lock(rscreen->mutex_num_contexts); 145 if (diff > 0) { 146 rscreen->num_contexts++; 147 148 if (rscreen->num_contexts > 1) 149 util_slab_set_thread_safety(&rscreen->pool_buffers, 150 UTIL_SLAB_MULTITHREADED); 151 } else { 152 rscreen->num_contexts--; 153 154 if (rscreen->num_contexts <= 1) 155 util_slab_set_thread_safety(&rscreen->pool_buffers, 156 UTIL_SLAB_SINGLETHREADED); 157 } 158 pipe_mutex_unlock(rscreen->mutex_num_contexts); 159} 160 161static void r600_destroy_context(struct pipe_context *context) 162{ 163 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context; 164 165 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 166 util_unreference_framebuffer_state(&rctx->framebuffer); 167 168 r600_context_fini(&rctx->ctx); 169 170 util_blitter_destroy(rctx->blitter); 171 172 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 173 free(rctx->states[i]); 174 } 175 176 u_vbuf_mgr_destroy(rctx->vbuf_mgr); 177 util_slab_destroy(&rctx->pool_transfers); 178 179 if (rctx->fences.bo) { 180 struct r600_fence_block *entry, *tmp; 181 182 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) { 183 LIST_DEL(&entry->head); 184 FREE(entry); 185 } 186 187 r600_bo_unmap(rctx->radeon, rctx->fences.bo); 188 r600_bo_reference(&rctx->fences.bo, NULL); 189 } 190 191 r600_update_num_contexts(rctx->screen, -1); 192 193 FREE(rctx); 194} 195 196static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 197{ 198 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context); 199 struct r600_screen* rscreen = (struct r600_screen *)screen; 200 201 if (rctx == NULL) 202 return NULL; 203 204 r600_update_num_contexts(rscreen, 1); 205 206 rctx->context.winsys = rscreen->screen.winsys; 207 rctx->context.screen = screen; 208 rctx->context.priv = priv; 209 rctx->context.destroy = r600_destroy_context; 210 rctx->context.flush = r600_flush_from_st; 211 212 /* Easy accessing of screen/winsys. */ 213 rctx->screen = rscreen; 214 rctx->radeon = rscreen->radeon; 215 rctx->family = r600_get_family(rctx->radeon); 216 rctx->chip_class = r600_get_family_class(rctx->radeon); 217 218 rctx->fences.bo = NULL; 219 rctx->fences.data = NULL; 220 rctx->fences.next_index = 0; 221 LIST_INITHEAD(&rctx->fences.pool); 222 LIST_INITHEAD(&rctx->fences.blocks); 223 224 r600_init_blit_functions(rctx); 225 r600_init_query_functions(rctx); 226 r600_init_context_resource_functions(rctx); 227 r600_init_surface_functions(rctx); 228 rctx->context.draw_vbo = r600_draw_vbo; 229 230 rctx->context.create_video_decoder = vl_create_decoder; 231 rctx->context.create_video_buffer = vl_video_buffer_create; 232 233 switch (rctx->chip_class) { 234 case R600: 235 case R700: 236 r600_init_state_functions(rctx); 237 if (r600_context_init(&rctx->ctx, rctx->radeon)) { 238 r600_destroy_context(&rctx->context); 239 return NULL; 240 } 241 r600_init_config(rctx); 242 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 243 break; 244 case EVERGREEN: 245 case CAYMAN: 246 evergreen_init_state_functions(rctx); 247 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) { 248 r600_destroy_context(&rctx->context); 249 return NULL; 250 } 251 evergreen_init_config(rctx); 252 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 253 break; 254 default: 255 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); 256 r600_destroy_context(&rctx->context); 257 return NULL; 258 } 259 260 rctx->screen->ws->cs_set_flush_callback(rctx->ctx.cs, r600_flush_from_winsys, rctx); 261 262 util_slab_create(&rctx->pool_transfers, 263 sizeof(struct pipe_transfer), 64, 264 UTIL_SLAB_SINGLETHREADED); 265 266 rctx->vbuf_mgr = u_vbuf_mgr_create(&rctx->context, 1024 * 1024, 256, 267 PIPE_BIND_VERTEX_BUFFER | 268 PIPE_BIND_INDEX_BUFFER | 269 PIPE_BIND_CONSTANT_BUFFER, 270 U_VERTEX_FETCH_DWORD_ALIGNED); 271 if (!rctx->vbuf_mgr) { 272 r600_destroy_context(&rctx->context); 273 return NULL; 274 } 275 rctx->vbuf_mgr->caps.format_fixed32 = 0; 276 277 rctx->blitter = util_blitter_create(&rctx->context); 278 if (rctx->blitter == NULL) { 279 r600_destroy_context(&rctx->context); 280 return NULL; 281 } 282 283 return &rctx->context; 284} 285 286/* 287 * pipe_screen 288 */ 289static const char* r600_get_vendor(struct pipe_screen* pscreen) 290{ 291 return "X.Org"; 292} 293 294static const char *r600_get_family_name(enum radeon_family family) 295{ 296 switch(family) { 297 case CHIP_R600: return "AMD R600"; 298 case CHIP_RV610: return "AMD RV610"; 299 case CHIP_RV630: return "AMD RV630"; 300 case CHIP_RV670: return "AMD RV670"; 301 case CHIP_RV620: return "AMD RV620"; 302 case CHIP_RV635: return "AMD RV635"; 303 case CHIP_RS780: return "AMD RS780"; 304 case CHIP_RS880: return "AMD RS880"; 305 case CHIP_RV770: return "AMD RV770"; 306 case CHIP_RV730: return "AMD RV730"; 307 case CHIP_RV710: return "AMD RV710"; 308 case CHIP_RV740: return "AMD RV740"; 309 case CHIP_CEDAR: return "AMD CEDAR"; 310 case CHIP_REDWOOD: return "AMD REDWOOD"; 311 case CHIP_JUNIPER: return "AMD JUNIPER"; 312 case CHIP_CYPRESS: return "AMD CYPRESS"; 313 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 314 case CHIP_PALM: return "AMD PALM"; 315 case CHIP_SUMO: return "AMD SUMO"; 316 case CHIP_SUMO2: return "AMD SUMO2"; 317 case CHIP_BARTS: return "AMD BARTS"; 318 case CHIP_TURKS: return "AMD TURKS"; 319 case CHIP_CAICOS: return "AMD CAICOS"; 320 case CHIP_CAYMAN: return "AMD CAYMAN"; 321 default: return "AMD unknown"; 322 } 323} 324 325static const char* r600_get_name(struct pipe_screen* pscreen) 326{ 327 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 328 enum radeon_family family = r600_get_family(rscreen->radeon); 329 330 return r600_get_family_name(family); 331} 332 333static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 334{ 335 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 336 enum radeon_family family = r600_get_family(rscreen->radeon); 337 338 switch (param) { 339 /* Supported features (boolean caps). */ 340 case PIPE_CAP_NPOT_TEXTURES: 341 case PIPE_CAP_TWO_SIDED_STENCIL: 342 case PIPE_CAP_GLSL: 343 case PIPE_CAP_DUAL_SOURCE_BLEND: 344 case PIPE_CAP_ANISOTROPIC_FILTER: 345 case PIPE_CAP_POINT_SPRITE: 346 case PIPE_CAP_OCCLUSION_QUERY: 347 case PIPE_CAP_TEXTURE_SHADOW_MAP: 348 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 349 case PIPE_CAP_TEXTURE_MIRROR_REPEAT: 350 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 351 case PIPE_CAP_TEXTURE_SWIZZLE: 352 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 353 case PIPE_CAP_DEPTH_CLAMP: 354 case PIPE_CAP_SHADER_STENCIL_EXPORT: 355 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 356 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 357 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 358 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 359 case PIPE_CAP_SM3: 360 case PIPE_CAP_SEAMLESS_CUBE_MAP: 361 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL: 362 case PIPE_CAP_PRIMITIVE_RESTART: 363 return 1; 364 365 /* Supported except the original R600. */ 366 case PIPE_CAP_INDEP_BLEND_ENABLE: 367 case PIPE_CAP_INDEP_BLEND_FUNC: 368 /* R600 doesn't support per-MRT blends */ 369 return family == CHIP_R600 ? 0 : 1; 370 371 /* Supported on Evergreen. */ 372 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 373 return family >= CHIP_CEDAR ? 1 : 0; 374 375 /* Unsupported features. */ 376 case PIPE_CAP_STREAM_OUTPUT: 377 case PIPE_CAP_TGSI_INSTANCEID: 378 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 379 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 380 return 0; 381 382 /* Texturing. */ 383 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 384 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 385 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 386 if (family >= CHIP_CEDAR) 387 return 15; 388 else 389 return 14; 390 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 391 return rscreen->info.drm_minor >= 9 ? 392 (family >= CHIP_CEDAR ? 16384 : 8192) : 0; 393 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS: 394 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS: 395 return 16; 396 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 397 return 32; 398 399 /* Render targets. */ 400 case PIPE_CAP_MAX_RENDER_TARGETS: 401 /* FIXME some r6xx are buggy and can only do 4 */ 402 return 8; 403 404 /* Timer queries, present when the clock frequency is non zero. */ 405 case PIPE_CAP_TIMER_QUERY: 406 return rscreen->info.r600_clock_crystal_freq != 0; 407 408 case PIPE_CAP_MIN_TEXEL_OFFSET: 409 return -8; 410 411 case PIPE_CAP_MAX_TEXEL_OFFSET: 412 return 7; 413 414 default: 415 R600_ERR("r600: unknown param %d\n", param); 416 return 0; 417 } 418} 419 420static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param) 421{ 422 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 423 enum radeon_family family = r600_get_family(rscreen->radeon); 424 425 switch (param) { 426 case PIPE_CAP_MAX_LINE_WIDTH: 427 case PIPE_CAP_MAX_LINE_WIDTH_AA: 428 case PIPE_CAP_MAX_POINT_WIDTH: 429 case PIPE_CAP_MAX_POINT_WIDTH_AA: 430 if (family >= CHIP_CEDAR) 431 return 16384.0f; 432 else 433 return 8192.0f; 434 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: 435 return 16.0f; 436 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: 437 return 16.0f; 438 default: 439 R600_ERR("r600: unsupported paramf %d\n", param); 440 return 0.0f; 441 } 442} 443 444static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 445{ 446 switch(shader) 447 { 448 case PIPE_SHADER_FRAGMENT: 449 case PIPE_SHADER_VERTEX: 450 break; 451 case PIPE_SHADER_GEOMETRY: 452 /* TODO: support and enable geometry programs */ 453 return 0; 454 default: 455 /* TODO: support tessellation on Evergreen */ 456 return 0; 457 } 458 459 /* TODO: all these should be fixed, since r600 surely supports much more! */ 460 switch (param) { 461 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 462 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 463 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 464 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 465 return 16384; 466 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 467 return 8; /* FIXME */ 468 case PIPE_SHADER_CAP_MAX_INPUTS: 469 if(shader == PIPE_SHADER_FRAGMENT) 470 return 34; 471 else 472 return 32; 473 case PIPE_SHADER_CAP_MAX_TEMPS: 474 return 256; /* Max native temporaries. */ 475 case PIPE_SHADER_CAP_MAX_ADDRS: 476 /* FIXME Isn't this equal to TEMPS? */ 477 return 1; /* Max native address registers */ 478 case PIPE_SHADER_CAP_MAX_CONSTS: 479 return R600_MAX_CONST_BUFFER_SIZE; 480 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 481 return R600_MAX_CONST_BUFFERS; 482 case PIPE_SHADER_CAP_MAX_PREDS: 483 return 0; /* FIXME */ 484 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 485 return 1; 486 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 487 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 488 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 489 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 490 return 1; 491 case PIPE_SHADER_CAP_SUBROUTINES: 492 return 0; 493 case PIPE_SHADER_CAP_INTEGERS: 494 return 0; 495 default: 496 return 0; 497 } 498} 499 500static int r600_get_video_param(struct pipe_screen *screen, 501 enum pipe_video_profile profile, 502 enum pipe_video_cap param) 503{ 504 switch (param) { 505 case PIPE_VIDEO_CAP_SUPPORTED: 506 return vl_profile_supported(screen, profile); 507 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 508 return 1; 509 case PIPE_VIDEO_CAP_MAX_WIDTH: 510 case PIPE_VIDEO_CAP_MAX_HEIGHT: 511 return vl_video_buffer_max_size(screen); 512 case PIPE_VIDEO_CAP_NUM_BUFFERS_DESIRED: 513 return vl_num_buffers_desired(screen, profile); 514 default: 515 return 0; 516 } 517} 518 519static void r600_destroy_screen(struct pipe_screen* pscreen) 520{ 521 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 522 523 if (rscreen == NULL) 524 return; 525 526 radeon_destroy(rscreen->radeon); 527 rscreen->ws->destroy(rscreen->ws); 528 529 util_slab_destroy(&rscreen->pool_buffers); 530 pipe_mutex_destroy(rscreen->mutex_num_contexts); 531 FREE(rscreen); 532} 533 534static void r600_fence_reference(struct pipe_screen *pscreen, 535 struct pipe_fence_handle **ptr, 536 struct pipe_fence_handle *fence) 537{ 538 struct r600_fence **oldf = (struct r600_fence**)ptr; 539 struct r600_fence *newf = (struct r600_fence*)fence; 540 541 if (pipe_reference(&(*oldf)->reference, &newf->reference)) { 542 struct r600_pipe_context *ctx = (*oldf)->ctx; 543 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool); 544 } 545 546 *ptr = fence; 547} 548 549static boolean r600_fence_signalled(struct pipe_screen *pscreen, 550 struct pipe_fence_handle *fence) 551{ 552 struct r600_fence *rfence = (struct r600_fence*)fence; 553 struct r600_pipe_context *ctx = rfence->ctx; 554 555 return ctx->fences.data[rfence->index]; 556} 557 558static boolean r600_fence_finish(struct pipe_screen *pscreen, 559 struct pipe_fence_handle *fence, 560 uint64_t timeout) 561{ 562 struct r600_fence *rfence = (struct r600_fence*)fence; 563 struct r600_pipe_context *ctx = rfence->ctx; 564 int64_t start_time = 0; 565 unsigned spins = 0; 566 567 if (timeout != PIPE_TIMEOUT_INFINITE) { 568 start_time = os_time_get(); 569 570 /* Convert to microseconds. */ 571 timeout /= 1000; 572 } 573 574 while (ctx->fences.data[rfence->index] == 0) { 575 if (++spins % 256) 576 continue; 577#ifdef PIPE_OS_UNIX 578 sched_yield(); 579#else 580 os_time_sleep(10); 581#endif 582 if (timeout != PIPE_TIMEOUT_INFINITE && 583 os_time_get() - start_time >= timeout) { 584 return FALSE; 585 } 586 } 587 588 return TRUE; 589} 590 591static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 592{ 593 switch ((tiling_config & 0xe) >> 1) { 594 case 0: 595 rscreen->tiling_info.num_channels = 1; 596 break; 597 case 1: 598 rscreen->tiling_info.num_channels = 2; 599 break; 600 case 2: 601 rscreen->tiling_info.num_channels = 4; 602 break; 603 case 3: 604 rscreen->tiling_info.num_channels = 8; 605 break; 606 default: 607 return -EINVAL; 608 } 609 610 switch ((tiling_config & 0x30) >> 4) { 611 case 0: 612 rscreen->tiling_info.num_banks = 4; 613 break; 614 case 1: 615 rscreen->tiling_info.num_banks = 8; 616 break; 617 default: 618 return -EINVAL; 619 620 } 621 switch ((tiling_config & 0xc0) >> 6) { 622 case 0: 623 rscreen->tiling_info.group_bytes = 256; 624 break; 625 case 1: 626 rscreen->tiling_info.group_bytes = 512; 627 break; 628 default: 629 return -EINVAL; 630 } 631 return 0; 632} 633 634static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 635{ 636 switch (tiling_config & 0xf) { 637 case 0: 638 rscreen->tiling_info.num_channels = 1; 639 break; 640 case 1: 641 rscreen->tiling_info.num_channels = 2; 642 break; 643 case 2: 644 rscreen->tiling_info.num_channels = 4; 645 break; 646 case 3: 647 rscreen->tiling_info.num_channels = 8; 648 break; 649 default: 650 return -EINVAL; 651 } 652 653 switch ((tiling_config & 0xf0) >> 4) { 654 case 0: 655 rscreen->tiling_info.num_banks = 4; 656 break; 657 case 1: 658 rscreen->tiling_info.num_banks = 8; 659 break; 660 case 2: 661 rscreen->tiling_info.num_banks = 16; 662 break; 663 default: 664 return -EINVAL; 665 } 666 667 switch ((tiling_config & 0xf00) >> 8) { 668 case 0: 669 rscreen->tiling_info.group_bytes = 256; 670 break; 671 case 1: 672 rscreen->tiling_info.group_bytes = 512; 673 break; 674 default: 675 return -EINVAL; 676 } 677 return 0; 678} 679 680static int r600_init_tiling(struct r600_screen *rscreen) 681{ 682 uint32_t tiling_config = rscreen->info.r600_tiling_config; 683 684 /* set default group bytes, overridden by tiling info ioctl */ 685 if (r600_get_family_class(rscreen->radeon) <= R700) { 686 rscreen->tiling_info.group_bytes = 256; 687 } else { 688 rscreen->tiling_info.group_bytes = 512; 689 } 690 691 if (!tiling_config) 692 return 0; 693 694 if (r600_get_family_class(rscreen->radeon) <= R700) { 695 return r600_interpret_tiling(rscreen, tiling_config); 696 } else { 697 return evergreen_interpret_tiling(rscreen, tiling_config); 698 } 699} 700 701struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) 702{ 703 struct r600_screen *rscreen; 704 struct radeon *radeon = radeon_create(ws); 705 if (!radeon) { 706 return NULL; 707 } 708 709 rscreen = CALLOC_STRUCT(r600_screen); 710 if (rscreen == NULL) { 711 radeon_destroy(radeon); 712 return NULL; 713 } 714 715 rscreen->ws = ws; 716 rscreen->radeon = radeon; 717 ws->query_info(ws, &rscreen->info); 718 719 if (r600_init_tiling(rscreen)) { 720 radeon_destroy(radeon); 721 FREE(rscreen); 722 return NULL; 723 } 724 725 rscreen->screen.winsys = (struct pipe_winsys*)ws; 726 rscreen->screen.destroy = r600_destroy_screen; 727 rscreen->screen.get_name = r600_get_name; 728 rscreen->screen.get_vendor = r600_get_vendor; 729 rscreen->screen.get_param = r600_get_param; 730 rscreen->screen.get_shader_param = r600_get_shader_param; 731 rscreen->screen.get_paramf = r600_get_paramf; 732 rscreen->screen.get_video_param = r600_get_video_param; 733 if (r600_get_family_class(radeon) >= EVERGREEN) { 734 rscreen->screen.is_format_supported = evergreen_is_format_supported; 735 } else { 736 rscreen->screen.is_format_supported = r600_is_format_supported; 737 } 738 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; 739 rscreen->screen.context_create = r600_create_context; 740 rscreen->screen.fence_reference = r600_fence_reference; 741 rscreen->screen.fence_signalled = r600_fence_signalled; 742 rscreen->screen.fence_finish = r600_fence_finish; 743 r600_init_screen_resource_functions(&rscreen->screen); 744 745 util_format_s3tc_init(); 746 747 util_slab_create(&rscreen->pool_buffers, 748 sizeof(struct r600_resource_buffer), 64, 749 UTIL_SLAB_SINGLETHREADED); 750 751 pipe_mutex_init(rscreen->mutex_num_contexts); 752 753 return &rscreen->screen; 754} 755