r600_pipe.c revision e2809849ecac69615ece294a55ee355afaac33d3
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include <stdio.h> 24#include <errno.h> 25#include "pipe/p_defines.h" 26#include "pipe/p_state.h" 27#include "pipe/p_context.h" 28#include "tgsi/tgsi_scan.h" 29#include "tgsi/tgsi_parse.h" 30#include "tgsi/tgsi_util.h" 31#include "util/u_blitter.h" 32#include "util/u_double_list.h" 33#include "util/u_format.h" 34#include "util/u_format_s3tc.h" 35#include "util/u_transfer.h" 36#include "util/u_surface.h" 37#include "util/u_pack_color.h" 38#include "util/u_memory.h" 39#include "util/u_inlines.h" 40#include "util/u_upload_mgr.h" 41#include "vl/vl_decoder.h" 42#include "vl/vl_video_buffer.h" 43#include "os/os_time.h" 44#include "pipebuffer/pb_buffer.h" 45#include "r600.h" 46#include "r600d.h" 47#include "r600_resource.h" 48#include "r600_shader.h" 49#include "r600_pipe.h" 50#include "r600_hw_context_priv.h" 51 52/* 53 * pipe_context 54 */ 55static struct r600_fence *r600_create_fence(struct r600_context *rctx) 56{ 57 struct r600_screen *rscreen = rctx->screen; 58 struct r600_fence *fence = NULL; 59 60 pipe_mutex_lock(rscreen->fences.mutex); 61 62 if (!rscreen->fences.bo) { 63 /* Create the shared buffer object */ 64 rscreen->fences.bo = (struct r600_resource*) 65 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM, 66 PIPE_USAGE_STAGING, 4096); 67 if (!rscreen->fences.bo) { 68 R600_ERR("r600: failed to create bo for fence objects\n"); 69 goto out; 70 } 71 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->buf, 72 rctx->cs, 73 PIPE_TRANSFER_READ_WRITE); 74 } 75 76 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) { 77 struct r600_fence *entry; 78 79 /* Try to find a freed fence that has been signalled */ 80 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) { 81 if (rscreen->fences.data[entry->index] != 0) { 82 LIST_DELINIT(&entry->head); 83 fence = entry; 84 break; 85 } 86 } 87 } 88 89 if (!fence) { 90 /* Allocate a new fence */ 91 struct r600_fence_block *block; 92 unsigned index; 93 94 if ((rscreen->fences.next_index + 1) >= 1024) { 95 R600_ERR("r600: too many concurrent fences\n"); 96 goto out; 97 } 98 99 index = rscreen->fences.next_index++; 100 101 if (!(index % FENCE_BLOCK_SIZE)) { 102 /* Allocate a new block */ 103 block = CALLOC_STRUCT(r600_fence_block); 104 if (block == NULL) 105 goto out; 106 107 LIST_ADD(&block->head, &rscreen->fences.blocks); 108 } else { 109 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head); 110 } 111 112 fence = &block->fences[index % FENCE_BLOCK_SIZE]; 113 fence->index = index; 114 } 115 116 pipe_reference_init(&fence->reference, 1); 117 118 rscreen->fences.data[fence->index] = 0; 119 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1); 120 121 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */ 122 fence->sleep_bo = (struct r600_resource*) 123 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM, 124 PIPE_USAGE_STAGING, 1); 125 /* Add the fence as a dummy relocation. */ 126 r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE); 127 128out: 129 pipe_mutex_unlock(rscreen->fences.mutex); 130 return fence; 131} 132 133 134void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 135 unsigned flags) 136{ 137 struct r600_context *rctx = (struct r600_context *)ctx; 138 struct r600_fence **rfence = (struct r600_fence**)fence; 139 struct pipe_query *render_cond = NULL; 140 unsigned render_cond_mode = 0; 141 142 if (rfence) 143 *rfence = r600_create_fence(rctx); 144 145 /* Disable render condition. */ 146 if (rctx->current_render_cond) { 147 render_cond = rctx->current_render_cond; 148 render_cond_mode = rctx->current_render_cond_mode; 149 ctx->render_condition(ctx, NULL, 0); 150 } 151 152 r600_context_flush(rctx, flags); 153 154 /* Re-enable render condition. */ 155 if (render_cond) { 156 ctx->render_condition(ctx, render_cond, render_cond_mode); 157 } 158} 159 160static void r600_flush_from_st(struct pipe_context *ctx, 161 struct pipe_fence_handle **fence) 162{ 163 r600_flush(ctx, fence, 0); 164} 165 166static void r600_flush_from_winsys(void *ctx, unsigned flags) 167{ 168 r600_flush((struct pipe_context*)ctx, NULL, flags); 169} 170 171static void r600_update_num_contexts(struct r600_screen *rscreen, int diff) 172{ 173 pipe_mutex_lock(rscreen->mutex_num_contexts); 174 if (diff > 0) { 175 rscreen->num_contexts++; 176 177 if (rscreen->num_contexts > 1) 178 util_slab_set_thread_safety(&rscreen->pool_buffers, 179 UTIL_SLAB_MULTITHREADED); 180 } else { 181 rscreen->num_contexts--; 182 183 if (rscreen->num_contexts <= 1) 184 util_slab_set_thread_safety(&rscreen->pool_buffers, 185 UTIL_SLAB_SINGLETHREADED); 186 } 187 pipe_mutex_unlock(rscreen->mutex_num_contexts); 188} 189 190static void r600_destroy_context(struct pipe_context *context) 191{ 192 struct r600_context *rctx = (struct r600_context *)context; 193 194 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 195 util_unreference_framebuffer_state(&rctx->framebuffer); 196 197 r600_context_fini(rctx); 198 199 util_blitter_destroy(rctx->blitter); 200 201 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 202 free(rctx->states[i]); 203 } 204 205 u_vbuf_destroy(rctx->vbuf_mgr); 206 util_slab_destroy(&rctx->pool_transfers); 207 208 r600_update_num_contexts(rctx->screen, -1); 209 210 r600_release_command_buffer(&rctx->atom_start_cs); 211 FREE(rctx); 212} 213 214static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 215{ 216 struct r600_context *rctx = CALLOC_STRUCT(r600_context); 217 struct r600_screen* rscreen = (struct r600_screen *)screen; 218 219 if (rctx == NULL) 220 return NULL; 221 222 r600_update_num_contexts(rscreen, 1); 223 224 rctx->context.screen = screen; 225 rctx->context.priv = priv; 226 rctx->context.destroy = r600_destroy_context; 227 rctx->context.flush = r600_flush_from_st; 228 229 /* Easy accessing of screen/winsys. */ 230 rctx->screen = rscreen; 231 rctx->ws = rscreen->ws; 232 rctx->family = rscreen->family; 233 rctx->chip_class = rscreen->chip_class; 234 235 LIST_INITHEAD(&rctx->dirty_states); 236 237 r600_init_blit_functions(rctx); 238 r600_init_query_functions(rctx); 239 r600_init_context_resource_functions(rctx); 240 r600_init_surface_functions(rctx); 241 rctx->context.draw_vbo = r600_draw_vbo; 242 243 rctx->context.create_video_decoder = vl_create_decoder; 244 rctx->context.create_video_buffer = vl_video_buffer_create; 245 246 r600_init_common_atoms(rctx); 247 248 switch (rctx->chip_class) { 249 case R600: 250 case R700: 251 r600_init_state_functions(rctx); 252 r600_init_atom_start_cs(rctx); 253 if (r600_context_init(rctx)) { 254 r600_destroy_context(&rctx->context); 255 return NULL; 256 } 257 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 258 break; 259 case EVERGREEN: 260 case CAYMAN: 261 evergreen_init_state_functions(rctx); 262 evergreen_init_atom_start_cs(rctx); 263 if (evergreen_context_init(rctx)) { 264 r600_destroy_context(&rctx->context); 265 return NULL; 266 } 267 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 268 break; 269 default: 270 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); 271 r600_destroy_context(&rctx->context); 272 return NULL; 273 } 274 275 rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx); 276 277 util_slab_create(&rctx->pool_transfers, 278 sizeof(struct pipe_transfer), 64, 279 UTIL_SLAB_SINGLETHREADED); 280 281 rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256, 282 PIPE_BIND_VERTEX_BUFFER | 283 PIPE_BIND_INDEX_BUFFER | 284 PIPE_BIND_CONSTANT_BUFFER, 285 U_VERTEX_FETCH_DWORD_ALIGNED); 286 if (!rctx->vbuf_mgr) { 287 r600_destroy_context(&rctx->context); 288 return NULL; 289 } 290 rctx->vbuf_mgr->caps.format_fixed32 = 0; 291 292 rctx->blitter = util_blitter_create(&rctx->context); 293 if (rctx->blitter == NULL) { 294 r600_destroy_context(&rctx->context); 295 return NULL; 296 } 297 298 r600_get_backend_mask(rctx); /* this emits commands and must be last */ 299 300 return &rctx->context; 301} 302 303/* 304 * pipe_screen 305 */ 306static const char* r600_get_vendor(struct pipe_screen* pscreen) 307{ 308 return "X.Org"; 309} 310 311static const char *r600_get_family_name(enum radeon_family family) 312{ 313 switch(family) { 314 case CHIP_R600: return "AMD R600"; 315 case CHIP_RV610: return "AMD RV610"; 316 case CHIP_RV630: return "AMD RV630"; 317 case CHIP_RV670: return "AMD RV670"; 318 case CHIP_RV620: return "AMD RV620"; 319 case CHIP_RV635: return "AMD RV635"; 320 case CHIP_RS780: return "AMD RS780"; 321 case CHIP_RS880: return "AMD RS880"; 322 case CHIP_RV770: return "AMD RV770"; 323 case CHIP_RV730: return "AMD RV730"; 324 case CHIP_RV710: return "AMD RV710"; 325 case CHIP_RV740: return "AMD RV740"; 326 case CHIP_CEDAR: return "AMD CEDAR"; 327 case CHIP_REDWOOD: return "AMD REDWOOD"; 328 case CHIP_JUNIPER: return "AMD JUNIPER"; 329 case CHIP_CYPRESS: return "AMD CYPRESS"; 330 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 331 case CHIP_PALM: return "AMD PALM"; 332 case CHIP_SUMO: return "AMD SUMO"; 333 case CHIP_SUMO2: return "AMD SUMO2"; 334 case CHIP_BARTS: return "AMD BARTS"; 335 case CHIP_TURKS: return "AMD TURKS"; 336 case CHIP_CAICOS: return "AMD CAICOS"; 337 case CHIP_CAYMAN: return "AMD CAYMAN"; 338 default: return "AMD unknown"; 339 } 340} 341 342static const char* r600_get_name(struct pipe_screen* pscreen) 343{ 344 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 345 346 return r600_get_family_name(rscreen->family); 347} 348 349static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 350{ 351 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 352 enum radeon_family family = rscreen->family; 353 354 switch (param) { 355 /* Supported features (boolean caps). */ 356 case PIPE_CAP_NPOT_TEXTURES: 357 case PIPE_CAP_TWO_SIDED_STENCIL: 358 case PIPE_CAP_DUAL_SOURCE_BLEND: 359 case PIPE_CAP_ANISOTROPIC_FILTER: 360 case PIPE_CAP_POINT_SPRITE: 361 case PIPE_CAP_OCCLUSION_QUERY: 362 case PIPE_CAP_TEXTURE_SHADOW_MAP: 363 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 364 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 365 case PIPE_CAP_TEXTURE_SWIZZLE: 366 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 367 case PIPE_CAP_DEPTH_CLIP_DISABLE: 368 case PIPE_CAP_SHADER_STENCIL_EXPORT: 369 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 370 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 371 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 372 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 373 case PIPE_CAP_SM3: 374 case PIPE_CAP_SEAMLESS_CUBE_MAP: 375 case PIPE_CAP_PRIMITIVE_RESTART: 376 case PIPE_CAP_CONDITIONAL_RENDER: 377 case PIPE_CAP_TEXTURE_BARRIER: 378 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 379 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 380 return 1; 381 382 case PIPE_CAP_GLSL_FEATURE_LEVEL: 383 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120; 384 385 /* Supported except the original R600. */ 386 case PIPE_CAP_INDEP_BLEND_ENABLE: 387 case PIPE_CAP_INDEP_BLEND_FUNC: 388 /* R600 doesn't support per-MRT blends */ 389 return family == CHIP_R600 ? 0 : 1; 390 391 /* Supported on Evergreen. */ 392 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 393 return family >= CHIP_CEDAR ? 1 : 0; 394 395 /* Unsupported features. */ 396 case PIPE_CAP_TGSI_INSTANCEID: 397 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 398 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 399 case PIPE_CAP_SCALED_RESOLVE: 400 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 401 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 402 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 403 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 404 return 0; 405 406 /* Stream output. */ 407 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 408 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0; 409 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 410 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0; 411 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 412 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 413 return 16*4; 414 415 /* Texturing. */ 416 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 417 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 418 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 419 if (family >= CHIP_CEDAR) 420 return 15; 421 else 422 return 14; 423 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 424 return rscreen->info.drm_minor >= 9 ? 425 (family >= CHIP_CEDAR ? 16384 : 8192) : 0; 426 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 427 return 32; 428 429 /* Render targets. */ 430 case PIPE_CAP_MAX_RENDER_TARGETS: 431 /* FIXME some r6xx are buggy and can only do 4 */ 432 return 8; 433 434 /* Timer queries, present when the clock frequency is non zero. */ 435 case PIPE_CAP_TIMER_QUERY: 436 return rscreen->info.r600_clock_crystal_freq != 0; 437 438 case PIPE_CAP_MIN_TEXEL_OFFSET: 439 return -8; 440 441 case PIPE_CAP_MAX_TEXEL_OFFSET: 442 return 7; 443 } 444 return 0; 445} 446 447static float r600_get_paramf(struct pipe_screen* pscreen, 448 enum pipe_capf param) 449{ 450 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 451 enum radeon_family family = rscreen->family; 452 453 switch (param) { 454 case PIPE_CAPF_MAX_LINE_WIDTH: 455 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 456 case PIPE_CAPF_MAX_POINT_WIDTH: 457 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 458 if (family >= CHIP_CEDAR) 459 return 16384.0f; 460 else 461 return 8192.0f; 462 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 463 return 16.0f; 464 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 465 return 16.0f; 466 case PIPE_CAPF_GUARD_BAND_LEFT: 467 case PIPE_CAPF_GUARD_BAND_TOP: 468 case PIPE_CAPF_GUARD_BAND_RIGHT: 469 case PIPE_CAPF_GUARD_BAND_BOTTOM: 470 return 0.0f; 471 } 472 return 0.0f; 473} 474 475static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 476{ 477 switch(shader) 478 { 479 case PIPE_SHADER_FRAGMENT: 480 case PIPE_SHADER_VERTEX: 481 break; 482 case PIPE_SHADER_GEOMETRY: 483 /* TODO: support and enable geometry programs */ 484 return 0; 485 default: 486 /* TODO: support tessellation on Evergreen */ 487 return 0; 488 } 489 490 /* TODO: all these should be fixed, since r600 surely supports much more! */ 491 switch (param) { 492 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 493 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 494 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 495 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 496 return 16384; 497 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 498 return 8; /* FIXME */ 499 case PIPE_SHADER_CAP_MAX_INPUTS: 500 if(shader == PIPE_SHADER_FRAGMENT) 501 return 34; 502 else 503 return 32; 504 case PIPE_SHADER_CAP_MAX_TEMPS: 505 return 256; /* Max native temporaries. */ 506 case PIPE_SHADER_CAP_MAX_ADDRS: 507 /* FIXME Isn't this equal to TEMPS? */ 508 return 1; /* Max native address registers */ 509 case PIPE_SHADER_CAP_MAX_CONSTS: 510 return R600_MAX_CONST_BUFFER_SIZE; 511 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 512 return R600_MAX_CONST_BUFFERS-1; 513 case PIPE_SHADER_CAP_MAX_PREDS: 514 return 0; /* FIXME */ 515 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 516 return 1; 517 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 518 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 519 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 520 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 521 return 1; 522 case PIPE_SHADER_CAP_SUBROUTINES: 523 return 0; 524 case PIPE_SHADER_CAP_INTEGERS: 525 return 0; 526 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 527 return 16; 528 case PIPE_SHADER_CAP_OUTPUT_READ: 529 return 1; 530 } 531 return 0; 532} 533 534static int r600_get_video_param(struct pipe_screen *screen, 535 enum pipe_video_profile profile, 536 enum pipe_video_cap param) 537{ 538 switch (param) { 539 case PIPE_VIDEO_CAP_SUPPORTED: 540 return vl_profile_supported(screen, profile); 541 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 542 return 1; 543 case PIPE_VIDEO_CAP_MAX_WIDTH: 544 case PIPE_VIDEO_CAP_MAX_HEIGHT: 545 return vl_video_buffer_max_size(screen); 546 case PIPE_VIDEO_CAP_PREFERED_FORMAT: 547 return PIPE_FORMAT_NV12; 548 case PIPE_VIDEO_CAP_PREFERS_INTERLACED: 549 return false; 550 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: 551 return false; 552 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: 553 return true; 554 default: 555 return 0; 556 } 557} 558 559static void r600_destroy_screen(struct pipe_screen* pscreen) 560{ 561 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 562 563 if (rscreen == NULL) 564 return; 565 566 if (rscreen->fences.bo) { 567 struct r600_fence_block *entry, *tmp; 568 569 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) { 570 LIST_DEL(&entry->head); 571 FREE(entry); 572 } 573 574 rscreen->ws->buffer_unmap(rscreen->fences.bo->buf); 575 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL); 576 } 577 pipe_mutex_destroy(rscreen->fences.mutex); 578 579 rscreen->ws->destroy(rscreen->ws); 580 581 util_slab_destroy(&rscreen->pool_buffers); 582 pipe_mutex_destroy(rscreen->mutex_num_contexts); 583 FREE(rscreen); 584} 585 586static void r600_fence_reference(struct pipe_screen *pscreen, 587 struct pipe_fence_handle **ptr, 588 struct pipe_fence_handle *fence) 589{ 590 struct r600_fence **oldf = (struct r600_fence**)ptr; 591 struct r600_fence *newf = (struct r600_fence*)fence; 592 593 if (pipe_reference(&(*oldf)->reference, &newf->reference)) { 594 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 595 pipe_mutex_lock(rscreen->fences.mutex); 596 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL); 597 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool); 598 pipe_mutex_unlock(rscreen->fences.mutex); 599 } 600 601 *ptr = fence; 602} 603 604static boolean r600_fence_signalled(struct pipe_screen *pscreen, 605 struct pipe_fence_handle *fence) 606{ 607 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 608 struct r600_fence *rfence = (struct r600_fence*)fence; 609 610 return rscreen->fences.data[rfence->index]; 611} 612 613static boolean r600_fence_finish(struct pipe_screen *pscreen, 614 struct pipe_fence_handle *fence, 615 uint64_t timeout) 616{ 617 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 618 struct r600_fence *rfence = (struct r600_fence*)fence; 619 int64_t start_time = 0; 620 unsigned spins = 0; 621 622 if (timeout != PIPE_TIMEOUT_INFINITE) { 623 start_time = os_time_get(); 624 625 /* Convert to microseconds. */ 626 timeout /= 1000; 627 } 628 629 while (rscreen->fences.data[rfence->index] == 0) { 630 /* Special-case infinite timeout - wait for the dummy BO to become idle */ 631 if (timeout == PIPE_TIMEOUT_INFINITE) { 632 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE); 633 break; 634 } 635 636 /* The dummy BO will be busy until the CS including the fence has completed, or 637 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */ 638 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE)) 639 break; 640 641 if (++spins % 256) 642 continue; 643#ifdef PIPE_OS_UNIX 644 sched_yield(); 645#else 646 os_time_sleep(10); 647#endif 648 if (timeout != PIPE_TIMEOUT_INFINITE && 649 os_time_get() - start_time >= timeout) { 650 break; 651 } 652 } 653 654 return rscreen->fences.data[rfence->index] != 0; 655} 656 657static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 658{ 659 switch ((tiling_config & 0xe) >> 1) { 660 case 0: 661 rscreen->tiling_info.num_channels = 1; 662 break; 663 case 1: 664 rscreen->tiling_info.num_channels = 2; 665 break; 666 case 2: 667 rscreen->tiling_info.num_channels = 4; 668 break; 669 case 3: 670 rscreen->tiling_info.num_channels = 8; 671 break; 672 default: 673 return -EINVAL; 674 } 675 676 switch ((tiling_config & 0x30) >> 4) { 677 case 0: 678 rscreen->tiling_info.num_banks = 4; 679 break; 680 case 1: 681 rscreen->tiling_info.num_banks = 8; 682 break; 683 default: 684 return -EINVAL; 685 686 } 687 switch ((tiling_config & 0xc0) >> 6) { 688 case 0: 689 rscreen->tiling_info.group_bytes = 256; 690 break; 691 case 1: 692 rscreen->tiling_info.group_bytes = 512; 693 break; 694 default: 695 return -EINVAL; 696 } 697 return 0; 698} 699 700static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 701{ 702 switch (tiling_config & 0xf) { 703 case 0: 704 rscreen->tiling_info.num_channels = 1; 705 break; 706 case 1: 707 rscreen->tiling_info.num_channels = 2; 708 break; 709 case 2: 710 rscreen->tiling_info.num_channels = 4; 711 break; 712 case 3: 713 rscreen->tiling_info.num_channels = 8; 714 break; 715 default: 716 return -EINVAL; 717 } 718 719 switch ((tiling_config & 0xf0) >> 4) { 720 case 0: 721 rscreen->tiling_info.num_banks = 4; 722 break; 723 case 1: 724 rscreen->tiling_info.num_banks = 8; 725 break; 726 case 2: 727 rscreen->tiling_info.num_banks = 16; 728 break; 729 default: 730 return -EINVAL; 731 } 732 733 switch ((tiling_config & 0xf00) >> 8) { 734 case 0: 735 rscreen->tiling_info.group_bytes = 256; 736 break; 737 case 1: 738 rscreen->tiling_info.group_bytes = 512; 739 break; 740 default: 741 return -EINVAL; 742 } 743 return 0; 744} 745 746static int r600_init_tiling(struct r600_screen *rscreen) 747{ 748 uint32_t tiling_config = rscreen->info.r600_tiling_config; 749 750 /* set default group bytes, overridden by tiling info ioctl */ 751 if (rscreen->chip_class <= R700) { 752 rscreen->tiling_info.group_bytes = 256; 753 } else { 754 rscreen->tiling_info.group_bytes = 512; 755 } 756 757 if (!tiling_config) 758 return 0; 759 760 if (rscreen->chip_class <= R700) { 761 return r600_interpret_tiling(rscreen, tiling_config); 762 } else { 763 return evergreen_interpret_tiling(rscreen, tiling_config); 764 } 765} 766 767static unsigned radeon_family_from_device(unsigned device) 768{ 769 switch (device) { 770#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family; 771#include "pci_ids/r600_pci_ids.h" 772#undef CHIPSET 773 default: 774 return CHIP_UNKNOWN; 775 } 776} 777 778struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) 779{ 780 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen); 781 if (rscreen == NULL) { 782 return NULL; 783 } 784 785 rscreen->ws = ws; 786 ws->query_info(ws, &rscreen->info); 787 788 rscreen->family = radeon_family_from_device(rscreen->info.pci_id); 789 if (rscreen->family == CHIP_UNKNOWN) { 790 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); 791 FREE(rscreen); 792 return NULL; 793 } 794 795 /* setup class */ 796 if (rscreen->family == CHIP_CAYMAN) { 797 rscreen->chip_class = CAYMAN; 798 } else if (rscreen->family >= CHIP_CEDAR) { 799 rscreen->chip_class = EVERGREEN; 800 } else if (rscreen->family >= CHIP_RV770) { 801 rscreen->chip_class = R700; 802 } else { 803 rscreen->chip_class = R600; 804 } 805 806 if (r600_init_tiling(rscreen)) { 807 FREE(rscreen); 808 return NULL; 809 } 810 811 rscreen->screen.destroy = r600_destroy_screen; 812 rscreen->screen.get_name = r600_get_name; 813 rscreen->screen.get_vendor = r600_get_vendor; 814 rscreen->screen.get_param = r600_get_param; 815 rscreen->screen.get_shader_param = r600_get_shader_param; 816 rscreen->screen.get_paramf = r600_get_paramf; 817 rscreen->screen.get_video_param = r600_get_video_param; 818 if (rscreen->chip_class >= EVERGREEN) { 819 rscreen->screen.is_format_supported = evergreen_is_format_supported; 820 } else { 821 rscreen->screen.is_format_supported = r600_is_format_supported; 822 } 823 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; 824 rscreen->screen.context_create = r600_create_context; 825 rscreen->screen.fence_reference = r600_fence_reference; 826 rscreen->screen.fence_signalled = r600_fence_signalled; 827 rscreen->screen.fence_finish = r600_fence_finish; 828 r600_init_screen_resource_functions(&rscreen->screen); 829 830 util_format_s3tc_init(); 831 832 util_slab_create(&rscreen->pool_buffers, 833 sizeof(struct r600_resource), 64, 834 UTIL_SLAB_SINGLETHREADED); 835 836 pipe_mutex_init(rscreen->mutex_num_contexts); 837 838 rscreen->fences.bo = NULL; 839 rscreen->fences.data = NULL; 840 rscreen->fences.next_index = 0; 841 LIST_INITHEAD(&rscreen->fences.pool); 842 LIST_INITHEAD(&rscreen->fences.blocks); 843 pipe_mutex_init(rscreen->fences.mutex); 844 845 return &rscreen->screen; 846} 847