r600_pipe.c revision e4340c1908a6a3b09e1a15d5195f6da7d00494d0
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include <stdio.h> 24#include <errno.h> 25#include "pipe/p_defines.h" 26#include "pipe/p_state.h" 27#include "pipe/p_context.h" 28#include "tgsi/tgsi_scan.h" 29#include "tgsi/tgsi_parse.h" 30#include "tgsi/tgsi_util.h" 31#include "util/u_blitter.h" 32#include "util/u_double_list.h" 33#include "util/u_format.h" 34#include "util/u_format_s3tc.h" 35#include "util/u_transfer.h" 36#include "util/u_surface.h" 37#include "util/u_pack_color.h" 38#include "util/u_memory.h" 39#include "util/u_inlines.h" 40#include "util/u_upload_mgr.h" 41#include "vl/vl_decoder.h" 42#include "vl/vl_video_buffer.h" 43#include "os/os_time.h" 44#include "pipebuffer/pb_buffer.h" 45#include "r600.h" 46#include "r600d.h" 47#include "r600_resource.h" 48#include "r600_shader.h" 49#include "r600_pipe.h" 50 51/* 52 * pipe_context 53 */ 54static struct r600_fence *r600_create_fence(struct r600_context *rctx) 55{ 56 struct r600_screen *rscreen = rctx->screen; 57 struct r600_fence *fence = NULL; 58 59 pipe_mutex_lock(rscreen->fences.mutex); 60 61 if (!rscreen->fences.bo) { 62 /* Create the shared buffer object */ 63 rscreen->fences.bo = (struct r600_resource*) 64 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM, 65 PIPE_USAGE_STAGING, 4096); 66 if (!rscreen->fences.bo) { 67 R600_ERR("r600: failed to create bo for fence objects\n"); 68 goto out; 69 } 70 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->buf, 71 rctx->cs, 72 PIPE_TRANSFER_READ_WRITE); 73 } 74 75 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) { 76 struct r600_fence *entry; 77 78 /* Try to find a freed fence that has been signalled */ 79 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) { 80 if (rscreen->fences.data[entry->index] != 0) { 81 LIST_DELINIT(&entry->head); 82 fence = entry; 83 break; 84 } 85 } 86 } 87 88 if (!fence) { 89 /* Allocate a new fence */ 90 struct r600_fence_block *block; 91 unsigned index; 92 93 if ((rscreen->fences.next_index + 1) >= 1024) { 94 R600_ERR("r600: too many concurrent fences\n"); 95 goto out; 96 } 97 98 index = rscreen->fences.next_index++; 99 100 if (!(index % FENCE_BLOCK_SIZE)) { 101 /* Allocate a new block */ 102 block = CALLOC_STRUCT(r600_fence_block); 103 if (block == NULL) 104 goto out; 105 106 LIST_ADD(&block->head, &rscreen->fences.blocks); 107 } else { 108 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head); 109 } 110 111 fence = &block->fences[index % FENCE_BLOCK_SIZE]; 112 fence->index = index; 113 } 114 115 pipe_reference_init(&fence->reference, 1); 116 117 rscreen->fences.data[fence->index] = 0; 118 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1); 119out: 120 pipe_mutex_unlock(rscreen->fences.mutex); 121 return fence; 122} 123 124 125void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 126 unsigned flags) 127{ 128 struct r600_context *rctx = (struct r600_context *)ctx; 129 struct r600_fence **rfence = (struct r600_fence**)fence; 130 struct pipe_query *render_cond = NULL; 131 unsigned render_cond_mode = 0; 132 133 if (rfence) 134 *rfence = r600_create_fence(rctx); 135 136 /* Disable render condition. */ 137 if (rctx->current_render_cond) { 138 render_cond = rctx->current_render_cond; 139 render_cond_mode = rctx->current_render_cond_mode; 140 ctx->render_condition(ctx, NULL, 0); 141 } 142 143 r600_context_flush(rctx, flags); 144 145 /* Re-enable render condition. */ 146 if (render_cond) { 147 ctx->render_condition(ctx, render_cond, render_cond_mode); 148 } 149} 150 151static void r600_flush_from_st(struct pipe_context *ctx, 152 struct pipe_fence_handle **fence) 153{ 154 r600_flush(ctx, fence, 0); 155} 156 157static void r600_flush_from_winsys(void *ctx, unsigned flags) 158{ 159 r600_flush((struct pipe_context*)ctx, NULL, flags); 160} 161 162static void r600_update_num_contexts(struct r600_screen *rscreen, int diff) 163{ 164 pipe_mutex_lock(rscreen->mutex_num_contexts); 165 if (diff > 0) { 166 rscreen->num_contexts++; 167 168 if (rscreen->num_contexts > 1) 169 util_slab_set_thread_safety(&rscreen->pool_buffers, 170 UTIL_SLAB_MULTITHREADED); 171 } else { 172 rscreen->num_contexts--; 173 174 if (rscreen->num_contexts <= 1) 175 util_slab_set_thread_safety(&rscreen->pool_buffers, 176 UTIL_SLAB_SINGLETHREADED); 177 } 178 pipe_mutex_unlock(rscreen->mutex_num_contexts); 179} 180 181static void r600_destroy_context(struct pipe_context *context) 182{ 183 struct r600_context *rctx = (struct r600_context *)context; 184 185 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 186 util_unreference_framebuffer_state(&rctx->framebuffer); 187 188 r600_context_fini(rctx); 189 190 util_blitter_destroy(rctx->blitter); 191 192 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 193 free(rctx->states[i]); 194 } 195 196 u_vbuf_destroy(rctx->vbuf_mgr); 197 util_slab_destroy(&rctx->pool_transfers); 198 199 r600_update_num_contexts(rctx->screen, -1); 200 201 FREE(rctx); 202} 203 204static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 205{ 206 struct r600_context *rctx = CALLOC_STRUCT(r600_context); 207 struct r600_screen* rscreen = (struct r600_screen *)screen; 208 209 if (rctx == NULL) 210 return NULL; 211 212 r600_update_num_contexts(rscreen, 1); 213 214 rctx->context.winsys = rscreen->screen.winsys; 215 rctx->context.screen = screen; 216 rctx->context.priv = priv; 217 rctx->context.destroy = r600_destroy_context; 218 rctx->context.flush = r600_flush_from_st; 219 220 /* Easy accessing of screen/winsys. */ 221 rctx->screen = rscreen; 222 rctx->ws = rscreen->ws; 223 rctx->family = rscreen->family; 224 rctx->chip_class = rscreen->chip_class; 225 226 r600_init_blit_functions(rctx); 227 r600_init_query_functions(rctx); 228 r600_init_context_resource_functions(rctx); 229 r600_init_surface_functions(rctx); 230 rctx->context.draw_vbo = r600_draw_vbo; 231 232 rctx->context.create_video_decoder = vl_create_decoder; 233 rctx->context.create_video_buffer = vl_video_buffer_create; 234 235 switch (rctx->chip_class) { 236 case R600: 237 case R700: 238 r600_init_state_functions(rctx); 239 if (r600_context_init(rctx, rctx->screen)) { 240 r600_destroy_context(&rctx->context); 241 return NULL; 242 } 243 r600_init_config(rctx); 244 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 245 break; 246 case EVERGREEN: 247 case CAYMAN: 248 evergreen_init_state_functions(rctx); 249 if (evergreen_context_init(rctx, rctx->screen)) { 250 r600_destroy_context(&rctx->context); 251 return NULL; 252 } 253 evergreen_init_config(rctx); 254 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 255 break; 256 default: 257 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); 258 r600_destroy_context(&rctx->context); 259 return NULL; 260 } 261 262 rctx->pipe = &rctx->context; 263 rctx->flush = r600_flush_from_winsys; 264 rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx); 265 266 util_slab_create(&rctx->pool_transfers, 267 sizeof(struct pipe_transfer), 64, 268 UTIL_SLAB_SINGLETHREADED); 269 270 rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256, 271 PIPE_BIND_VERTEX_BUFFER | 272 PIPE_BIND_INDEX_BUFFER | 273 PIPE_BIND_CONSTANT_BUFFER, 274 U_VERTEX_FETCH_DWORD_ALIGNED); 275 if (!rctx->vbuf_mgr) { 276 r600_destroy_context(&rctx->context); 277 return NULL; 278 } 279 rctx->vbuf_mgr->caps.format_fixed32 = 0; 280 281 rctx->blitter = util_blitter_create(&rctx->context); 282 if (rctx->blitter == NULL) { 283 r600_destroy_context(&rctx->context); 284 return NULL; 285 } 286 287 r600_get_backend_mask(rctx); /* this emits commands and must be last */ 288 289 return &rctx->context; 290} 291 292/* 293 * pipe_screen 294 */ 295static const char* r600_get_vendor(struct pipe_screen* pscreen) 296{ 297 return "X.Org"; 298} 299 300static const char *r600_get_family_name(enum radeon_family family) 301{ 302 switch(family) { 303 case CHIP_R600: return "AMD R600"; 304 case CHIP_RV610: return "AMD RV610"; 305 case CHIP_RV630: return "AMD RV630"; 306 case CHIP_RV670: return "AMD RV670"; 307 case CHIP_RV620: return "AMD RV620"; 308 case CHIP_RV635: return "AMD RV635"; 309 case CHIP_RS780: return "AMD RS780"; 310 case CHIP_RS880: return "AMD RS880"; 311 case CHIP_RV770: return "AMD RV770"; 312 case CHIP_RV730: return "AMD RV730"; 313 case CHIP_RV710: return "AMD RV710"; 314 case CHIP_RV740: return "AMD RV740"; 315 case CHIP_CEDAR: return "AMD CEDAR"; 316 case CHIP_REDWOOD: return "AMD REDWOOD"; 317 case CHIP_JUNIPER: return "AMD JUNIPER"; 318 case CHIP_CYPRESS: return "AMD CYPRESS"; 319 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 320 case CHIP_PALM: return "AMD PALM"; 321 case CHIP_SUMO: return "AMD SUMO"; 322 case CHIP_SUMO2: return "AMD SUMO2"; 323 case CHIP_BARTS: return "AMD BARTS"; 324 case CHIP_TURKS: return "AMD TURKS"; 325 case CHIP_CAICOS: return "AMD CAICOS"; 326 case CHIP_CAYMAN: return "AMD CAYMAN"; 327 default: return "AMD unknown"; 328 } 329} 330 331static const char* r600_get_name(struct pipe_screen* pscreen) 332{ 333 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 334 335 return r600_get_family_name(rscreen->family); 336} 337 338static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 339{ 340 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 341 enum radeon_family family = rscreen->family; 342 343 switch (param) { 344 /* Supported features (boolean caps). */ 345 case PIPE_CAP_NPOT_TEXTURES: 346 case PIPE_CAP_TWO_SIDED_STENCIL: 347 case PIPE_CAP_DUAL_SOURCE_BLEND: 348 case PIPE_CAP_ANISOTROPIC_FILTER: 349 case PIPE_CAP_POINT_SPRITE: 350 case PIPE_CAP_OCCLUSION_QUERY: 351 case PIPE_CAP_TEXTURE_SHADOW_MAP: 352 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 353 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 354 case PIPE_CAP_TEXTURE_SWIZZLE: 355 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 356 case PIPE_CAP_DEPTH_CLIP_DISABLE: 357 case PIPE_CAP_SHADER_STENCIL_EXPORT: 358 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 359 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 360 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 361 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 362 case PIPE_CAP_SM3: 363 case PIPE_CAP_SEAMLESS_CUBE_MAP: 364 case PIPE_CAP_PRIMITIVE_RESTART: 365 case PIPE_CAP_CONDITIONAL_RENDER: 366 case PIPE_CAP_TEXTURE_BARRIER: 367 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 368 return 1; 369 370 case PIPE_CAP_GLSL_FEATURE_LEVEL: 371 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120; 372 373 /* Supported except the original R600. */ 374 case PIPE_CAP_INDEP_BLEND_ENABLE: 375 case PIPE_CAP_INDEP_BLEND_FUNC: 376 /* R600 doesn't support per-MRT blends */ 377 return family == CHIP_R600 ? 0 : 1; 378 379 /* Supported on Evergreen. */ 380 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 381 return family >= CHIP_CEDAR ? 1 : 0; 382 383 /* Unsupported features. */ 384 case PIPE_CAP_TGSI_INSTANCEID: 385 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 386 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 387 case PIPE_CAP_SCALED_RESOLVE: 388 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 389 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 390 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 391 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 392 return 0; 393 394 /* Stream output. */ 395 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 396 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0; 397 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 398 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0; 399 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 400 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 401 return 16*4; 402 403 /* Texturing. */ 404 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 405 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 406 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 407 if (family >= CHIP_CEDAR) 408 return 15; 409 else 410 return 14; 411 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 412 return rscreen->info.drm_minor >= 9 ? 413 (family >= CHIP_CEDAR ? 16384 : 8192) : 0; 414 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 415 return 32; 416 417 /* Render targets. */ 418 case PIPE_CAP_MAX_RENDER_TARGETS: 419 /* FIXME some r6xx are buggy and can only do 4 */ 420 return 8; 421 422 /* Timer queries, present when the clock frequency is non zero. */ 423 case PIPE_CAP_TIMER_QUERY: 424 return rscreen->info.r600_clock_crystal_freq != 0; 425 426 case PIPE_CAP_MIN_TEXEL_OFFSET: 427 return -8; 428 429 case PIPE_CAP_MAX_TEXEL_OFFSET: 430 return 7; 431 } 432 return 0; 433} 434 435static float r600_get_paramf(struct pipe_screen* pscreen, 436 enum pipe_capf param) 437{ 438 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 439 enum radeon_family family = rscreen->family; 440 441 switch (param) { 442 case PIPE_CAPF_MAX_LINE_WIDTH: 443 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 444 case PIPE_CAPF_MAX_POINT_WIDTH: 445 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 446 if (family >= CHIP_CEDAR) 447 return 16384.0f; 448 else 449 return 8192.0f; 450 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 451 return 16.0f; 452 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 453 return 16.0f; 454 case PIPE_CAPF_GUARD_BAND_LEFT: 455 case PIPE_CAPF_GUARD_BAND_TOP: 456 case PIPE_CAPF_GUARD_BAND_RIGHT: 457 case PIPE_CAPF_GUARD_BAND_BOTTOM: 458 return 0.0f; 459 } 460 return 0.0f; 461} 462 463static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 464{ 465 switch(shader) 466 { 467 case PIPE_SHADER_FRAGMENT: 468 case PIPE_SHADER_VERTEX: 469 break; 470 case PIPE_SHADER_GEOMETRY: 471 /* TODO: support and enable geometry programs */ 472 return 0; 473 default: 474 /* TODO: support tessellation on Evergreen */ 475 return 0; 476 } 477 478 /* TODO: all these should be fixed, since r600 surely supports much more! */ 479 switch (param) { 480 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 481 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 482 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 483 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 484 return 16384; 485 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 486 return 8; /* FIXME */ 487 case PIPE_SHADER_CAP_MAX_INPUTS: 488 if(shader == PIPE_SHADER_FRAGMENT) 489 return 34; 490 else 491 return 32; 492 case PIPE_SHADER_CAP_MAX_TEMPS: 493 return 256; /* Max native temporaries. */ 494 case PIPE_SHADER_CAP_MAX_ADDRS: 495 /* FIXME Isn't this equal to TEMPS? */ 496 return 1; /* Max native address registers */ 497 case PIPE_SHADER_CAP_MAX_CONSTS: 498 return R600_MAX_CONST_BUFFER_SIZE; 499 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 500 return R600_MAX_CONST_BUFFERS-1; 501 case PIPE_SHADER_CAP_MAX_PREDS: 502 return 0; /* FIXME */ 503 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 504 return 1; 505 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 506 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 507 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 508 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 509 return 1; 510 case PIPE_SHADER_CAP_SUBROUTINES: 511 return 0; 512 case PIPE_SHADER_CAP_INTEGERS: 513 return 0; 514 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 515 return 16; 516 case PIPE_SHADER_CAP_OUTPUT_READ: 517 return 1; 518 } 519 return 0; 520} 521 522static int r600_get_video_param(struct pipe_screen *screen, 523 enum pipe_video_profile profile, 524 enum pipe_video_cap param) 525{ 526 switch (param) { 527 case PIPE_VIDEO_CAP_SUPPORTED: 528 return vl_profile_supported(screen, profile); 529 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 530 return 1; 531 case PIPE_VIDEO_CAP_MAX_WIDTH: 532 case PIPE_VIDEO_CAP_MAX_HEIGHT: 533 return vl_video_buffer_max_size(screen); 534 case PIPE_VIDEO_CAP_PREFERED_FORMAT: 535 return PIPE_FORMAT_NV12; 536 default: 537 return 0; 538 } 539} 540 541static void r600_destroy_screen(struct pipe_screen* pscreen) 542{ 543 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 544 545 if (rscreen == NULL) 546 return; 547 548 if (rscreen->fences.bo) { 549 struct r600_fence_block *entry, *tmp; 550 551 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) { 552 LIST_DEL(&entry->head); 553 FREE(entry); 554 } 555 556 rscreen->ws->buffer_unmap(rscreen->fences.bo->buf); 557 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL); 558 } 559 pipe_mutex_destroy(rscreen->fences.mutex); 560 561 rscreen->ws->destroy(rscreen->ws); 562 563 util_slab_destroy(&rscreen->pool_buffers); 564 pipe_mutex_destroy(rscreen->mutex_num_contexts); 565 FREE(rscreen); 566} 567 568static void r600_fence_reference(struct pipe_screen *pscreen, 569 struct pipe_fence_handle **ptr, 570 struct pipe_fence_handle *fence) 571{ 572 struct r600_fence **oldf = (struct r600_fence**)ptr; 573 struct r600_fence *newf = (struct r600_fence*)fence; 574 575 if (pipe_reference(&(*oldf)->reference, &newf->reference)) { 576 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 577 pipe_mutex_lock(rscreen->fences.mutex); 578 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool); 579 pipe_mutex_unlock(rscreen->fences.mutex); 580 } 581 582 *ptr = fence; 583} 584 585static boolean r600_fence_signalled(struct pipe_screen *pscreen, 586 struct pipe_fence_handle *fence) 587{ 588 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 589 struct r600_fence *rfence = (struct r600_fence*)fence; 590 591 return rscreen->fences.data[rfence->index]; 592} 593 594static boolean r600_fence_finish(struct pipe_screen *pscreen, 595 struct pipe_fence_handle *fence, 596 uint64_t timeout) 597{ 598 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 599 struct r600_fence *rfence = (struct r600_fence*)fence; 600 int64_t start_time = 0; 601 unsigned spins = 0; 602 603 if (timeout != PIPE_TIMEOUT_INFINITE) { 604 start_time = os_time_get(); 605 606 /* Convert to microseconds. */ 607 timeout /= 1000; 608 } 609 610 while (rscreen->fences.data[rfence->index] == 0) { 611 if (++spins % 256) 612 continue; 613#ifdef PIPE_OS_UNIX 614 sched_yield(); 615#else 616 os_time_sleep(10); 617#endif 618 if (timeout != PIPE_TIMEOUT_INFINITE && 619 os_time_get() - start_time >= timeout) { 620 return FALSE; 621 } 622 } 623 624 return TRUE; 625} 626 627static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 628{ 629 switch ((tiling_config & 0xe) >> 1) { 630 case 0: 631 rscreen->tiling_info.num_channels = 1; 632 break; 633 case 1: 634 rscreen->tiling_info.num_channels = 2; 635 break; 636 case 2: 637 rscreen->tiling_info.num_channels = 4; 638 break; 639 case 3: 640 rscreen->tiling_info.num_channels = 8; 641 break; 642 default: 643 return -EINVAL; 644 } 645 646 switch ((tiling_config & 0x30) >> 4) { 647 case 0: 648 rscreen->tiling_info.num_banks = 4; 649 break; 650 case 1: 651 rscreen->tiling_info.num_banks = 8; 652 break; 653 default: 654 return -EINVAL; 655 656 } 657 switch ((tiling_config & 0xc0) >> 6) { 658 case 0: 659 rscreen->tiling_info.group_bytes = 256; 660 break; 661 case 1: 662 rscreen->tiling_info.group_bytes = 512; 663 break; 664 default: 665 return -EINVAL; 666 } 667 return 0; 668} 669 670static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 671{ 672 switch (tiling_config & 0xf) { 673 case 0: 674 rscreen->tiling_info.num_channels = 1; 675 break; 676 case 1: 677 rscreen->tiling_info.num_channels = 2; 678 break; 679 case 2: 680 rscreen->tiling_info.num_channels = 4; 681 break; 682 case 3: 683 rscreen->tiling_info.num_channels = 8; 684 break; 685 default: 686 return -EINVAL; 687 } 688 689 switch ((tiling_config & 0xf0) >> 4) { 690 case 0: 691 rscreen->tiling_info.num_banks = 4; 692 break; 693 case 1: 694 rscreen->tiling_info.num_banks = 8; 695 break; 696 case 2: 697 rscreen->tiling_info.num_banks = 16; 698 break; 699 default: 700 return -EINVAL; 701 } 702 703 switch ((tiling_config & 0xf00) >> 8) { 704 case 0: 705 rscreen->tiling_info.group_bytes = 256; 706 break; 707 case 1: 708 rscreen->tiling_info.group_bytes = 512; 709 break; 710 default: 711 return -EINVAL; 712 } 713 return 0; 714} 715 716static int r600_init_tiling(struct r600_screen *rscreen) 717{ 718 uint32_t tiling_config = rscreen->info.r600_tiling_config; 719 720 /* set default group bytes, overridden by tiling info ioctl */ 721 if (rscreen->chip_class <= R700) { 722 rscreen->tiling_info.group_bytes = 256; 723 } else { 724 rscreen->tiling_info.group_bytes = 512; 725 } 726 727 if (!tiling_config) 728 return 0; 729 730 if (rscreen->chip_class <= R700) { 731 return r600_interpret_tiling(rscreen, tiling_config); 732 } else { 733 return evergreen_interpret_tiling(rscreen, tiling_config); 734 } 735} 736 737static unsigned radeon_family_from_device(unsigned device) 738{ 739 switch (device) { 740#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family; 741#include "pci_ids/r600_pci_ids.h" 742#undef CHIPSET 743 default: 744 return CHIP_UNKNOWN; 745 } 746} 747 748struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) 749{ 750 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen); 751 if (rscreen == NULL) { 752 return NULL; 753 } 754 755 rscreen->ws = ws; 756 ws->query_info(ws, &rscreen->info); 757 758 rscreen->family = radeon_family_from_device(rscreen->info.pci_id); 759 if (rscreen->family == CHIP_UNKNOWN) { 760 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); 761 FREE(rscreen); 762 return NULL; 763 } 764 765 /* setup class */ 766 if (rscreen->family == CHIP_CAYMAN) { 767 rscreen->chip_class = CAYMAN; 768 } else if (rscreen->family >= CHIP_CEDAR) { 769 rscreen->chip_class = EVERGREEN; 770 } else if (rscreen->family >= CHIP_RV770) { 771 rscreen->chip_class = R700; 772 } else { 773 rscreen->chip_class = R600; 774 } 775 776 if (r600_init_tiling(rscreen)) { 777 FREE(rscreen); 778 return NULL; 779 } 780 781 rscreen->screen.winsys = (struct pipe_winsys*)ws; 782 rscreen->screen.destroy = r600_destroy_screen; 783 rscreen->screen.get_name = r600_get_name; 784 rscreen->screen.get_vendor = r600_get_vendor; 785 rscreen->screen.get_param = r600_get_param; 786 rscreen->screen.get_shader_param = r600_get_shader_param; 787 rscreen->screen.get_paramf = r600_get_paramf; 788 rscreen->screen.get_video_param = r600_get_video_param; 789 if (rscreen->chip_class >= EVERGREEN) { 790 rscreen->screen.is_format_supported = evergreen_is_format_supported; 791 } else { 792 rscreen->screen.is_format_supported = r600_is_format_supported; 793 } 794 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; 795 rscreen->screen.context_create = r600_create_context; 796 rscreen->screen.fence_reference = r600_fence_reference; 797 rscreen->screen.fence_signalled = r600_fence_signalled; 798 rscreen->screen.fence_finish = r600_fence_finish; 799 r600_init_screen_resource_functions(&rscreen->screen); 800 801 util_format_s3tc_init(); 802 803 util_slab_create(&rscreen->pool_buffers, 804 sizeof(struct r600_resource), 64, 805 UTIL_SLAB_SINGLETHREADED); 806 807 pipe_mutex_init(rscreen->mutex_num_contexts); 808 809 rscreen->fences.bo = NULL; 810 rscreen->fences.data = NULL; 811 rscreen->fences.next_index = 0; 812 LIST_INITHEAD(&rscreen->fences.pool); 813 LIST_INITHEAD(&rscreen->fences.blocks); 814 pipe_mutex_init(rscreen->fences.mutex); 815 816 return &rscreen->screen; 817} 818