brw_fs.cpp revision 3dbc9ea0a35653a0484d3b0a65a305626c251789
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28extern "C" { 29 30#include <sys/types.h> 31 32#include "main/macros.h" 33#include "main/shaderobj.h" 34#include "program/prog_parameter.h" 35#include "program/prog_print.h" 36#include "program/prog_optimize.h" 37#include "program/hash_table.h" 38#include "brw_context.h" 39#include "brw_eu.h" 40#include "brw_wm.h" 41#include "talloc.h" 42} 43#include "../glsl/glsl_types.h" 44#include "../glsl/ir_optimization.h" 45#include "../glsl/ir_print_visitor.h" 46 47enum register_file { 48 ARF = BRW_ARCHITECTURE_REGISTER_FILE, 49 GRF = BRW_GENERAL_REGISTER_FILE, 50 MRF = BRW_MESSAGE_REGISTER_FILE, 51 IMM = BRW_IMMEDIATE_VALUE, 52 FIXED_HW_REG, /* a struct brw_reg */ 53 UNIFORM, /* prog_data->params[hw_reg] */ 54 BAD_FILE 55}; 56 57enum fs_opcodes { 58 FS_OPCODE_FB_WRITE = 256, 59 FS_OPCODE_RCP, 60 FS_OPCODE_RSQ, 61 FS_OPCODE_SQRT, 62 FS_OPCODE_EXP2, 63 FS_OPCODE_LOG2, 64 FS_OPCODE_POW, 65 FS_OPCODE_SIN, 66 FS_OPCODE_COS, 67 FS_OPCODE_DDX, 68 FS_OPCODE_DDY, 69 FS_OPCODE_LINTERP, 70 FS_OPCODE_TEX, 71 FS_OPCODE_TXB, 72 FS_OPCODE_TXL, 73 FS_OPCODE_DISCARD, 74}; 75 76static int using_new_fs = -1; 77 78struct gl_shader * 79brw_new_shader(GLcontext *ctx, GLuint name, GLuint type) 80{ 81 struct brw_shader *shader; 82 83 shader = talloc_zero(NULL, struct brw_shader); 84 if (shader) { 85 shader->base.Type = type; 86 shader->base.Name = name; 87 _mesa_init_shader(ctx, &shader->base); 88 } 89 90 return &shader->base; 91} 92 93struct gl_shader_program * 94brw_new_shader_program(GLcontext *ctx, GLuint name) 95{ 96 struct brw_shader_program *prog; 97 prog = talloc_zero(NULL, struct brw_shader_program); 98 if (prog) { 99 prog->base.Name = name; 100 _mesa_init_shader_program(ctx, &prog->base); 101 } 102 return &prog->base; 103} 104 105GLboolean 106brw_compile_shader(GLcontext *ctx, struct gl_shader *shader) 107{ 108 if (!_mesa_ir_compile_shader(ctx, shader)) 109 return GL_FALSE; 110 111 return GL_TRUE; 112} 113 114GLboolean 115brw_link_shader(GLcontext *ctx, struct gl_shader_program *prog) 116{ 117 if (using_new_fs == -1) 118 using_new_fs = getenv("INTEL_NEW_FS") != NULL; 119 120 for (unsigned i = 0; i < prog->_NumLinkedShaders; i++) { 121 struct brw_shader *shader = (struct brw_shader *)prog->_LinkedShaders[i]; 122 123 if (using_new_fs && shader->base.Type == GL_FRAGMENT_SHADER) { 124 void *mem_ctx = talloc_new(NULL); 125 bool progress; 126 127 if (shader->ir) 128 talloc_free(shader->ir); 129 shader->ir = new(shader) exec_list; 130 clone_ir_list(mem_ctx, shader->ir, shader->base.ir); 131 132 do_mat_op_to_vec(shader->ir); 133 do_mod_to_fract(shader->ir); 134 do_div_to_mul_rcp(shader->ir); 135 do_sub_to_add_neg(shader->ir); 136 do_explog_to_explog2(shader->ir); 137 138 brw_do_channel_expressions(shader->ir); 139 brw_do_vector_splitting(shader->ir); 140 141 do { 142 progress = false; 143 144 progress = do_common_optimization(shader->ir, true) || progress; 145 } while (progress); 146 147 validate_ir_tree(shader->ir); 148 149 reparent_ir(shader->ir, shader->ir); 150 talloc_free(mem_ctx); 151 } 152 } 153 154 if (!_mesa_ir_link_shader(ctx, prog)) 155 return GL_FALSE; 156 157 return GL_TRUE; 158} 159 160static int 161type_size(const struct glsl_type *type) 162{ 163 unsigned int size, i; 164 165 switch (type->base_type) { 166 case GLSL_TYPE_UINT: 167 case GLSL_TYPE_INT: 168 case GLSL_TYPE_FLOAT: 169 case GLSL_TYPE_BOOL: 170 return type->components(); 171 case GLSL_TYPE_ARRAY: 172 /* FINISHME: uniform/varying arrays. */ 173 return type_size(type->fields.array) * type->length; 174 case GLSL_TYPE_STRUCT: 175 size = 0; 176 for (i = 0; i < type->length; i++) { 177 size += type_size(type->fields.structure[i].type); 178 } 179 return size; 180 case GLSL_TYPE_SAMPLER: 181 /* Samplers take up no register space, since they're baked in at 182 * link time. 183 */ 184 return 0; 185 default: 186 assert(!"not reached"); 187 return 0; 188 } 189} 190 191class fs_reg { 192public: 193 /* Callers of this talloc-based new need not call delete. It's 194 * easier to just talloc_free 'ctx' (or any of its ancestors). */ 195 static void* operator new(size_t size, void *ctx) 196 { 197 void *node; 198 199 node = talloc_size(ctx, size); 200 assert(node != NULL); 201 202 return node; 203 } 204 205 void init() 206 { 207 this->reg = 0; 208 this->reg_offset = 0; 209 this->negate = 0; 210 this->abs = 0; 211 this->hw_reg = -1; 212 } 213 214 /** Generic unset register constructor. */ 215 fs_reg() 216 { 217 init(); 218 this->file = BAD_FILE; 219 } 220 221 /** Immediate value constructor. */ 222 fs_reg(float f) 223 { 224 init(); 225 this->file = IMM; 226 this->type = BRW_REGISTER_TYPE_F; 227 this->imm.f = f; 228 } 229 230 /** Immediate value constructor. */ 231 fs_reg(int32_t i) 232 { 233 init(); 234 this->file = IMM; 235 this->type = BRW_REGISTER_TYPE_D; 236 this->imm.i = i; 237 } 238 239 /** Immediate value constructor. */ 240 fs_reg(uint32_t u) 241 { 242 init(); 243 this->file = IMM; 244 this->type = BRW_REGISTER_TYPE_UD; 245 this->imm.u = u; 246 } 247 248 /** Fixed brw_reg Immediate value constructor. */ 249 fs_reg(struct brw_reg fixed_hw_reg) 250 { 251 init(); 252 this->file = FIXED_HW_REG; 253 this->fixed_hw_reg = fixed_hw_reg; 254 this->type = fixed_hw_reg.type; 255 } 256 257 fs_reg(enum register_file file, int hw_reg); 258 fs_reg(class fs_visitor *v, const struct glsl_type *type); 259 260 /** Register file: ARF, GRF, MRF, IMM. */ 261 enum register_file file; 262 /** Abstract register number. 0 = fixed hw reg */ 263 int reg; 264 /** Offset within the abstract register. */ 265 int reg_offset; 266 /** HW register number. Generally unset until register allocation. */ 267 int hw_reg; 268 /** Register type. BRW_REGISTER_TYPE_* */ 269 int type; 270 bool negate; 271 bool abs; 272 struct brw_reg fixed_hw_reg; 273 274 /** Value for file == BRW_IMMMEDIATE_FILE */ 275 union { 276 int32_t i; 277 uint32_t u; 278 float f; 279 } imm; 280}; 281 282static const fs_reg reg_undef; 283static const fs_reg reg_null(ARF, BRW_ARF_NULL); 284 285class fs_inst : public exec_node { 286public: 287 /* Callers of this talloc-based new need not call delete. It's 288 * easier to just talloc_free 'ctx' (or any of its ancestors). */ 289 static void* operator new(size_t size, void *ctx) 290 { 291 void *node; 292 293 node = talloc_zero_size(ctx, size); 294 assert(node != NULL); 295 296 return node; 297 } 298 299 void init() 300 { 301 this->opcode = BRW_OPCODE_NOP; 302 this->saturate = false; 303 this->conditional_mod = BRW_CONDITIONAL_NONE; 304 this->predicated = false; 305 this->sampler = 0; 306 this->shadow_compare = false; 307 } 308 309 fs_inst() 310 { 311 init(); 312 } 313 314 fs_inst(int opcode) 315 { 316 init(); 317 this->opcode = opcode; 318 } 319 320 fs_inst(int opcode, fs_reg dst, fs_reg src0) 321 { 322 init(); 323 this->opcode = opcode; 324 this->dst = dst; 325 this->src[0] = src0; 326 } 327 328 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1) 329 { 330 init(); 331 this->opcode = opcode; 332 this->dst = dst; 333 this->src[0] = src0; 334 this->src[1] = src1; 335 } 336 337 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) 338 { 339 init(); 340 this->opcode = opcode; 341 this->dst = dst; 342 this->src[0] = src0; 343 this->src[1] = src1; 344 this->src[2] = src2; 345 } 346 347 int opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ 348 fs_reg dst; 349 fs_reg src[3]; 350 bool saturate; 351 bool predicated; 352 int conditional_mod; /**< BRW_CONDITIONAL_* */ 353 354 int mlen; /** SEND message length */ 355 int sampler; 356 bool shadow_compare; 357 358 /** @{ 359 * Annotation for the generated IR. One of the two can be set. 360 */ 361 ir_instruction *ir; 362 const char *annotation; 363 /** @} */ 364}; 365 366class fs_visitor : public ir_visitor 367{ 368public: 369 370 fs_visitor(struct brw_wm_compile *c, struct brw_shader *shader) 371 { 372 this->c = c; 373 this->p = &c->func; 374 this->brw = p->brw; 375 this->intel = &brw->intel; 376 this->ctx = &intel->ctx; 377 this->mem_ctx = talloc_new(NULL); 378 this->shader = shader; 379 this->fail = false; 380 this->next_abstract_grf = 1; 381 this->variable_ht = hash_table_ctor(0, 382 hash_table_pointer_hash, 383 hash_table_pointer_compare); 384 385 this->frag_color = NULL; 386 this->frag_data = NULL; 387 this->frag_depth = NULL; 388 this->first_non_payload_grf = 0; 389 390 this->current_annotation = NULL; 391 this->annotation_string = NULL; 392 this->annotation_ir = NULL; 393 } 394 ~fs_visitor() 395 { 396 talloc_free(this->mem_ctx); 397 hash_table_dtor(this->variable_ht); 398 } 399 400 fs_reg *variable_storage(ir_variable *var); 401 402 void visit(ir_variable *ir); 403 void visit(ir_assignment *ir); 404 void visit(ir_dereference_variable *ir); 405 void visit(ir_dereference_record *ir); 406 void visit(ir_dereference_array *ir); 407 void visit(ir_expression *ir); 408 void visit(ir_texture *ir); 409 void visit(ir_if *ir); 410 void visit(ir_constant *ir); 411 void visit(ir_swizzle *ir); 412 void visit(ir_return *ir); 413 void visit(ir_loop *ir); 414 void visit(ir_loop_jump *ir); 415 void visit(ir_discard *ir); 416 void visit(ir_call *ir); 417 void visit(ir_function *ir); 418 void visit(ir_function_signature *ir); 419 420 fs_inst *emit(fs_inst inst); 421 void assign_curb_setup(); 422 void assign_urb_setup(); 423 void assign_regs(); 424 void generate_code(); 425 void generate_fb_write(fs_inst *inst); 426 void generate_linterp(fs_inst *inst, struct brw_reg dst, 427 struct brw_reg *src); 428 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src); 429 void generate_math(fs_inst *inst, struct brw_reg dst, struct brw_reg *src); 430 void generate_discard(fs_inst *inst); 431 432 void emit_dummy_fs(); 433 void emit_interpolation(); 434 void emit_pinterp(int location); 435 void emit_fb_writes(); 436 437 struct brw_reg interp_reg(int location, int channel); 438 439 struct brw_context *brw; 440 struct intel_context *intel; 441 GLcontext *ctx; 442 struct brw_wm_compile *c; 443 struct brw_compile *p; 444 struct brw_shader *shader; 445 void *mem_ctx; 446 exec_list instructions; 447 int next_abstract_grf; 448 struct hash_table *variable_ht; 449 ir_variable *frag_color, *frag_data, *frag_depth; 450 int first_non_payload_grf; 451 452 /** @{ debug annotation info */ 453 const char *current_annotation; 454 ir_instruction *base_ir; 455 const char **annotation_string; 456 ir_instruction **annotation_ir; 457 /** @} */ 458 459 bool fail; 460 461 /* Result of last visit() method. */ 462 fs_reg result; 463 464 fs_reg pixel_x; 465 fs_reg pixel_y; 466 fs_reg pixel_w; 467 fs_reg delta_x; 468 fs_reg delta_y; 469 fs_reg interp_attrs[64]; 470 471 int grf_used; 472 473}; 474 475/** Fixed HW reg constructor. */ 476fs_reg::fs_reg(enum register_file file, int hw_reg) 477{ 478 init(); 479 this->file = file; 480 this->hw_reg = hw_reg; 481 this->type = BRW_REGISTER_TYPE_F; 482} 483 484/** Automatic reg constructor. */ 485fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type) 486{ 487 init(); 488 489 this->file = GRF; 490 this->reg = v->next_abstract_grf; 491 this->reg_offset = 0; 492 v->next_abstract_grf += type_size(type); 493 494 switch (type->base_type) { 495 case GLSL_TYPE_FLOAT: 496 this->type = BRW_REGISTER_TYPE_F; 497 break; 498 case GLSL_TYPE_INT: 499 case GLSL_TYPE_BOOL: 500 this->type = BRW_REGISTER_TYPE_D; 501 break; 502 case GLSL_TYPE_UINT: 503 this->type = BRW_REGISTER_TYPE_UD; 504 break; 505 default: 506 assert(!"not reached"); 507 this->type = BRW_REGISTER_TYPE_F; 508 break; 509 } 510} 511 512fs_reg * 513fs_visitor::variable_storage(ir_variable *var) 514{ 515 return (fs_reg *)hash_table_find(this->variable_ht, var); 516} 517 518void 519fs_visitor::visit(ir_variable *ir) 520{ 521 fs_reg *reg = NULL; 522 523 if (strcmp(ir->name, "gl_FragColor") == 0) { 524 this->frag_color = ir; 525 } else if (strcmp(ir->name, "gl_FragData") == 0) { 526 this->frag_data = ir; 527 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 528 this->frag_depth = ir; 529 assert(!"FINISHME: this hangs currently."); 530 } 531 532 if (ir->mode == ir_var_in) { 533 reg = &this->interp_attrs[ir->location]; 534 } 535 536 if (ir->mode == ir_var_uniform) { 537 const float *vec_values; 538 int param_index = c->prog_data.nr_params; 539 540 /* FINISHME: This is wildly incomplete. */ 541 assert(ir->type->is_scalar() || ir->type->is_vector() || 542 ir->type->is_sampler()); 543 544 const struct gl_program *fp = &this->brw->fragment_program->Base; 545 /* Our support for uniforms is piggy-backed on the struct 546 * gl_fragment_program, because that's where the values actually 547 * get stored, rather than in some global gl_shader_program uniform 548 * store. 549 */ 550 vec_values = fp->Parameters->ParameterValues[ir->location]; 551 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 552 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[i]; 553 } 554 555 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 556 } 557 558 if (!reg) 559 reg = new(this->mem_ctx) fs_reg(this, ir->type); 560 561 hash_table_insert(this->variable_ht, reg, ir); 562} 563 564void 565fs_visitor::visit(ir_dereference_variable *ir) 566{ 567 fs_reg *reg = variable_storage(ir->var); 568 this->result = *reg; 569} 570 571void 572fs_visitor::visit(ir_dereference_record *ir) 573{ 574 assert(!"FINISHME"); 575} 576 577void 578fs_visitor::visit(ir_dereference_array *ir) 579{ 580 ir_constant *index; 581 int element_size; 582 583 ir->array->accept(this); 584 index = ir->array_index->as_constant(); 585 586 if (ir->type->is_matrix()) { 587 element_size = ir->type->vector_elements; 588 } else { 589 element_size = type_size(ir->type); 590 } 591 592 if (index) { 593 assert(this->result.file == UNIFORM || 594 (this->result.file == GRF && 595 this->result.reg != 0)); 596 this->result.reg_offset += index->value.i[0] * element_size; 597 } else { 598 assert(!"FINISHME: non-constant matrix column"); 599 } 600} 601 602void 603fs_visitor::visit(ir_expression *ir) 604{ 605 unsigned int operand; 606 fs_reg op[2], temp; 607 fs_reg result; 608 fs_inst *inst; 609 610 for (operand = 0; operand < ir->get_num_operands(); operand++) { 611 ir->operands[operand]->accept(this); 612 if (this->result.file == BAD_FILE) { 613 ir_print_visitor v; 614 printf("Failed to get tree for expression operand:\n"); 615 ir->operands[operand]->accept(&v); 616 this->fail = true; 617 } 618 op[operand] = this->result; 619 620 /* Matrix expression operands should have been broken down to vector 621 * operations already. 622 */ 623 assert(!ir->operands[operand]->type->is_matrix()); 624 /* And then those vector operands should have been broken down to scalar. 625 */ 626 assert(!ir->operands[operand]->type->is_vector()); 627 } 628 629 /* Storage for our result. If our result goes into an assignment, it will 630 * just get copy-propagated out, so no worries. 631 */ 632 this->result = fs_reg(this, ir->type); 633 634 switch (ir->operation) { 635 case ir_unop_logic_not: 636 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], fs_reg(-1))); 637 break; 638 case ir_unop_neg: 639 op[0].negate = ~op[0].negate; 640 this->result = op[0]; 641 break; 642 case ir_unop_abs: 643 op[0].abs = true; 644 this->result = op[0]; 645 break; 646 case ir_unop_sign: 647 temp = fs_reg(this, ir->type); 648 649 emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(0.0f))); 650 651 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f))); 652 inst->conditional_mod = BRW_CONDITIONAL_G; 653 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(1.0f))); 654 inst->predicated = true; 655 656 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f))); 657 inst->conditional_mod = BRW_CONDITIONAL_L; 658 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f))); 659 inst->predicated = true; 660 661 break; 662 case ir_unop_rcp: 663 emit(fs_inst(FS_OPCODE_RCP, this->result, op[0])); 664 break; 665 666 case ir_unop_exp2: 667 emit(fs_inst(FS_OPCODE_EXP2, this->result, op[0])); 668 break; 669 case ir_unop_log2: 670 emit(fs_inst(FS_OPCODE_LOG2, this->result, op[0])); 671 break; 672 case ir_unop_exp: 673 case ir_unop_log: 674 assert(!"not reached: should be handled by ir_explog_to_explog2"); 675 break; 676 case ir_unop_sin: 677 emit(fs_inst(FS_OPCODE_SIN, this->result, op[0])); 678 break; 679 case ir_unop_cos: 680 emit(fs_inst(FS_OPCODE_COS, this->result, op[0])); 681 break; 682 683 case ir_unop_dFdx: 684 emit(fs_inst(FS_OPCODE_DDX, this->result, op[0])); 685 break; 686 case ir_unop_dFdy: 687 emit(fs_inst(FS_OPCODE_DDY, this->result, op[0])); 688 break; 689 690 case ir_binop_add: 691 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], op[1])); 692 break; 693 case ir_binop_sub: 694 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 695 break; 696 697 case ir_binop_mul: 698 emit(fs_inst(BRW_OPCODE_MUL, this->result, op[0], op[1])); 699 break; 700 case ir_binop_div: 701 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 702 break; 703 case ir_binop_mod: 704 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 705 break; 706 707 case ir_binop_less: 708 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 709 inst->conditional_mod = BRW_CONDITIONAL_L; 710 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 711 break; 712 case ir_binop_greater: 713 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 714 inst->conditional_mod = BRW_CONDITIONAL_G; 715 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 716 break; 717 case ir_binop_lequal: 718 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 719 inst->conditional_mod = BRW_CONDITIONAL_LE; 720 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 721 break; 722 case ir_binop_gequal: 723 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 724 inst->conditional_mod = BRW_CONDITIONAL_GE; 725 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 726 break; 727 case ir_binop_equal: 728 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 729 inst->conditional_mod = BRW_CONDITIONAL_Z; 730 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 731 break; 732 case ir_binop_nequal: 733 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 734 inst->conditional_mod = BRW_CONDITIONAL_NZ; 735 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 736 break; 737 738 case ir_binop_logic_xor: 739 emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1])); 740 break; 741 742 case ir_binop_logic_or: 743 emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1])); 744 break; 745 746 case ir_binop_logic_and: 747 emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1])); 748 break; 749 750 case ir_binop_dot: 751 case ir_binop_cross: 752 case ir_unop_any: 753 assert(!"not reached: should be handled by brw_channel_expressions"); 754 break; 755 756 case ir_unop_sqrt: 757 emit(fs_inst(FS_OPCODE_SQRT, this->result, op[0])); 758 break; 759 760 case ir_unop_rsq: 761 emit(fs_inst(FS_OPCODE_RSQ, this->result, op[0])); 762 break; 763 764 case ir_unop_i2f: 765 case ir_unop_b2f: 766 case ir_unop_b2i: 767 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0])); 768 break; 769 case ir_unop_f2i: 770 emit(fs_inst(BRW_OPCODE_RNDZ, this->result, op[0])); 771 break; 772 case ir_unop_f2b: 773 case ir_unop_i2b: 774 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f))); 775 inst->conditional_mod = BRW_CONDITIONAL_NZ; 776 777 case ir_unop_trunc: 778 emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0])); 779 break; 780 case ir_unop_ceil: 781 op[0].negate = ~op[0].negate; 782 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0])); 783 this->result.negate = true; 784 break; 785 case ir_unop_floor: 786 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0])); 787 break; 788 case ir_unop_fract: 789 inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0])); 790 break; 791 792 case ir_binop_min: 793 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 794 inst->conditional_mod = BRW_CONDITIONAL_L; 795 796 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1])); 797 inst->predicated = true; 798 break; 799 case ir_binop_max: 800 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 801 inst->conditional_mod = BRW_CONDITIONAL_G; 802 803 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1])); 804 inst->predicated = true; 805 break; 806 807 case ir_binop_pow: 808 inst = emit(fs_inst(FS_OPCODE_POW, this->result, op[0], op[1])); 809 break; 810 811 case ir_unop_bit_not: 812 case ir_unop_u2f: 813 case ir_binop_lshift: 814 case ir_binop_rshift: 815 case ir_binop_bit_and: 816 case ir_binop_bit_xor: 817 case ir_binop_bit_or: 818 assert(!"GLSL 1.30 features unsupported"); 819 break; 820 } 821} 822 823void 824fs_visitor::visit(ir_assignment *ir) 825{ 826 struct fs_reg l, r; 827 int i; 828 int write_mask; 829 fs_inst *inst; 830 831 /* FINISHME: arrays on the lhs */ 832 ir->lhs->accept(this); 833 l = this->result; 834 835 ir->rhs->accept(this); 836 r = this->result; 837 838 /* FINISHME: This should really set to the correct maximal writemask for each 839 * FINISHME: component written (in the loops below). This case can only 840 * FINISHME: occur for matrices, arrays, and structures. 841 */ 842 if (ir->write_mask == 0) { 843 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector()); 844 write_mask = WRITEMASK_XYZW; 845 } else { 846 assert(ir->lhs->type->is_vector() || ir->lhs->type->is_scalar()); 847 write_mask = ir->write_mask; 848 } 849 850 assert(l.file != BAD_FILE); 851 assert(r.file != BAD_FILE); 852 853 if (ir->condition) { 854 /* Get the condition bool into the predicate. */ 855 ir->condition->accept(this); 856 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, fs_reg(0))); 857 inst->conditional_mod = BRW_CONDITIONAL_NZ; 858 } 859 860 for (i = 0; i < type_size(ir->lhs->type); i++) { 861 if (i >= 4 || (write_mask & (1 << i))) { 862 inst = emit(fs_inst(BRW_OPCODE_MOV, l, r)); 863 if (ir->condition) 864 inst->predicated = true; 865 } 866 l.reg_offset++; 867 r.reg_offset++; 868 } 869} 870 871void 872fs_visitor::visit(ir_texture *ir) 873{ 874 int base_mrf = 2; 875 fs_inst *inst = NULL; 876 unsigned int mlen = 0; 877 878 ir->coordinate->accept(this); 879 fs_reg coordinate = this->result; 880 881 if (ir->projector) { 882 fs_reg inv_proj = fs_reg(this, glsl_type::float_type); 883 884 ir->projector->accept(this); 885 emit(fs_inst(FS_OPCODE_RCP, inv_proj, this->result)); 886 887 fs_reg proj_coordinate = fs_reg(this, ir->coordinate->type); 888 for (unsigned int i = 0; i < ir->coordinate->type->vector_elements; i++) { 889 emit(fs_inst(BRW_OPCODE_MUL, proj_coordinate, coordinate, inv_proj)); 890 coordinate.reg_offset++; 891 proj_coordinate.reg_offset++; 892 } 893 proj_coordinate.reg_offset = 0; 894 895 coordinate = proj_coordinate; 896 } 897 898 for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) { 899 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate)); 900 coordinate.reg_offset++; 901 } 902 903 /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */ 904 if (intel->gen < 5) 905 mlen = 3; 906 907 if (ir->shadow_comparitor) { 908 /* For shadow comparisons, we have to supply u,v,r. */ 909 mlen = 3; 910 911 ir->shadow_comparitor->accept(this); 912 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result)); 913 mlen++; 914 } 915 916 /* Do we ever want to handle writemasking on texture samples? Is it 917 * performance relevant? 918 */ 919 fs_reg dst = fs_reg(this, glsl_type::vec4_type); 920 921 switch (ir->op) { 922 case ir_tex: 923 inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf))); 924 break; 925 case ir_txb: 926 ir->lod_info.bias->accept(this); 927 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result)); 928 mlen++; 929 930 inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf))); 931 break; 932 case ir_txl: 933 ir->lod_info.lod->accept(this); 934 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result)); 935 mlen++; 936 937 inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf))); 938 break; 939 case ir_txd: 940 case ir_txf: 941 assert(!"GLSL 1.30 features unsupported"); 942 break; 943 } 944 945 this->result = dst; 946 947 if (ir->shadow_comparitor) 948 inst->shadow_compare = true; 949 inst->mlen = mlen; 950} 951 952void 953fs_visitor::visit(ir_swizzle *ir) 954{ 955 ir->val->accept(this); 956 fs_reg val = this->result; 957 958 fs_reg result = fs_reg(this, ir->type); 959 this->result = result; 960 961 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 962 fs_reg channel = val; 963 int swiz = 0; 964 965 switch (i) { 966 case 0: 967 swiz = ir->mask.x; 968 break; 969 case 1: 970 swiz = ir->mask.y; 971 break; 972 case 2: 973 swiz = ir->mask.z; 974 break; 975 case 3: 976 swiz = ir->mask.w; 977 break; 978 } 979 980 channel.reg_offset += swiz; 981 emit(fs_inst(BRW_OPCODE_MOV, result, channel)); 982 result.reg_offset++; 983 } 984} 985 986void 987fs_visitor::visit(ir_discard *ir) 988{ 989 assert(ir->condition == NULL); /* FINISHME */ 990 991 emit(fs_inst(FS_OPCODE_DISCARD)); 992} 993 994void 995fs_visitor::visit(ir_constant *ir) 996{ 997 fs_reg reg(this, ir->type); 998 this->result = reg; 999 1000 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1001 switch (ir->type->base_type) { 1002 case GLSL_TYPE_FLOAT: 1003 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.f[i]))); 1004 break; 1005 case GLSL_TYPE_UINT: 1006 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.u[i]))); 1007 break; 1008 case GLSL_TYPE_INT: 1009 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.i[i]))); 1010 break; 1011 case GLSL_TYPE_BOOL: 1012 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg((int)ir->value.b[i]))); 1013 break; 1014 default: 1015 assert(!"Non-float/uint/int/bool constant"); 1016 } 1017 reg.reg_offset++; 1018 } 1019} 1020 1021void 1022fs_visitor::visit(ir_if *ir) 1023{ 1024 fs_inst *inst; 1025 1026 /* Don't point the annotation at the if statement, because then it plus 1027 * the then and else blocks get printed. 1028 */ 1029 this->base_ir = ir->condition; 1030 1031 /* Generate the condition into the condition code. */ 1032 ir->condition->accept(this); 1033 inst = emit(fs_inst(BRW_OPCODE_MOV, fs_reg(brw_null_reg()), this->result)); 1034 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1035 1036 inst = emit(fs_inst(BRW_OPCODE_IF)); 1037 inst->predicated = true; 1038 1039 foreach_iter(exec_list_iterator, iter, ir->then_instructions) { 1040 ir_instruction *ir = (ir_instruction *)iter.get(); 1041 this->base_ir = ir; 1042 1043 ir->accept(this); 1044 } 1045 1046 if (!ir->else_instructions.is_empty()) { 1047 emit(fs_inst(BRW_OPCODE_ELSE)); 1048 1049 foreach_iter(exec_list_iterator, iter, ir->else_instructions) { 1050 ir_instruction *ir = (ir_instruction *)iter.get(); 1051 this->base_ir = ir; 1052 1053 ir->accept(this); 1054 } 1055 } 1056 1057 emit(fs_inst(BRW_OPCODE_ENDIF)); 1058} 1059 1060void 1061fs_visitor::visit(ir_loop *ir) 1062{ 1063 assert(!ir->from); 1064 assert(!ir->to); 1065 assert(!ir->increment); 1066 assert(!ir->counter); 1067 1068 emit(fs_inst(BRW_OPCODE_DO)); 1069 1070 /* Start a safety counter. If the user messed up their loop 1071 * counting, we don't want to hang the GPU. 1072 */ 1073 fs_reg max_iter = fs_reg(this, glsl_type::int_type); 1074 emit(fs_inst(BRW_OPCODE_MOV, max_iter, fs_reg(10000))); 1075 1076 foreach_iter(exec_list_iterator, iter, ir->body_instructions) { 1077 ir_instruction *ir = (ir_instruction *)iter.get(); 1078 fs_inst *inst; 1079 1080 this->base_ir = ir; 1081 ir->accept(this); 1082 1083 /* Check the maximum loop iters counter. */ 1084 inst = emit(fs_inst(BRW_OPCODE_ADD, max_iter, max_iter, fs_reg(-1))); 1085 inst->conditional_mod = BRW_CONDITIONAL_Z; 1086 1087 inst = emit(fs_inst(BRW_OPCODE_BREAK)); 1088 inst->predicated = true; 1089 } 1090 1091 emit(fs_inst(BRW_OPCODE_WHILE)); 1092} 1093 1094void 1095fs_visitor::visit(ir_loop_jump *ir) 1096{ 1097 switch (ir->mode) { 1098 case ir_loop_jump::jump_break: 1099 emit(fs_inst(BRW_OPCODE_BREAK)); 1100 break; 1101 case ir_loop_jump::jump_continue: 1102 emit(fs_inst(BRW_OPCODE_CONTINUE)); 1103 break; 1104 } 1105} 1106 1107void 1108fs_visitor::visit(ir_call *ir) 1109{ 1110 assert(!"FINISHME"); 1111} 1112 1113void 1114fs_visitor::visit(ir_return *ir) 1115{ 1116 assert(!"FINISHME"); 1117} 1118 1119void 1120fs_visitor::visit(ir_function *ir) 1121{ 1122 /* Ignore function bodies other than main() -- we shouldn't see calls to 1123 * them since they should all be inlined before we get to ir_to_mesa. 1124 */ 1125 if (strcmp(ir->name, "main") == 0) { 1126 const ir_function_signature *sig; 1127 exec_list empty; 1128 1129 sig = ir->matching_signature(&empty); 1130 1131 assert(sig); 1132 1133 foreach_iter(exec_list_iterator, iter, sig->body) { 1134 ir_instruction *ir = (ir_instruction *)iter.get(); 1135 this->base_ir = ir; 1136 1137 ir->accept(this); 1138 } 1139 } 1140} 1141 1142void 1143fs_visitor::visit(ir_function_signature *ir) 1144{ 1145 assert(!"not reached"); 1146 (void)ir; 1147} 1148 1149fs_inst * 1150fs_visitor::emit(fs_inst inst) 1151{ 1152 fs_inst *list_inst = new(mem_ctx) fs_inst; 1153 *list_inst = inst; 1154 1155 list_inst->annotation = this->current_annotation; 1156 list_inst->ir = this->base_ir; 1157 1158 this->instructions.push_tail(list_inst); 1159 1160 return list_inst; 1161} 1162 1163/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1164void 1165fs_visitor::emit_dummy_fs() 1166{ 1167 /* Everyone's favorite color. */ 1168 emit(fs_inst(BRW_OPCODE_MOV, 1169 fs_reg(MRF, 2), 1170 fs_reg(1.0f))); 1171 emit(fs_inst(BRW_OPCODE_MOV, 1172 fs_reg(MRF, 3), 1173 fs_reg(0.0f))); 1174 emit(fs_inst(BRW_OPCODE_MOV, 1175 fs_reg(MRF, 4), 1176 fs_reg(1.0f))); 1177 emit(fs_inst(BRW_OPCODE_MOV, 1178 fs_reg(MRF, 5), 1179 fs_reg(0.0f))); 1180 1181 fs_inst *write; 1182 write = emit(fs_inst(FS_OPCODE_FB_WRITE, 1183 fs_reg(0), 1184 fs_reg(0))); 1185} 1186 1187/* The register location here is relative to the start of the URB 1188 * data. It will get adjusted to be a real location before 1189 * generate_code() time. 1190 */ 1191struct brw_reg 1192fs_visitor::interp_reg(int location, int channel) 1193{ 1194 int regnr = location * 2 + channel / 2; 1195 int stride = (channel & 1) * 4; 1196 1197 return brw_vec1_grf(regnr, stride); 1198} 1199 1200/** Emits the interpolation for the varying inputs. */ 1201void 1202fs_visitor::emit_interpolation() 1203{ 1204 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1205 /* For now, the source regs for the setup URB data will be unset, 1206 * since we don't know until codegen how many push constants we'll 1207 * use, and therefore what the setup URB offset is. 1208 */ 1209 fs_reg src_reg = reg_undef; 1210 1211 this->current_annotation = "compute pixel centers"; 1212 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1213 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1214 emit(fs_inst(BRW_OPCODE_ADD, 1215 this->pixel_x, 1216 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1217 fs_reg(brw_imm_v(0x10101010)))); 1218 emit(fs_inst(BRW_OPCODE_ADD, 1219 this->pixel_y, 1220 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1221 fs_reg(brw_imm_v(0x11001100)))); 1222 1223 this->current_annotation = "compute pixel deltas from v0"; 1224 this->delta_x = fs_reg(this, glsl_type::float_type); 1225 this->delta_y = fs_reg(this, glsl_type::float_type); 1226 emit(fs_inst(BRW_OPCODE_ADD, 1227 this->delta_x, 1228 this->pixel_x, 1229 fs_reg(negate(brw_vec1_grf(1, 0))))); 1230 emit(fs_inst(BRW_OPCODE_ADD, 1231 this->delta_y, 1232 this->pixel_y, 1233 fs_reg(brw_vec1_grf(1, 1)))); 1234 1235 this->current_annotation = "compute pos.w and 1/pos.w"; 1236 /* Compute wpos. Unlike many other varying inputs, we usually need it 1237 * to produce 1/w, and the varying variable wouldn't show up. 1238 */ 1239 fs_reg wpos = fs_reg(this, glsl_type::vec4_type); 1240 this->interp_attrs[FRAG_ATTRIB_WPOS] = wpos; 1241 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_x)); /* FINISHME: ARB_fcc */ 1242 wpos.reg_offset++; 1243 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y)); /* FINISHME: ARB_fcc */ 1244 wpos.reg_offset++; 1245 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y, 1246 interp_reg(FRAG_ATTRIB_WPOS, 2))); 1247 wpos.reg_offset++; 1248 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y, 1249 interp_reg(FRAG_ATTRIB_WPOS, 3))); 1250 /* Compute the pixel W value from wpos.w. */ 1251 this->pixel_w = fs_reg(this, glsl_type::float_type); 1252 emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos)); 1253 1254 /* FINISHME: gl_FrontFacing */ 1255 1256 foreach_iter(exec_list_iterator, iter, *this->shader->ir) { 1257 ir_instruction *ir = (ir_instruction *)iter.get(); 1258 ir_variable *var = ir->as_variable(); 1259 1260 if (!var) 1261 continue; 1262 1263 if (var->mode != ir_var_in) 1264 continue; 1265 1266 /* If it's already set up (WPOS), skip. */ 1267 if (var->location == 0) 1268 continue; 1269 1270 this->current_annotation = talloc_asprintf(this->mem_ctx, 1271 "interpolate %s " 1272 "(FRAG_ATTRIB[%d])", 1273 var->name, 1274 var->location); 1275 emit_pinterp(var->location); 1276 } 1277 this->current_annotation = NULL; 1278} 1279 1280void 1281fs_visitor::emit_pinterp(int location) 1282{ 1283 fs_reg interp_attr = fs_reg(this, glsl_type::vec4_type); 1284 this->interp_attrs[location] = interp_attr; 1285 1286 for (unsigned int i = 0; i < 4; i++) { 1287 struct brw_reg interp = interp_reg(location, i); 1288 emit(fs_inst(FS_OPCODE_LINTERP, 1289 interp_attr, 1290 this->delta_x, 1291 this->delta_y, 1292 fs_reg(interp))); 1293 interp_attr.reg_offset++; 1294 } 1295 interp_attr.reg_offset -= 4; 1296 1297 for (unsigned int i = 0; i < 4; i++) { 1298 emit(fs_inst(BRW_OPCODE_MUL, 1299 interp_attr, 1300 interp_attr, 1301 this->pixel_w)); 1302 interp_attr.reg_offset++; 1303 } 1304} 1305 1306void 1307fs_visitor::emit_fb_writes() 1308{ 1309 this->current_annotation = "FB write"; 1310 1311 assert(this->frag_color || !"FINISHME: MRT"); 1312 fs_reg color = *(variable_storage(this->frag_color)); 1313 1314 for (int i = 0; i < 4; i++) { 1315 emit(fs_inst(BRW_OPCODE_MOV, 1316 fs_reg(MRF, 2 + i), 1317 color)); 1318 color.reg_offset++; 1319 } 1320 1321 emit(fs_inst(FS_OPCODE_FB_WRITE, 1322 fs_reg(0), 1323 fs_reg(0))); 1324 1325 this->current_annotation = NULL; 1326} 1327 1328void 1329fs_visitor::generate_fb_write(fs_inst *inst) 1330{ 1331 GLboolean eot = 1; /* FINISHME: MRT */ 1332 /* FINISHME: AADS */ 1333 1334 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied 1335 * move, here's g1. 1336 */ 1337 brw_push_insn_state(p); 1338 brw_set_mask_control(p, BRW_MASK_DISABLE); 1339 brw_set_compression_control(p, BRW_COMPRESSION_NONE); 1340 brw_MOV(p, 1341 brw_message_reg(1), 1342 brw_vec8_grf(1, 0)); 1343 brw_pop_insn_state(p); 1344 1345 int nr = 2 + 4; 1346 1347 brw_fb_WRITE(p, 1348 8, /* dispatch_width */ 1349 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW), 1350 0, /* base MRF */ 1351 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), 1352 0, /* FINISHME: MRT target */ 1353 nr, 1354 0, 1355 eot); 1356} 1357 1358void 1359fs_visitor::generate_linterp(fs_inst *inst, 1360 struct brw_reg dst, struct brw_reg *src) 1361{ 1362 struct brw_reg delta_x = src[0]; 1363 struct brw_reg delta_y = src[1]; 1364 struct brw_reg interp = src[2]; 1365 1366 if (brw->has_pln && 1367 delta_y.nr == delta_x.nr + 1 && 1368 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) { 1369 brw_PLN(p, dst, interp, delta_x); 1370 } else { 1371 brw_LINE(p, brw_null_reg(), interp, delta_x); 1372 brw_MAC(p, dst, suboffset(interp, 1), delta_y); 1373 } 1374} 1375 1376void 1377fs_visitor::generate_math(fs_inst *inst, 1378 struct brw_reg dst, struct brw_reg *src) 1379{ 1380 int op; 1381 1382 switch (inst->opcode) { 1383 case FS_OPCODE_RCP: 1384 op = BRW_MATH_FUNCTION_INV; 1385 break; 1386 case FS_OPCODE_RSQ: 1387 op = BRW_MATH_FUNCTION_RSQ; 1388 break; 1389 case FS_OPCODE_SQRT: 1390 op = BRW_MATH_FUNCTION_SQRT; 1391 break; 1392 case FS_OPCODE_EXP2: 1393 op = BRW_MATH_FUNCTION_EXP; 1394 break; 1395 case FS_OPCODE_LOG2: 1396 op = BRW_MATH_FUNCTION_LOG; 1397 break; 1398 case FS_OPCODE_POW: 1399 op = BRW_MATH_FUNCTION_POW; 1400 break; 1401 case FS_OPCODE_SIN: 1402 op = BRW_MATH_FUNCTION_SIN; 1403 break; 1404 case FS_OPCODE_COS: 1405 op = BRW_MATH_FUNCTION_COS; 1406 break; 1407 default: 1408 assert(!"not reached: unknown math function"); 1409 op = 0; 1410 break; 1411 } 1412 1413 if (inst->opcode == FS_OPCODE_POW) { 1414 brw_MOV(p, brw_message_reg(3), src[1]); 1415 } 1416 1417 brw_math(p, dst, 1418 op, 1419 inst->saturate ? BRW_MATH_SATURATE_SATURATE : 1420 BRW_MATH_SATURATE_NONE, 1421 2, src[0], 1422 BRW_MATH_DATA_VECTOR, 1423 BRW_MATH_PRECISION_FULL); 1424} 1425 1426void 1427fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) 1428{ 1429 int msg_type = -1; 1430 int rlen = 4; 1431 1432 if (intel->gen == 5) { 1433 switch (inst->opcode) { 1434 case FS_OPCODE_TEX: 1435 if (inst->shadow_compare) { 1436 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5; 1437 } else { 1438 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5; 1439 } 1440 break; 1441 case FS_OPCODE_TXB: 1442 if (inst->shadow_compare) { 1443 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5; 1444 } else { 1445 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5; 1446 } 1447 break; 1448 } 1449 } else { 1450 switch (inst->opcode) { 1451 case FS_OPCODE_TEX: 1452 /* Note that G45 and older determines shadow compare and dispatch width 1453 * from message length for most messages. 1454 */ 1455 if (inst->shadow_compare) { 1456 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE; 1457 } else { 1458 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE; 1459 } 1460 case FS_OPCODE_TXB: 1461 if (inst->shadow_compare) { 1462 assert(!"FINISHME: shadow compare with bias."); 1463 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; 1464 } else { 1465 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; 1466 rlen = 8; 1467 } 1468 break; 1469 } 1470 } 1471 assert(msg_type != -1); 1472 1473 /* g0 header. */ 1474 src.nr--; 1475 1476 brw_SAMPLE(p, 1477 retype(dst, BRW_REGISTER_TYPE_UW), 1478 src.nr, 1479 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), 1480 SURF_INDEX_TEXTURE(inst->sampler), 1481 inst->sampler, 1482 WRITEMASK_XYZW, 1483 msg_type, 1484 rlen, 1485 inst->mlen + 1, 1486 0, 1487 1, 1488 BRW_SAMPLER_SIMD_MODE_SIMD8); 1489} 1490 1491void 1492fs_visitor::generate_discard(fs_inst *inst) 1493{ 1494 struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); 1495 brw_push_insn_state(p); 1496 brw_set_mask_control(p, BRW_MASK_DISABLE); 1497 brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); /* IMASK */ 1498 brw_AND(p, g0, c->emit_mask_reg, g0); 1499 brw_pop_insn_state(p); 1500} 1501 1502static void 1503trivial_assign_reg(int header_size, fs_reg *reg) 1504{ 1505 if (reg->file == GRF && reg->reg != 0) { 1506 reg->hw_reg = header_size + reg->reg - 1 + reg->reg_offset; 1507 reg->reg = 0; 1508 } 1509} 1510 1511void 1512fs_visitor::assign_curb_setup() 1513{ 1514 c->prog_data.first_curbe_grf = c->key.nr_payload_regs; 1515 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8; 1516 1517 /* Map the offsets in the UNIFORM file to fixed HW regs. */ 1518 foreach_iter(exec_list_iterator, iter, this->instructions) { 1519 fs_inst *inst = (fs_inst *)iter.get(); 1520 1521 for (unsigned int i = 0; i < 3; i++) { 1522 if (inst->src[i].file == UNIFORM) { 1523 int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset; 1524 struct brw_reg brw_reg = brw_vec1_grf(c->prog_data.first_curbe_grf + 1525 constant_nr / 8, 1526 constant_nr % 8); 1527 1528 inst->src[i].file = FIXED_HW_REG; 1529 inst->src[i].fixed_hw_reg = brw_reg; 1530 } 1531 } 1532 } 1533} 1534 1535void 1536fs_visitor::assign_urb_setup() 1537{ 1538 int urb_start = c->prog_data.first_curbe_grf + c->prog_data.curb_read_length; 1539 int interp_reg_nr[FRAG_ATTRIB_MAX]; 1540 1541 c->prog_data.urb_read_length = 0; 1542 1543 /* Figure out where each of the incoming setup attributes lands. */ 1544 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) { 1545 interp_reg_nr[i] = -1; 1546 1547 if (i != FRAG_ATTRIB_WPOS && 1548 !(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i))) 1549 continue; 1550 1551 /* Each attribute is 4 setup channels, each of which is half a reg. */ 1552 interp_reg_nr[i] = urb_start + c->prog_data.urb_read_length; 1553 c->prog_data.urb_read_length += 2; 1554 } 1555 1556 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses 1557 * the correct setup input. 1558 */ 1559 foreach_iter(exec_list_iterator, iter, this->instructions) { 1560 fs_inst *inst = (fs_inst *)iter.get(); 1561 1562 if (inst->opcode != FS_OPCODE_LINTERP) 1563 continue; 1564 1565 assert(inst->src[2].file == FIXED_HW_REG); 1566 1567 int location = inst->src[2].fixed_hw_reg.nr / 2; 1568 assert(interp_reg_nr[location] != -1); 1569 inst->src[2].fixed_hw_reg.nr = (interp_reg_nr[location] + 1570 (inst->src[2].fixed_hw_reg.nr & 1)); 1571 } 1572 1573 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length; 1574} 1575 1576void 1577fs_visitor::assign_regs() 1578{ 1579 int header_size = this->first_non_payload_grf; 1580 int last_grf = 0; 1581 1582 /* FINISHME: trivial assignment of register numbers */ 1583 foreach_iter(exec_list_iterator, iter, this->instructions) { 1584 fs_inst *inst = (fs_inst *)iter.get(); 1585 1586 trivial_assign_reg(header_size, &inst->dst); 1587 trivial_assign_reg(header_size, &inst->src[0]); 1588 trivial_assign_reg(header_size, &inst->src[1]); 1589 1590 last_grf = MAX2(last_grf, inst->dst.hw_reg); 1591 last_grf = MAX2(last_grf, inst->src[0].hw_reg); 1592 last_grf = MAX2(last_grf, inst->src[1].hw_reg); 1593 } 1594 1595 this->grf_used = last_grf + 1; 1596} 1597 1598static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg) 1599{ 1600 struct brw_reg brw_reg; 1601 1602 switch (reg->file) { 1603 case GRF: 1604 case ARF: 1605 case MRF: 1606 brw_reg = brw_vec8_reg(reg->file, 1607 reg->hw_reg, 0); 1608 brw_reg = retype(brw_reg, reg->type); 1609 break; 1610 case IMM: 1611 switch (reg->type) { 1612 case BRW_REGISTER_TYPE_F: 1613 brw_reg = brw_imm_f(reg->imm.f); 1614 break; 1615 case BRW_REGISTER_TYPE_D: 1616 brw_reg = brw_imm_d(reg->imm.i); 1617 break; 1618 case BRW_REGISTER_TYPE_UD: 1619 brw_reg = brw_imm_ud(reg->imm.u); 1620 break; 1621 default: 1622 assert(!"not reached"); 1623 break; 1624 } 1625 break; 1626 case FIXED_HW_REG: 1627 brw_reg = reg->fixed_hw_reg; 1628 break; 1629 case BAD_FILE: 1630 /* Probably unused. */ 1631 brw_reg = brw_null_reg(); 1632 break; 1633 case UNIFORM: 1634 assert(!"not reached"); 1635 brw_reg = brw_null_reg(); 1636 break; 1637 } 1638 if (reg->abs) 1639 brw_reg = brw_abs(brw_reg); 1640 if (reg->negate) 1641 brw_reg = negate(brw_reg); 1642 1643 return brw_reg; 1644} 1645 1646void 1647fs_visitor::generate_code() 1648{ 1649 unsigned int annotation_len = 0; 1650 int last_native_inst = 0; 1651 struct brw_instruction *if_stack[16], *loop_stack[16]; 1652 int if_stack_depth = 0, loop_stack_depth = 0; 1653 int if_depth_in_loop[16]; 1654 1655 if_depth_in_loop[loop_stack_depth] = 0; 1656 1657 memset(&if_stack, 0, sizeof(if_stack)); 1658 foreach_iter(exec_list_iterator, iter, this->instructions) { 1659 fs_inst *inst = (fs_inst *)iter.get(); 1660 struct brw_reg src[3], dst; 1661 1662 for (unsigned int i = 0; i < 3; i++) { 1663 src[i] = brw_reg_from_fs_reg(&inst->src[i]); 1664 } 1665 dst = brw_reg_from_fs_reg(&inst->dst); 1666 1667 brw_set_conditionalmod(p, inst->conditional_mod); 1668 brw_set_predicate_control(p, inst->predicated); 1669 1670 switch (inst->opcode) { 1671 case BRW_OPCODE_MOV: 1672 brw_MOV(p, dst, src[0]); 1673 break; 1674 case BRW_OPCODE_ADD: 1675 brw_ADD(p, dst, src[0], src[1]); 1676 break; 1677 case BRW_OPCODE_MUL: 1678 brw_MUL(p, dst, src[0], src[1]); 1679 break; 1680 1681 case BRW_OPCODE_FRC: 1682 brw_FRC(p, dst, src[0]); 1683 break; 1684 case BRW_OPCODE_RNDD: 1685 brw_RNDD(p, dst, src[0]); 1686 break; 1687 case BRW_OPCODE_RNDZ: 1688 brw_RNDZ(p, dst, src[0]); 1689 break; 1690 1691 case BRW_OPCODE_AND: 1692 brw_AND(p, dst, src[0], src[1]); 1693 break; 1694 case BRW_OPCODE_OR: 1695 brw_OR(p, dst, src[0], src[1]); 1696 break; 1697 case BRW_OPCODE_XOR: 1698 brw_XOR(p, dst, src[0], src[1]); 1699 break; 1700 1701 case BRW_OPCODE_CMP: 1702 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); 1703 break; 1704 case BRW_OPCODE_SEL: 1705 brw_SEL(p, dst, src[0], src[1]); 1706 break; 1707 1708 case BRW_OPCODE_IF: 1709 assert(if_stack_depth < 16); 1710 if_stack[if_stack_depth] = brw_IF(p, BRW_EXECUTE_8); 1711 if_stack_depth++; 1712 break; 1713 case BRW_OPCODE_ELSE: 1714 if_stack[if_stack_depth - 1] = 1715 brw_ELSE(p, if_stack[if_stack_depth - 1]); 1716 break; 1717 case BRW_OPCODE_ENDIF: 1718 if_stack_depth--; 1719 brw_ENDIF(p , if_stack[if_stack_depth]); 1720 break; 1721 1722 case BRW_OPCODE_DO: 1723 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8); 1724 if_depth_in_loop[loop_stack_depth] = 0; 1725 break; 1726 1727 case BRW_OPCODE_BREAK: 1728 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]); 1729 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 1730 break; 1731 case BRW_OPCODE_CONTINUE: 1732 brw_CONT(p, if_depth_in_loop[loop_stack_depth]); 1733 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 1734 break; 1735 1736 case BRW_OPCODE_WHILE: { 1737 struct brw_instruction *inst0, *inst1; 1738 GLuint br = 1; 1739 1740 if (intel->gen == 5) 1741 br = 2; 1742 1743 assert(loop_stack_depth > 0); 1744 loop_stack_depth--; 1745 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]); 1746 /* patch all the BREAK/CONT instructions from last BGNLOOP */ 1747 while (inst0 > loop_stack[loop_stack_depth]) { 1748 inst0--; 1749 if (inst0->header.opcode == BRW_OPCODE_BREAK && 1750 inst0->bits3.if_else.jump_count == 0) { 1751 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); 1752 } 1753 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE && 1754 inst0->bits3.if_else.jump_count == 0) { 1755 inst0->bits3.if_else.jump_count = br * (inst1 - inst0); 1756 } 1757 } 1758 } 1759 break; 1760 1761 case FS_OPCODE_RCP: 1762 case FS_OPCODE_RSQ: 1763 case FS_OPCODE_SQRT: 1764 case FS_OPCODE_EXP2: 1765 case FS_OPCODE_LOG2: 1766 case FS_OPCODE_POW: 1767 case FS_OPCODE_SIN: 1768 case FS_OPCODE_COS: 1769 generate_math(inst, dst, src); 1770 break; 1771 case FS_OPCODE_LINTERP: 1772 generate_linterp(inst, dst, src); 1773 break; 1774 case FS_OPCODE_TEX: 1775 case FS_OPCODE_TXB: 1776 case FS_OPCODE_TXL: 1777 generate_tex(inst, dst, src[0]); 1778 break; 1779 case FS_OPCODE_DISCARD: 1780 generate_discard(inst); 1781 break; 1782 case FS_OPCODE_FB_WRITE: 1783 generate_fb_write(inst); 1784 break; 1785 default: 1786 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { 1787 _mesa_problem(ctx, "Unsupported opcode `%s' in FS", 1788 brw_opcodes[inst->opcode].name); 1789 } else { 1790 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode); 1791 } 1792 this->fail = true; 1793 } 1794 1795 if (annotation_len < p->nr_insn) { 1796 annotation_len *= 2; 1797 if (annotation_len < 16) 1798 annotation_len = 16; 1799 1800 this->annotation_string = talloc_realloc(this->mem_ctx, 1801 annotation_string, 1802 const char *, 1803 annotation_len); 1804 this->annotation_ir = talloc_realloc(this->mem_ctx, 1805 annotation_ir, 1806 ir_instruction *, 1807 annotation_len); 1808 } 1809 1810 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { 1811 this->annotation_string[i] = inst->annotation; 1812 this->annotation_ir[i] = inst->ir; 1813 } 1814 last_native_inst = p->nr_insn; 1815 } 1816} 1817 1818GLboolean 1819brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c) 1820{ 1821 struct brw_compile *p = &c->func; 1822 struct intel_context *intel = &brw->intel; 1823 GLcontext *ctx = &intel->ctx; 1824 struct brw_shader *shader = NULL; 1825 struct gl_shader_program *prog = ctx->Shader.CurrentProgram; 1826 1827 if (!prog) 1828 return GL_FALSE; 1829 1830 if (!using_new_fs) 1831 return GL_FALSE; 1832 1833 for (unsigned int i = 0; i < prog->_NumLinkedShaders; i++) { 1834 if (prog->_LinkedShaders[i]->Type == GL_FRAGMENT_SHADER) { 1835 shader = (struct brw_shader *)prog->_LinkedShaders[i]; 1836 break; 1837 } 1838 } 1839 if (!shader) 1840 return GL_FALSE; 1841 1842 /* We always use 8-wide mode, at least for now. For one, flow 1843 * control only works in 8-wide. Also, when we're fragment shader 1844 * bound, we're almost always under register pressure as well, so 1845 * 8-wide would save us from the performance cliff of spilling 1846 * regs. 1847 */ 1848 c->dispatch_width = 8; 1849 1850 if (INTEL_DEBUG & DEBUG_WM) { 1851 printf("GLSL IR for native fragment shader %d:\n", prog->Name); 1852 _mesa_print_ir(shader->ir, NULL); 1853 printf("\n"); 1854 } 1855 1856 /* Now the main event: Visit the shader IR and generate our FS IR for it. 1857 */ 1858 fs_visitor v(c, shader); 1859 1860 if (0) { 1861 v.emit_dummy_fs(); 1862 } else { 1863 v.emit_interpolation(); 1864 1865 /* Generate FS IR for main(). (the visitor only descends into 1866 * functions called "main"). 1867 */ 1868 foreach_iter(exec_list_iterator, iter, *shader->ir) { 1869 ir_instruction *ir = (ir_instruction *)iter.get(); 1870 v.base_ir = ir; 1871 ir->accept(&v); 1872 } 1873 1874 v.emit_fb_writes(); 1875 v.assign_curb_setup(); 1876 v.assign_urb_setup(); 1877 v.assign_regs(); 1878 } 1879 1880 v.generate_code(); 1881 1882 assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */ 1883 1884 if (v.fail) 1885 return GL_FALSE; 1886 1887 if (INTEL_DEBUG & DEBUG_WM) { 1888 const char *last_annotation_string = NULL; 1889 ir_instruction *last_annotation_ir = NULL; 1890 1891 printf("Native code for fragment shader %d:\n", prog->Name); 1892 for (unsigned int i = 0; i < p->nr_insn; i++) { 1893 if (last_annotation_ir != v.annotation_ir[i]) { 1894 last_annotation_ir = v.annotation_ir[i]; 1895 if (last_annotation_ir) { 1896 printf(" "); 1897 last_annotation_ir->print(); 1898 printf("\n"); 1899 } 1900 } 1901 if (last_annotation_string != v.annotation_string[i]) { 1902 last_annotation_string = v.annotation_string[i]; 1903 if (last_annotation_string) 1904 printf(" %s\n", last_annotation_string); 1905 } 1906 brw_disasm(stdout, &p->store[i], intel->gen); 1907 } 1908 printf("\n"); 1909 } 1910 1911 c->prog_data.total_grf = v.grf_used; 1912 c->prog_data.total_scratch = 0; 1913 1914 return GL_TRUE; 1915} 1916