brw_fs.cpp revision 6ef5f212343c0557c4fca272d8236226c1a7c87a
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28extern "C" { 29 30#include <sys/types.h> 31 32#include "main/macros.h" 33#include "main/shaderobj.h" 34#include "program/prog_parameter.h" 35#include "program/prog_print.h" 36#include "program/prog_optimize.h" 37#include "program/hash_table.h" 38#include "brw_context.h" 39#include "brw_eu.h" 40#include "brw_wm.h" 41#include "talloc.h" 42} 43#include "../glsl/glsl_types.h" 44#include "../glsl/ir_optimization.h" 45#include "../glsl/ir_print_visitor.h" 46 47enum register_file { 48 ARF = BRW_ARCHITECTURE_REGISTER_FILE, 49 GRF = BRW_GENERAL_REGISTER_FILE, 50 MRF = BRW_MESSAGE_REGISTER_FILE, 51 IMM = BRW_IMMEDIATE_VALUE, 52 FIXED_HW_REG, /* a struct brw_reg */ 53 UNIFORM, /* prog_data->params[hw_reg] */ 54 BAD_FILE 55}; 56 57enum fs_opcodes { 58 FS_OPCODE_FB_WRITE = 256, 59 FS_OPCODE_RCP, 60 FS_OPCODE_RSQ, 61 FS_OPCODE_SQRT, 62 FS_OPCODE_EXP2, 63 FS_OPCODE_LOG2, 64 FS_OPCODE_POW, 65 FS_OPCODE_SIN, 66 FS_OPCODE_COS, 67 FS_OPCODE_DDX, 68 FS_OPCODE_DDY, 69 FS_OPCODE_LINTERP, 70 FS_OPCODE_TEX, 71 FS_OPCODE_TXB, 72 FS_OPCODE_TXL, 73 FS_OPCODE_DISCARD, 74}; 75 76static int using_new_fs = -1; 77 78struct gl_shader * 79brw_new_shader(GLcontext *ctx, GLuint name, GLuint type) 80{ 81 struct brw_shader *shader; 82 83 shader = talloc_zero(NULL, struct brw_shader); 84 if (shader) { 85 shader->base.Type = type; 86 shader->base.Name = name; 87 _mesa_init_shader(ctx, &shader->base); 88 } 89 90 return &shader->base; 91} 92 93struct gl_shader_program * 94brw_new_shader_program(GLcontext *ctx, GLuint name) 95{ 96 struct brw_shader_program *prog; 97 prog = talloc_zero(NULL, struct brw_shader_program); 98 if (prog) { 99 prog->base.Name = name; 100 _mesa_init_shader_program(ctx, &prog->base); 101 } 102 return &prog->base; 103} 104 105GLboolean 106brw_compile_shader(GLcontext *ctx, struct gl_shader *shader) 107{ 108 if (!_mesa_ir_compile_shader(ctx, shader)) 109 return GL_FALSE; 110 111 return GL_TRUE; 112} 113 114GLboolean 115brw_link_shader(GLcontext *ctx, struct gl_shader_program *prog) 116{ 117 if (using_new_fs == -1) 118 using_new_fs = getenv("INTEL_NEW_FS") != NULL; 119 120 for (unsigned i = 0; i < prog->_NumLinkedShaders; i++) { 121 struct brw_shader *shader = (struct brw_shader *)prog->_LinkedShaders[i]; 122 123 if (using_new_fs && shader->base.Type == GL_FRAGMENT_SHADER) { 124 void *mem_ctx = talloc_new(NULL); 125 bool progress; 126 127 if (shader->ir) 128 talloc_free(shader->ir); 129 shader->ir = new(shader) exec_list; 130 clone_ir_list(mem_ctx, shader->ir, shader->base.ir); 131 132 do_mat_op_to_vec(shader->ir); 133 do_mod_to_fract(shader->ir); 134 do_div_to_mul_rcp(shader->ir); 135 do_sub_to_add_neg(shader->ir); 136 do_explog_to_explog2(shader->ir); 137 138 brw_do_channel_expressions(shader->ir); 139 brw_do_vector_splitting(shader->ir); 140 141 do { 142 progress = false; 143 144 progress = do_common_optimization(shader->ir, true, 32) || progress; 145 } while (progress); 146 147 validate_ir_tree(shader->ir); 148 149 reparent_ir(shader->ir, shader->ir); 150 talloc_free(mem_ctx); 151 } 152 } 153 154 if (!_mesa_ir_link_shader(ctx, prog)) 155 return GL_FALSE; 156 157 return GL_TRUE; 158} 159 160static int 161type_size(const struct glsl_type *type) 162{ 163 unsigned int size, i; 164 165 switch (type->base_type) { 166 case GLSL_TYPE_UINT: 167 case GLSL_TYPE_INT: 168 case GLSL_TYPE_FLOAT: 169 case GLSL_TYPE_BOOL: 170 return type->components(); 171 case GLSL_TYPE_ARRAY: 172 /* FINISHME: uniform/varying arrays. */ 173 return type_size(type->fields.array) * type->length; 174 case GLSL_TYPE_STRUCT: 175 size = 0; 176 for (i = 0; i < type->length; i++) { 177 size += type_size(type->fields.structure[i].type); 178 } 179 return size; 180 case GLSL_TYPE_SAMPLER: 181 /* Samplers take up no register space, since they're baked in at 182 * link time. 183 */ 184 return 0; 185 default: 186 assert(!"not reached"); 187 return 0; 188 } 189} 190 191class fs_reg { 192public: 193 /* Callers of this talloc-based new need not call delete. It's 194 * easier to just talloc_free 'ctx' (or any of its ancestors). */ 195 static void* operator new(size_t size, void *ctx) 196 { 197 void *node; 198 199 node = talloc_size(ctx, size); 200 assert(node != NULL); 201 202 return node; 203 } 204 205 void init() 206 { 207 this->reg = 0; 208 this->reg_offset = 0; 209 this->negate = 0; 210 this->abs = 0; 211 this->hw_reg = -1; 212 } 213 214 /** Generic unset register constructor. */ 215 fs_reg() 216 { 217 init(); 218 this->file = BAD_FILE; 219 } 220 221 /** Immediate value constructor. */ 222 fs_reg(float f) 223 { 224 init(); 225 this->file = IMM; 226 this->type = BRW_REGISTER_TYPE_F; 227 this->imm.f = f; 228 } 229 230 /** Immediate value constructor. */ 231 fs_reg(int32_t i) 232 { 233 init(); 234 this->file = IMM; 235 this->type = BRW_REGISTER_TYPE_D; 236 this->imm.i = i; 237 } 238 239 /** Immediate value constructor. */ 240 fs_reg(uint32_t u) 241 { 242 init(); 243 this->file = IMM; 244 this->type = BRW_REGISTER_TYPE_UD; 245 this->imm.u = u; 246 } 247 248 /** Fixed brw_reg Immediate value constructor. */ 249 fs_reg(struct brw_reg fixed_hw_reg) 250 { 251 init(); 252 this->file = FIXED_HW_REG; 253 this->fixed_hw_reg = fixed_hw_reg; 254 this->type = fixed_hw_reg.type; 255 } 256 257 fs_reg(enum register_file file, int hw_reg); 258 fs_reg(class fs_visitor *v, const struct glsl_type *type); 259 260 /** Register file: ARF, GRF, MRF, IMM. */ 261 enum register_file file; 262 /** Abstract register number. 0 = fixed hw reg */ 263 int reg; 264 /** Offset within the abstract register. */ 265 int reg_offset; 266 /** HW register number. Generally unset until register allocation. */ 267 int hw_reg; 268 /** Register type. BRW_REGISTER_TYPE_* */ 269 int type; 270 bool negate; 271 bool abs; 272 struct brw_reg fixed_hw_reg; 273 274 /** Value for file == BRW_IMMMEDIATE_FILE */ 275 union { 276 int32_t i; 277 uint32_t u; 278 float f; 279 } imm; 280}; 281 282static const fs_reg reg_undef; 283static const fs_reg reg_null(ARF, BRW_ARF_NULL); 284 285class fs_inst : public exec_node { 286public: 287 /* Callers of this talloc-based new need not call delete. It's 288 * easier to just talloc_free 'ctx' (or any of its ancestors). */ 289 static void* operator new(size_t size, void *ctx) 290 { 291 void *node; 292 293 node = talloc_zero_size(ctx, size); 294 assert(node != NULL); 295 296 return node; 297 } 298 299 void init() 300 { 301 this->opcode = BRW_OPCODE_NOP; 302 this->saturate = false; 303 this->conditional_mod = BRW_CONDITIONAL_NONE; 304 this->predicated = false; 305 this->sampler = 0; 306 this->shadow_compare = false; 307 } 308 309 fs_inst() 310 { 311 init(); 312 } 313 314 fs_inst(int opcode) 315 { 316 init(); 317 this->opcode = opcode; 318 } 319 320 fs_inst(int opcode, fs_reg dst, fs_reg src0) 321 { 322 init(); 323 this->opcode = opcode; 324 this->dst = dst; 325 this->src[0] = src0; 326 } 327 328 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1) 329 { 330 init(); 331 this->opcode = opcode; 332 this->dst = dst; 333 this->src[0] = src0; 334 this->src[1] = src1; 335 } 336 337 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) 338 { 339 init(); 340 this->opcode = opcode; 341 this->dst = dst; 342 this->src[0] = src0; 343 this->src[1] = src1; 344 this->src[2] = src2; 345 } 346 347 int opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ 348 fs_reg dst; 349 fs_reg src[3]; 350 bool saturate; 351 bool predicated; 352 int conditional_mod; /**< BRW_CONDITIONAL_* */ 353 354 int mlen; /** SEND message length */ 355 int sampler; 356 bool shadow_compare; 357 358 /** @{ 359 * Annotation for the generated IR. One of the two can be set. 360 */ 361 ir_instruction *ir; 362 const char *annotation; 363 /** @} */ 364}; 365 366class fs_visitor : public ir_visitor 367{ 368public: 369 370 fs_visitor(struct brw_wm_compile *c, struct brw_shader *shader) 371 { 372 this->c = c; 373 this->p = &c->func; 374 this->brw = p->brw; 375 this->intel = &brw->intel; 376 this->ctx = &intel->ctx; 377 this->mem_ctx = talloc_new(NULL); 378 this->shader = shader; 379 this->fail = false; 380 this->next_abstract_grf = 1; 381 this->variable_ht = hash_table_ctor(0, 382 hash_table_pointer_hash, 383 hash_table_pointer_compare); 384 385 this->frag_color = NULL; 386 this->frag_data = NULL; 387 this->frag_depth = NULL; 388 this->first_non_payload_grf = 0; 389 390 this->current_annotation = NULL; 391 this->annotation_string = NULL; 392 this->annotation_ir = NULL; 393 } 394 ~fs_visitor() 395 { 396 talloc_free(this->mem_ctx); 397 hash_table_dtor(this->variable_ht); 398 } 399 400 fs_reg *variable_storage(ir_variable *var); 401 402 void visit(ir_variable *ir); 403 void visit(ir_assignment *ir); 404 void visit(ir_dereference_variable *ir); 405 void visit(ir_dereference_record *ir); 406 void visit(ir_dereference_array *ir); 407 void visit(ir_expression *ir); 408 void visit(ir_texture *ir); 409 void visit(ir_if *ir); 410 void visit(ir_constant *ir); 411 void visit(ir_swizzle *ir); 412 void visit(ir_return *ir); 413 void visit(ir_loop *ir); 414 void visit(ir_loop_jump *ir); 415 void visit(ir_discard *ir); 416 void visit(ir_call *ir); 417 void visit(ir_function *ir); 418 void visit(ir_function_signature *ir); 419 420 fs_inst *emit(fs_inst inst); 421 void assign_curb_setup(); 422 void assign_urb_setup(); 423 void assign_regs(); 424 void generate_code(); 425 void generate_fb_write(fs_inst *inst); 426 void generate_linterp(fs_inst *inst, struct brw_reg dst, 427 struct brw_reg *src); 428 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src); 429 void generate_math(fs_inst *inst, struct brw_reg dst, struct brw_reg *src); 430 void generate_discard(fs_inst *inst); 431 432 void emit_dummy_fs(); 433 void emit_interpolation(); 434 void emit_pinterp(int location); 435 void emit_fb_writes(); 436 437 struct brw_reg interp_reg(int location, int channel); 438 439 struct brw_context *brw; 440 struct intel_context *intel; 441 GLcontext *ctx; 442 struct brw_wm_compile *c; 443 struct brw_compile *p; 444 struct brw_shader *shader; 445 void *mem_ctx; 446 exec_list instructions; 447 int next_abstract_grf; 448 struct hash_table *variable_ht; 449 ir_variable *frag_color, *frag_data, *frag_depth; 450 int first_non_payload_grf; 451 452 /** @{ debug annotation info */ 453 const char *current_annotation; 454 ir_instruction *base_ir; 455 const char **annotation_string; 456 ir_instruction **annotation_ir; 457 /** @} */ 458 459 bool fail; 460 461 /* Result of last visit() method. */ 462 fs_reg result; 463 464 fs_reg pixel_x; 465 fs_reg pixel_y; 466 fs_reg pixel_w; 467 fs_reg delta_x; 468 fs_reg delta_y; 469 fs_reg interp_attrs[64]; 470 471 int grf_used; 472 473}; 474 475/** Fixed HW reg constructor. */ 476fs_reg::fs_reg(enum register_file file, int hw_reg) 477{ 478 init(); 479 this->file = file; 480 this->hw_reg = hw_reg; 481 this->type = BRW_REGISTER_TYPE_F; 482} 483 484/** Automatic reg constructor. */ 485fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type) 486{ 487 init(); 488 489 this->file = GRF; 490 this->reg = v->next_abstract_grf; 491 this->reg_offset = 0; 492 v->next_abstract_grf += type_size(type); 493 494 switch (type->base_type) { 495 case GLSL_TYPE_FLOAT: 496 this->type = BRW_REGISTER_TYPE_F; 497 break; 498 case GLSL_TYPE_INT: 499 case GLSL_TYPE_BOOL: 500 this->type = BRW_REGISTER_TYPE_D; 501 break; 502 case GLSL_TYPE_UINT: 503 this->type = BRW_REGISTER_TYPE_UD; 504 break; 505 default: 506 assert(!"not reached"); 507 this->type = BRW_REGISTER_TYPE_F; 508 break; 509 } 510} 511 512fs_reg * 513fs_visitor::variable_storage(ir_variable *var) 514{ 515 return (fs_reg *)hash_table_find(this->variable_ht, var); 516} 517 518void 519fs_visitor::visit(ir_variable *ir) 520{ 521 fs_reg *reg = NULL; 522 523 if (strcmp(ir->name, "gl_FragColor") == 0) { 524 this->frag_color = ir; 525 } else if (strcmp(ir->name, "gl_FragData") == 0) { 526 this->frag_data = ir; 527 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 528 this->frag_depth = ir; 529 assert(!"FINISHME: this hangs currently."); 530 } 531 532 if (ir->mode == ir_var_in) { 533 reg = &this->interp_attrs[ir->location]; 534 } 535 536 if (ir->mode == ir_var_uniform) { 537 const float *vec_values; 538 int param_index = c->prog_data.nr_params; 539 540 /* FINISHME: This is wildly incomplete. */ 541 assert(ir->type->is_scalar() || ir->type->is_vector() || 542 ir->type->is_sampler()); 543 544 const struct gl_program *fp = &this->brw->fragment_program->Base; 545 /* Our support for uniforms is piggy-backed on the struct 546 * gl_fragment_program, because that's where the values actually 547 * get stored, rather than in some global gl_shader_program uniform 548 * store. 549 */ 550 vec_values = fp->Parameters->ParameterValues[ir->location]; 551 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 552 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[i]; 553 } 554 555 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 556 } 557 558 if (!reg) 559 reg = new(this->mem_ctx) fs_reg(this, ir->type); 560 561 hash_table_insert(this->variable_ht, reg, ir); 562} 563 564void 565fs_visitor::visit(ir_dereference_variable *ir) 566{ 567 fs_reg *reg = variable_storage(ir->var); 568 this->result = *reg; 569} 570 571void 572fs_visitor::visit(ir_dereference_record *ir) 573{ 574 assert(!"FINISHME"); 575} 576 577void 578fs_visitor::visit(ir_dereference_array *ir) 579{ 580 ir_constant *index; 581 int element_size; 582 583 ir->array->accept(this); 584 index = ir->array_index->as_constant(); 585 586 if (ir->type->is_matrix()) { 587 element_size = ir->type->vector_elements; 588 } else { 589 element_size = type_size(ir->type); 590 } 591 592 if (index) { 593 assert(this->result.file == UNIFORM || 594 (this->result.file == GRF && 595 this->result.reg != 0)); 596 this->result.reg_offset += index->value.i[0] * element_size; 597 } else { 598 assert(!"FINISHME: non-constant matrix column"); 599 } 600} 601 602void 603fs_visitor::visit(ir_expression *ir) 604{ 605 unsigned int operand; 606 fs_reg op[2], temp; 607 fs_reg result; 608 fs_inst *inst; 609 610 for (operand = 0; operand < ir->get_num_operands(); operand++) { 611 ir->operands[operand]->accept(this); 612 if (this->result.file == BAD_FILE) { 613 ir_print_visitor v; 614 printf("Failed to get tree for expression operand:\n"); 615 ir->operands[operand]->accept(&v); 616 this->fail = true; 617 } 618 op[operand] = this->result; 619 620 /* Matrix expression operands should have been broken down to vector 621 * operations already. 622 */ 623 assert(!ir->operands[operand]->type->is_matrix()); 624 /* And then those vector operands should have been broken down to scalar. 625 */ 626 assert(!ir->operands[operand]->type->is_vector()); 627 } 628 629 /* Storage for our result. If our result goes into an assignment, it will 630 * just get copy-propagated out, so no worries. 631 */ 632 this->result = fs_reg(this, ir->type); 633 634 switch (ir->operation) { 635 case ir_unop_logic_not: 636 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], fs_reg(-1))); 637 break; 638 case ir_unop_neg: 639 op[0].negate = ~op[0].negate; 640 this->result = op[0]; 641 break; 642 case ir_unop_abs: 643 op[0].abs = true; 644 this->result = op[0]; 645 break; 646 case ir_unop_sign: 647 temp = fs_reg(this, ir->type); 648 649 emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(0.0f))); 650 651 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f))); 652 inst->conditional_mod = BRW_CONDITIONAL_G; 653 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(1.0f))); 654 inst->predicated = true; 655 656 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f))); 657 inst->conditional_mod = BRW_CONDITIONAL_L; 658 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f))); 659 inst->predicated = true; 660 661 break; 662 case ir_unop_rcp: 663 emit(fs_inst(FS_OPCODE_RCP, this->result, op[0])); 664 break; 665 666 case ir_unop_exp2: 667 emit(fs_inst(FS_OPCODE_EXP2, this->result, op[0])); 668 break; 669 case ir_unop_log2: 670 emit(fs_inst(FS_OPCODE_LOG2, this->result, op[0])); 671 break; 672 case ir_unop_exp: 673 case ir_unop_log: 674 assert(!"not reached: should be handled by ir_explog_to_explog2"); 675 break; 676 case ir_unop_sin: 677 emit(fs_inst(FS_OPCODE_SIN, this->result, op[0])); 678 break; 679 case ir_unop_cos: 680 emit(fs_inst(FS_OPCODE_COS, this->result, op[0])); 681 break; 682 683 case ir_unop_dFdx: 684 emit(fs_inst(FS_OPCODE_DDX, this->result, op[0])); 685 break; 686 case ir_unop_dFdy: 687 emit(fs_inst(FS_OPCODE_DDY, this->result, op[0])); 688 break; 689 690 case ir_binop_add: 691 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], op[1])); 692 break; 693 case ir_binop_sub: 694 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 695 break; 696 697 case ir_binop_mul: 698 emit(fs_inst(BRW_OPCODE_MUL, this->result, op[0], op[1])); 699 break; 700 case ir_binop_div: 701 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 702 break; 703 case ir_binop_mod: 704 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 705 break; 706 707 case ir_binop_less: 708 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 709 inst->conditional_mod = BRW_CONDITIONAL_L; 710 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 711 break; 712 case ir_binop_greater: 713 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 714 inst->conditional_mod = BRW_CONDITIONAL_G; 715 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 716 break; 717 case ir_binop_lequal: 718 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 719 inst->conditional_mod = BRW_CONDITIONAL_LE; 720 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 721 break; 722 case ir_binop_gequal: 723 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 724 inst->conditional_mod = BRW_CONDITIONAL_GE; 725 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 726 break; 727 case ir_binop_equal: 728 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 729 inst->conditional_mod = BRW_CONDITIONAL_Z; 730 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 731 break; 732 case ir_binop_nequal: 733 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 734 inst->conditional_mod = BRW_CONDITIONAL_NZ; 735 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 736 break; 737 738 case ir_binop_logic_xor: 739 emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1])); 740 break; 741 742 case ir_binop_logic_or: 743 emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1])); 744 break; 745 746 case ir_binop_logic_and: 747 emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1])); 748 break; 749 750 case ir_binop_dot: 751 case ir_binop_cross: 752 case ir_unop_any: 753 assert(!"not reached: should be handled by brw_channel_expressions"); 754 break; 755 756 case ir_unop_noise: 757 assert(!"not reached: should be handled by lower_noise"); 758 break; 759 760 case ir_unop_sqrt: 761 emit(fs_inst(FS_OPCODE_SQRT, this->result, op[0])); 762 break; 763 764 case ir_unop_rsq: 765 emit(fs_inst(FS_OPCODE_RSQ, this->result, op[0])); 766 break; 767 768 case ir_unop_i2f: 769 case ir_unop_b2f: 770 case ir_unop_b2i: 771 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0])); 772 break; 773 case ir_unop_f2i: 774 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0])); 775 break; 776 case ir_unop_f2b: 777 case ir_unop_i2b: 778 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f))); 779 inst->conditional_mod = BRW_CONDITIONAL_NZ; 780 781 case ir_unop_trunc: 782 emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0])); 783 break; 784 case ir_unop_ceil: 785 op[0].negate = ~op[0].negate; 786 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0])); 787 this->result.negate = true; 788 break; 789 case ir_unop_floor: 790 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0])); 791 break; 792 case ir_unop_fract: 793 inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0])); 794 break; 795 796 case ir_binop_min: 797 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 798 inst->conditional_mod = BRW_CONDITIONAL_L; 799 800 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1])); 801 inst->predicated = true; 802 break; 803 case ir_binop_max: 804 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 805 inst->conditional_mod = BRW_CONDITIONAL_G; 806 807 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1])); 808 inst->predicated = true; 809 break; 810 811 case ir_binop_pow: 812 inst = emit(fs_inst(FS_OPCODE_POW, this->result, op[0], op[1])); 813 break; 814 815 case ir_unop_bit_not: 816 case ir_unop_u2f: 817 case ir_binop_lshift: 818 case ir_binop_rshift: 819 case ir_binop_bit_and: 820 case ir_binop_bit_xor: 821 case ir_binop_bit_or: 822 assert(!"GLSL 1.30 features unsupported"); 823 break; 824 } 825} 826 827void 828fs_visitor::visit(ir_assignment *ir) 829{ 830 struct fs_reg l, r; 831 int i; 832 int write_mask; 833 fs_inst *inst; 834 835 /* FINISHME: arrays on the lhs */ 836 ir->lhs->accept(this); 837 l = this->result; 838 839 ir->rhs->accept(this); 840 r = this->result; 841 842 /* FINISHME: This should really set to the correct maximal writemask for each 843 * FINISHME: component written (in the loops below). This case can only 844 * FINISHME: occur for matrices, arrays, and structures. 845 */ 846 if (ir->write_mask == 0) { 847 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector()); 848 write_mask = WRITEMASK_XYZW; 849 } else { 850 assert(ir->lhs->type->is_vector() || ir->lhs->type->is_scalar()); 851 write_mask = ir->write_mask; 852 } 853 854 assert(l.file != BAD_FILE); 855 assert(r.file != BAD_FILE); 856 857 if (ir->condition) { 858 /* Get the condition bool into the predicate. */ 859 ir->condition->accept(this); 860 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, fs_reg(0))); 861 inst->conditional_mod = BRW_CONDITIONAL_NZ; 862 } 863 864 for (i = 0; i < type_size(ir->lhs->type); i++) { 865 if (i >= 4 || (write_mask & (1 << i))) { 866 inst = emit(fs_inst(BRW_OPCODE_MOV, l, r)); 867 if (ir->condition) 868 inst->predicated = true; 869 } 870 l.reg_offset++; 871 r.reg_offset++; 872 } 873} 874 875void 876fs_visitor::visit(ir_texture *ir) 877{ 878 int base_mrf = 2; 879 fs_inst *inst = NULL; 880 unsigned int mlen = 0; 881 882 ir->coordinate->accept(this); 883 fs_reg coordinate = this->result; 884 885 if (ir->projector) { 886 fs_reg inv_proj = fs_reg(this, glsl_type::float_type); 887 888 ir->projector->accept(this); 889 emit(fs_inst(FS_OPCODE_RCP, inv_proj, this->result)); 890 891 fs_reg proj_coordinate = fs_reg(this, ir->coordinate->type); 892 for (unsigned int i = 0; i < ir->coordinate->type->vector_elements; i++) { 893 emit(fs_inst(BRW_OPCODE_MUL, proj_coordinate, coordinate, inv_proj)); 894 coordinate.reg_offset++; 895 proj_coordinate.reg_offset++; 896 } 897 proj_coordinate.reg_offset = 0; 898 899 coordinate = proj_coordinate; 900 } 901 902 for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) { 903 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate)); 904 coordinate.reg_offset++; 905 } 906 907 /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */ 908 if (intel->gen < 5) 909 mlen = 3; 910 911 if (ir->shadow_comparitor) { 912 /* For shadow comparisons, we have to supply u,v,r. */ 913 mlen = 3; 914 915 ir->shadow_comparitor->accept(this); 916 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result)); 917 mlen++; 918 } 919 920 /* Do we ever want to handle writemasking on texture samples? Is it 921 * performance relevant? 922 */ 923 fs_reg dst = fs_reg(this, glsl_type::vec4_type); 924 925 switch (ir->op) { 926 case ir_tex: 927 inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf))); 928 break; 929 case ir_txb: 930 ir->lod_info.bias->accept(this); 931 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result)); 932 mlen++; 933 934 inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf))); 935 break; 936 case ir_txl: 937 ir->lod_info.lod->accept(this); 938 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result)); 939 mlen++; 940 941 inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf))); 942 break; 943 case ir_txd: 944 case ir_txf: 945 assert(!"GLSL 1.30 features unsupported"); 946 break; 947 } 948 949 this->result = dst; 950 951 if (ir->shadow_comparitor) 952 inst->shadow_compare = true; 953 inst->mlen = mlen; 954} 955 956void 957fs_visitor::visit(ir_swizzle *ir) 958{ 959 ir->val->accept(this); 960 fs_reg val = this->result; 961 962 fs_reg result = fs_reg(this, ir->type); 963 this->result = result; 964 965 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 966 fs_reg channel = val; 967 int swiz = 0; 968 969 switch (i) { 970 case 0: 971 swiz = ir->mask.x; 972 break; 973 case 1: 974 swiz = ir->mask.y; 975 break; 976 case 2: 977 swiz = ir->mask.z; 978 break; 979 case 3: 980 swiz = ir->mask.w; 981 break; 982 } 983 984 channel.reg_offset += swiz; 985 emit(fs_inst(BRW_OPCODE_MOV, result, channel)); 986 result.reg_offset++; 987 } 988} 989 990void 991fs_visitor::visit(ir_discard *ir) 992{ 993 assert(ir->condition == NULL); /* FINISHME */ 994 995 emit(fs_inst(FS_OPCODE_DISCARD)); 996} 997 998void 999fs_visitor::visit(ir_constant *ir) 1000{ 1001 fs_reg reg(this, ir->type); 1002 this->result = reg; 1003 1004 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1005 switch (ir->type->base_type) { 1006 case GLSL_TYPE_FLOAT: 1007 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.f[i]))); 1008 break; 1009 case GLSL_TYPE_UINT: 1010 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.u[i]))); 1011 break; 1012 case GLSL_TYPE_INT: 1013 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.i[i]))); 1014 break; 1015 case GLSL_TYPE_BOOL: 1016 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg((int)ir->value.b[i]))); 1017 break; 1018 default: 1019 assert(!"Non-float/uint/int/bool constant"); 1020 } 1021 reg.reg_offset++; 1022 } 1023} 1024 1025void 1026fs_visitor::visit(ir_if *ir) 1027{ 1028 fs_inst *inst; 1029 1030 /* Don't point the annotation at the if statement, because then it plus 1031 * the then and else blocks get printed. 1032 */ 1033 this->base_ir = ir->condition; 1034 1035 /* Generate the condition into the condition code. */ 1036 ir->condition->accept(this); 1037 inst = emit(fs_inst(BRW_OPCODE_MOV, fs_reg(brw_null_reg()), this->result)); 1038 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1039 1040 inst = emit(fs_inst(BRW_OPCODE_IF)); 1041 inst->predicated = true; 1042 1043 foreach_iter(exec_list_iterator, iter, ir->then_instructions) { 1044 ir_instruction *ir = (ir_instruction *)iter.get(); 1045 this->base_ir = ir; 1046 1047 ir->accept(this); 1048 } 1049 1050 if (!ir->else_instructions.is_empty()) { 1051 emit(fs_inst(BRW_OPCODE_ELSE)); 1052 1053 foreach_iter(exec_list_iterator, iter, ir->else_instructions) { 1054 ir_instruction *ir = (ir_instruction *)iter.get(); 1055 this->base_ir = ir; 1056 1057 ir->accept(this); 1058 } 1059 } 1060 1061 emit(fs_inst(BRW_OPCODE_ENDIF)); 1062} 1063 1064void 1065fs_visitor::visit(ir_loop *ir) 1066{ 1067 assert(!ir->from); 1068 assert(!ir->to); 1069 assert(!ir->increment); 1070 assert(!ir->counter); 1071 1072 emit(fs_inst(BRW_OPCODE_DO)); 1073 1074 /* Start a safety counter. If the user messed up their loop 1075 * counting, we don't want to hang the GPU. 1076 */ 1077 fs_reg max_iter = fs_reg(this, glsl_type::int_type); 1078 emit(fs_inst(BRW_OPCODE_MOV, max_iter, fs_reg(10000))); 1079 1080 foreach_iter(exec_list_iterator, iter, ir->body_instructions) { 1081 ir_instruction *ir = (ir_instruction *)iter.get(); 1082 fs_inst *inst; 1083 1084 this->base_ir = ir; 1085 ir->accept(this); 1086 1087 /* Check the maximum loop iters counter. */ 1088 inst = emit(fs_inst(BRW_OPCODE_ADD, max_iter, max_iter, fs_reg(-1))); 1089 inst->conditional_mod = BRW_CONDITIONAL_Z; 1090 1091 inst = emit(fs_inst(BRW_OPCODE_BREAK)); 1092 inst->predicated = true; 1093 } 1094 1095 emit(fs_inst(BRW_OPCODE_WHILE)); 1096} 1097 1098void 1099fs_visitor::visit(ir_loop_jump *ir) 1100{ 1101 switch (ir->mode) { 1102 case ir_loop_jump::jump_break: 1103 emit(fs_inst(BRW_OPCODE_BREAK)); 1104 break; 1105 case ir_loop_jump::jump_continue: 1106 emit(fs_inst(BRW_OPCODE_CONTINUE)); 1107 break; 1108 } 1109} 1110 1111void 1112fs_visitor::visit(ir_call *ir) 1113{ 1114 assert(!"FINISHME"); 1115} 1116 1117void 1118fs_visitor::visit(ir_return *ir) 1119{ 1120 assert(!"FINISHME"); 1121} 1122 1123void 1124fs_visitor::visit(ir_function *ir) 1125{ 1126 /* Ignore function bodies other than main() -- we shouldn't see calls to 1127 * them since they should all be inlined before we get to ir_to_mesa. 1128 */ 1129 if (strcmp(ir->name, "main") == 0) { 1130 const ir_function_signature *sig; 1131 exec_list empty; 1132 1133 sig = ir->matching_signature(&empty); 1134 1135 assert(sig); 1136 1137 foreach_iter(exec_list_iterator, iter, sig->body) { 1138 ir_instruction *ir = (ir_instruction *)iter.get(); 1139 this->base_ir = ir; 1140 1141 ir->accept(this); 1142 } 1143 } 1144} 1145 1146void 1147fs_visitor::visit(ir_function_signature *ir) 1148{ 1149 assert(!"not reached"); 1150 (void)ir; 1151} 1152 1153fs_inst * 1154fs_visitor::emit(fs_inst inst) 1155{ 1156 fs_inst *list_inst = new(mem_ctx) fs_inst; 1157 *list_inst = inst; 1158 1159 list_inst->annotation = this->current_annotation; 1160 list_inst->ir = this->base_ir; 1161 1162 this->instructions.push_tail(list_inst); 1163 1164 return list_inst; 1165} 1166 1167/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1168void 1169fs_visitor::emit_dummy_fs() 1170{ 1171 /* Everyone's favorite color. */ 1172 emit(fs_inst(BRW_OPCODE_MOV, 1173 fs_reg(MRF, 2), 1174 fs_reg(1.0f))); 1175 emit(fs_inst(BRW_OPCODE_MOV, 1176 fs_reg(MRF, 3), 1177 fs_reg(0.0f))); 1178 emit(fs_inst(BRW_OPCODE_MOV, 1179 fs_reg(MRF, 4), 1180 fs_reg(1.0f))); 1181 emit(fs_inst(BRW_OPCODE_MOV, 1182 fs_reg(MRF, 5), 1183 fs_reg(0.0f))); 1184 1185 fs_inst *write; 1186 write = emit(fs_inst(FS_OPCODE_FB_WRITE, 1187 fs_reg(0), 1188 fs_reg(0))); 1189} 1190 1191/* The register location here is relative to the start of the URB 1192 * data. It will get adjusted to be a real location before 1193 * generate_code() time. 1194 */ 1195struct brw_reg 1196fs_visitor::interp_reg(int location, int channel) 1197{ 1198 int regnr = location * 2 + channel / 2; 1199 int stride = (channel & 1) * 4; 1200 1201 return brw_vec1_grf(regnr, stride); 1202} 1203 1204/** Emits the interpolation for the varying inputs. */ 1205void 1206fs_visitor::emit_interpolation() 1207{ 1208 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1209 /* For now, the source regs for the setup URB data will be unset, 1210 * since we don't know until codegen how many push constants we'll 1211 * use, and therefore what the setup URB offset is. 1212 */ 1213 fs_reg src_reg = reg_undef; 1214 1215 this->current_annotation = "compute pixel centers"; 1216 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1217 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1218 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1219 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1220 emit(fs_inst(BRW_OPCODE_ADD, 1221 this->pixel_x, 1222 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1223 fs_reg(brw_imm_v(0x10101010)))); 1224 emit(fs_inst(BRW_OPCODE_ADD, 1225 this->pixel_y, 1226 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1227 fs_reg(brw_imm_v(0x11001100)))); 1228 1229 this->current_annotation = "compute pixel deltas from v0"; 1230 this->delta_x = fs_reg(this, glsl_type::float_type); 1231 this->delta_y = fs_reg(this, glsl_type::float_type); 1232 emit(fs_inst(BRW_OPCODE_ADD, 1233 this->delta_x, 1234 this->pixel_x, 1235 fs_reg(negate(brw_vec1_grf(1, 0))))); 1236 emit(fs_inst(BRW_OPCODE_ADD, 1237 this->delta_y, 1238 this->pixel_y, 1239 fs_reg(brw_vec1_grf(1, 1)))); 1240 1241 this->current_annotation = "compute pos.w and 1/pos.w"; 1242 /* Compute wpos. Unlike many other varying inputs, we usually need it 1243 * to produce 1/w, and the varying variable wouldn't show up. 1244 */ 1245 fs_reg wpos = fs_reg(this, glsl_type::vec4_type); 1246 this->interp_attrs[FRAG_ATTRIB_WPOS] = wpos; 1247 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_x)); /* FINISHME: ARB_fcc */ 1248 wpos.reg_offset++; 1249 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y)); /* FINISHME: ARB_fcc */ 1250 wpos.reg_offset++; 1251 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y, 1252 interp_reg(FRAG_ATTRIB_WPOS, 2))); 1253 wpos.reg_offset++; 1254 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y, 1255 interp_reg(FRAG_ATTRIB_WPOS, 3))); 1256 /* Compute the pixel W value from wpos.w. */ 1257 this->pixel_w = fs_reg(this, glsl_type::float_type); 1258 emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos)); 1259 1260 /* FINISHME: gl_FrontFacing */ 1261 1262 foreach_iter(exec_list_iterator, iter, *this->shader->ir) { 1263 ir_instruction *ir = (ir_instruction *)iter.get(); 1264 ir_variable *var = ir->as_variable(); 1265 1266 if (!var) 1267 continue; 1268 1269 if (var->mode != ir_var_in) 1270 continue; 1271 1272 /* If it's already set up (WPOS), skip. */ 1273 if (var->location == 0) 1274 continue; 1275 1276 this->current_annotation = talloc_asprintf(this->mem_ctx, 1277 "interpolate %s " 1278 "(FRAG_ATTRIB[%d])", 1279 var->name, 1280 var->location); 1281 emit_pinterp(var->location); 1282 } 1283 this->current_annotation = NULL; 1284} 1285 1286void 1287fs_visitor::emit_pinterp(int location) 1288{ 1289 fs_reg interp_attr = fs_reg(this, glsl_type::vec4_type); 1290 this->interp_attrs[location] = interp_attr; 1291 1292 for (unsigned int i = 0; i < 4; i++) { 1293 struct brw_reg interp = interp_reg(location, i); 1294 emit(fs_inst(FS_OPCODE_LINTERP, 1295 interp_attr, 1296 this->delta_x, 1297 this->delta_y, 1298 fs_reg(interp))); 1299 interp_attr.reg_offset++; 1300 } 1301 interp_attr.reg_offset -= 4; 1302 1303 for (unsigned int i = 0; i < 4; i++) { 1304 emit(fs_inst(BRW_OPCODE_MUL, 1305 interp_attr, 1306 interp_attr, 1307 this->pixel_w)); 1308 interp_attr.reg_offset++; 1309 } 1310} 1311 1312void 1313fs_visitor::emit_fb_writes() 1314{ 1315 this->current_annotation = "FB write"; 1316 1317 assert(this->frag_color || !"FINISHME: MRT"); 1318 fs_reg color = *(variable_storage(this->frag_color)); 1319 1320 for (int i = 0; i < 4; i++) { 1321 emit(fs_inst(BRW_OPCODE_MOV, 1322 fs_reg(MRF, 2 + i), 1323 color)); 1324 color.reg_offset++; 1325 } 1326 1327 emit(fs_inst(FS_OPCODE_FB_WRITE, 1328 fs_reg(0), 1329 fs_reg(0))); 1330 1331 this->current_annotation = NULL; 1332} 1333 1334void 1335fs_visitor::generate_fb_write(fs_inst *inst) 1336{ 1337 GLboolean eot = 1; /* FINISHME: MRT */ 1338 /* FINISHME: AADS */ 1339 1340 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied 1341 * move, here's g1. 1342 */ 1343 brw_push_insn_state(p); 1344 brw_set_mask_control(p, BRW_MASK_DISABLE); 1345 brw_set_compression_control(p, BRW_COMPRESSION_NONE); 1346 brw_MOV(p, 1347 brw_message_reg(1), 1348 brw_vec8_grf(1, 0)); 1349 brw_pop_insn_state(p); 1350 1351 int nr = 2 + 4; 1352 1353 brw_fb_WRITE(p, 1354 8, /* dispatch_width */ 1355 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW), 1356 0, /* base MRF */ 1357 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), 1358 0, /* FINISHME: MRT target */ 1359 nr, 1360 0, 1361 eot); 1362} 1363 1364void 1365fs_visitor::generate_linterp(fs_inst *inst, 1366 struct brw_reg dst, struct brw_reg *src) 1367{ 1368 struct brw_reg delta_x = src[0]; 1369 struct brw_reg delta_y = src[1]; 1370 struct brw_reg interp = src[2]; 1371 1372 if (brw->has_pln && 1373 delta_y.nr == delta_x.nr + 1 && 1374 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) { 1375 brw_PLN(p, dst, interp, delta_x); 1376 } else { 1377 brw_LINE(p, brw_null_reg(), interp, delta_x); 1378 brw_MAC(p, dst, suboffset(interp, 1), delta_y); 1379 } 1380} 1381 1382void 1383fs_visitor::generate_math(fs_inst *inst, 1384 struct brw_reg dst, struct brw_reg *src) 1385{ 1386 int op; 1387 1388 switch (inst->opcode) { 1389 case FS_OPCODE_RCP: 1390 op = BRW_MATH_FUNCTION_INV; 1391 break; 1392 case FS_OPCODE_RSQ: 1393 op = BRW_MATH_FUNCTION_RSQ; 1394 break; 1395 case FS_OPCODE_SQRT: 1396 op = BRW_MATH_FUNCTION_SQRT; 1397 break; 1398 case FS_OPCODE_EXP2: 1399 op = BRW_MATH_FUNCTION_EXP; 1400 break; 1401 case FS_OPCODE_LOG2: 1402 op = BRW_MATH_FUNCTION_LOG; 1403 break; 1404 case FS_OPCODE_POW: 1405 op = BRW_MATH_FUNCTION_POW; 1406 break; 1407 case FS_OPCODE_SIN: 1408 op = BRW_MATH_FUNCTION_SIN; 1409 break; 1410 case FS_OPCODE_COS: 1411 op = BRW_MATH_FUNCTION_COS; 1412 break; 1413 default: 1414 assert(!"not reached: unknown math function"); 1415 op = 0; 1416 break; 1417 } 1418 1419 if (inst->opcode == FS_OPCODE_POW) { 1420 brw_MOV(p, brw_message_reg(3), src[1]); 1421 } 1422 1423 brw_math(p, dst, 1424 op, 1425 inst->saturate ? BRW_MATH_SATURATE_SATURATE : 1426 BRW_MATH_SATURATE_NONE, 1427 2, src[0], 1428 BRW_MATH_DATA_VECTOR, 1429 BRW_MATH_PRECISION_FULL); 1430} 1431 1432void 1433fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) 1434{ 1435 int msg_type = -1; 1436 int rlen = 4; 1437 1438 if (intel->gen == 5) { 1439 switch (inst->opcode) { 1440 case FS_OPCODE_TEX: 1441 if (inst->shadow_compare) { 1442 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5; 1443 } else { 1444 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5; 1445 } 1446 break; 1447 case FS_OPCODE_TXB: 1448 if (inst->shadow_compare) { 1449 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5; 1450 } else { 1451 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5; 1452 } 1453 break; 1454 } 1455 } else { 1456 switch (inst->opcode) { 1457 case FS_OPCODE_TEX: 1458 /* Note that G45 and older determines shadow compare and dispatch width 1459 * from message length for most messages. 1460 */ 1461 if (inst->shadow_compare) { 1462 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE; 1463 } else { 1464 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE; 1465 } 1466 case FS_OPCODE_TXB: 1467 if (inst->shadow_compare) { 1468 assert(!"FINISHME: shadow compare with bias."); 1469 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; 1470 } else { 1471 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; 1472 rlen = 8; 1473 } 1474 break; 1475 } 1476 } 1477 assert(msg_type != -1); 1478 1479 /* g0 header. */ 1480 src.nr--; 1481 1482 brw_SAMPLE(p, 1483 retype(dst, BRW_REGISTER_TYPE_UW), 1484 src.nr, 1485 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), 1486 SURF_INDEX_TEXTURE(inst->sampler), 1487 inst->sampler, 1488 WRITEMASK_XYZW, 1489 msg_type, 1490 rlen, 1491 inst->mlen + 1, 1492 0, 1493 1, 1494 BRW_SAMPLER_SIMD_MODE_SIMD8); 1495} 1496 1497void 1498fs_visitor::generate_discard(fs_inst *inst) 1499{ 1500 struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); 1501 brw_push_insn_state(p); 1502 brw_set_mask_control(p, BRW_MASK_DISABLE); 1503 brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); /* IMASK */ 1504 brw_AND(p, g0, c->emit_mask_reg, g0); 1505 brw_pop_insn_state(p); 1506} 1507 1508static void 1509trivial_assign_reg(int header_size, fs_reg *reg) 1510{ 1511 if (reg->file == GRF && reg->reg != 0) { 1512 reg->hw_reg = header_size + reg->reg - 1 + reg->reg_offset; 1513 reg->reg = 0; 1514 } 1515} 1516 1517void 1518fs_visitor::assign_curb_setup() 1519{ 1520 c->prog_data.first_curbe_grf = c->key.nr_payload_regs; 1521 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8; 1522 1523 if (intel->gen == 5 && (c->prog_data.first_curbe_grf + 1524 c->prog_data.curb_read_length) & 1) { 1525 /* Align the start of the interpolation coefficients so that we can use 1526 * the PLN instruction. 1527 */ 1528 c->prog_data.first_curbe_grf++; 1529 } 1530 1531 /* Map the offsets in the UNIFORM file to fixed HW regs. */ 1532 foreach_iter(exec_list_iterator, iter, this->instructions) { 1533 fs_inst *inst = (fs_inst *)iter.get(); 1534 1535 for (unsigned int i = 0; i < 3; i++) { 1536 if (inst->src[i].file == UNIFORM) { 1537 int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset; 1538 struct brw_reg brw_reg = brw_vec1_grf(c->prog_data.first_curbe_grf + 1539 constant_nr / 8, 1540 constant_nr % 8); 1541 1542 inst->src[i].file = FIXED_HW_REG; 1543 inst->src[i].fixed_hw_reg = brw_reg; 1544 } 1545 } 1546 } 1547} 1548 1549void 1550fs_visitor::assign_urb_setup() 1551{ 1552 int urb_start = c->prog_data.first_curbe_grf + c->prog_data.curb_read_length; 1553 int interp_reg_nr[FRAG_ATTRIB_MAX]; 1554 1555 c->prog_data.urb_read_length = 0; 1556 1557 /* Figure out where each of the incoming setup attributes lands. */ 1558 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) { 1559 interp_reg_nr[i] = -1; 1560 1561 if (i != FRAG_ATTRIB_WPOS && 1562 !(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i))) 1563 continue; 1564 1565 /* Each attribute is 4 setup channels, each of which is half a reg. */ 1566 interp_reg_nr[i] = urb_start + c->prog_data.urb_read_length; 1567 c->prog_data.urb_read_length += 2; 1568 } 1569 1570 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses 1571 * the correct setup input. 1572 */ 1573 foreach_iter(exec_list_iterator, iter, this->instructions) { 1574 fs_inst *inst = (fs_inst *)iter.get(); 1575 1576 if (inst->opcode != FS_OPCODE_LINTERP) 1577 continue; 1578 1579 assert(inst->src[2].file == FIXED_HW_REG); 1580 1581 int location = inst->src[2].fixed_hw_reg.nr / 2; 1582 assert(interp_reg_nr[location] != -1); 1583 inst->src[2].fixed_hw_reg.nr = (interp_reg_nr[location] + 1584 (inst->src[2].fixed_hw_reg.nr & 1)); 1585 } 1586 1587 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length; 1588} 1589 1590void 1591fs_visitor::assign_regs() 1592{ 1593 int header_size = this->first_non_payload_grf; 1594 int last_grf = 0; 1595 1596 /* FINISHME: trivial assignment of register numbers */ 1597 foreach_iter(exec_list_iterator, iter, this->instructions) { 1598 fs_inst *inst = (fs_inst *)iter.get(); 1599 1600 trivial_assign_reg(header_size, &inst->dst); 1601 trivial_assign_reg(header_size, &inst->src[0]); 1602 trivial_assign_reg(header_size, &inst->src[1]); 1603 1604 last_grf = MAX2(last_grf, inst->dst.hw_reg); 1605 last_grf = MAX2(last_grf, inst->src[0].hw_reg); 1606 last_grf = MAX2(last_grf, inst->src[1].hw_reg); 1607 } 1608 1609 this->grf_used = last_grf + 1; 1610} 1611 1612static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg) 1613{ 1614 struct brw_reg brw_reg; 1615 1616 switch (reg->file) { 1617 case GRF: 1618 case ARF: 1619 case MRF: 1620 brw_reg = brw_vec8_reg(reg->file, 1621 reg->hw_reg, 0); 1622 brw_reg = retype(brw_reg, reg->type); 1623 break; 1624 case IMM: 1625 switch (reg->type) { 1626 case BRW_REGISTER_TYPE_F: 1627 brw_reg = brw_imm_f(reg->imm.f); 1628 break; 1629 case BRW_REGISTER_TYPE_D: 1630 brw_reg = brw_imm_d(reg->imm.i); 1631 break; 1632 case BRW_REGISTER_TYPE_UD: 1633 brw_reg = brw_imm_ud(reg->imm.u); 1634 break; 1635 default: 1636 assert(!"not reached"); 1637 break; 1638 } 1639 break; 1640 case FIXED_HW_REG: 1641 brw_reg = reg->fixed_hw_reg; 1642 break; 1643 case BAD_FILE: 1644 /* Probably unused. */ 1645 brw_reg = brw_null_reg(); 1646 break; 1647 case UNIFORM: 1648 assert(!"not reached"); 1649 brw_reg = brw_null_reg(); 1650 break; 1651 } 1652 if (reg->abs) 1653 brw_reg = brw_abs(brw_reg); 1654 if (reg->negate) 1655 brw_reg = negate(brw_reg); 1656 1657 return brw_reg; 1658} 1659 1660void 1661fs_visitor::generate_code() 1662{ 1663 unsigned int annotation_len = 0; 1664 int last_native_inst = 0; 1665 struct brw_instruction *if_stack[16], *loop_stack[16]; 1666 int if_stack_depth = 0, loop_stack_depth = 0; 1667 int if_depth_in_loop[16]; 1668 1669 if_depth_in_loop[loop_stack_depth] = 0; 1670 1671 memset(&if_stack, 0, sizeof(if_stack)); 1672 foreach_iter(exec_list_iterator, iter, this->instructions) { 1673 fs_inst *inst = (fs_inst *)iter.get(); 1674 struct brw_reg src[3], dst; 1675 1676 for (unsigned int i = 0; i < 3; i++) { 1677 src[i] = brw_reg_from_fs_reg(&inst->src[i]); 1678 } 1679 dst = brw_reg_from_fs_reg(&inst->dst); 1680 1681 brw_set_conditionalmod(p, inst->conditional_mod); 1682 brw_set_predicate_control(p, inst->predicated); 1683 1684 switch (inst->opcode) { 1685 case BRW_OPCODE_MOV: 1686 brw_MOV(p, dst, src[0]); 1687 break; 1688 case BRW_OPCODE_ADD: 1689 brw_ADD(p, dst, src[0], src[1]); 1690 break; 1691 case BRW_OPCODE_MUL: 1692 brw_MUL(p, dst, src[0], src[1]); 1693 break; 1694 1695 case BRW_OPCODE_FRC: 1696 brw_FRC(p, dst, src[0]); 1697 break; 1698 case BRW_OPCODE_RNDD: 1699 brw_RNDD(p, dst, src[0]); 1700 break; 1701 case BRW_OPCODE_RNDZ: 1702 brw_RNDZ(p, dst, src[0]); 1703 break; 1704 1705 case BRW_OPCODE_AND: 1706 brw_AND(p, dst, src[0], src[1]); 1707 break; 1708 case BRW_OPCODE_OR: 1709 brw_OR(p, dst, src[0], src[1]); 1710 break; 1711 case BRW_OPCODE_XOR: 1712 brw_XOR(p, dst, src[0], src[1]); 1713 break; 1714 1715 case BRW_OPCODE_CMP: 1716 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); 1717 break; 1718 case BRW_OPCODE_SEL: 1719 brw_SEL(p, dst, src[0], src[1]); 1720 break; 1721 1722 case BRW_OPCODE_IF: 1723 assert(if_stack_depth < 16); 1724 if_stack[if_stack_depth] = brw_IF(p, BRW_EXECUTE_8); 1725 if_stack_depth++; 1726 break; 1727 case BRW_OPCODE_ELSE: 1728 if_stack[if_stack_depth - 1] = 1729 brw_ELSE(p, if_stack[if_stack_depth - 1]); 1730 break; 1731 case BRW_OPCODE_ENDIF: 1732 if_stack_depth--; 1733 brw_ENDIF(p , if_stack[if_stack_depth]); 1734 break; 1735 1736 case BRW_OPCODE_DO: 1737 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8); 1738 if_depth_in_loop[loop_stack_depth] = 0; 1739 break; 1740 1741 case BRW_OPCODE_BREAK: 1742 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]); 1743 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 1744 break; 1745 case BRW_OPCODE_CONTINUE: 1746 brw_CONT(p, if_depth_in_loop[loop_stack_depth]); 1747 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 1748 break; 1749 1750 case BRW_OPCODE_WHILE: { 1751 struct brw_instruction *inst0, *inst1; 1752 GLuint br = 1; 1753 1754 if (intel->gen == 5) 1755 br = 2; 1756 1757 assert(loop_stack_depth > 0); 1758 loop_stack_depth--; 1759 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]); 1760 /* patch all the BREAK/CONT instructions from last BGNLOOP */ 1761 while (inst0 > loop_stack[loop_stack_depth]) { 1762 inst0--; 1763 if (inst0->header.opcode == BRW_OPCODE_BREAK && 1764 inst0->bits3.if_else.jump_count == 0) { 1765 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); 1766 } 1767 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE && 1768 inst0->bits3.if_else.jump_count == 0) { 1769 inst0->bits3.if_else.jump_count = br * (inst1 - inst0); 1770 } 1771 } 1772 } 1773 break; 1774 1775 case FS_OPCODE_RCP: 1776 case FS_OPCODE_RSQ: 1777 case FS_OPCODE_SQRT: 1778 case FS_OPCODE_EXP2: 1779 case FS_OPCODE_LOG2: 1780 case FS_OPCODE_POW: 1781 case FS_OPCODE_SIN: 1782 case FS_OPCODE_COS: 1783 generate_math(inst, dst, src); 1784 break; 1785 case FS_OPCODE_LINTERP: 1786 generate_linterp(inst, dst, src); 1787 break; 1788 case FS_OPCODE_TEX: 1789 case FS_OPCODE_TXB: 1790 case FS_OPCODE_TXL: 1791 generate_tex(inst, dst, src[0]); 1792 break; 1793 case FS_OPCODE_DISCARD: 1794 generate_discard(inst); 1795 break; 1796 case FS_OPCODE_FB_WRITE: 1797 generate_fb_write(inst); 1798 break; 1799 default: 1800 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { 1801 _mesa_problem(ctx, "Unsupported opcode `%s' in FS", 1802 brw_opcodes[inst->opcode].name); 1803 } else { 1804 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode); 1805 } 1806 this->fail = true; 1807 } 1808 1809 if (annotation_len < p->nr_insn) { 1810 annotation_len *= 2; 1811 if (annotation_len < 16) 1812 annotation_len = 16; 1813 1814 this->annotation_string = talloc_realloc(this->mem_ctx, 1815 annotation_string, 1816 const char *, 1817 annotation_len); 1818 this->annotation_ir = talloc_realloc(this->mem_ctx, 1819 annotation_ir, 1820 ir_instruction *, 1821 annotation_len); 1822 } 1823 1824 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { 1825 this->annotation_string[i] = inst->annotation; 1826 this->annotation_ir[i] = inst->ir; 1827 } 1828 last_native_inst = p->nr_insn; 1829 } 1830} 1831 1832GLboolean 1833brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c) 1834{ 1835 struct brw_compile *p = &c->func; 1836 struct intel_context *intel = &brw->intel; 1837 GLcontext *ctx = &intel->ctx; 1838 struct brw_shader *shader = NULL; 1839 struct gl_shader_program *prog = ctx->Shader.CurrentProgram; 1840 1841 if (!prog) 1842 return GL_FALSE; 1843 1844 if (!using_new_fs) 1845 return GL_FALSE; 1846 1847 for (unsigned int i = 0; i < prog->_NumLinkedShaders; i++) { 1848 if (prog->_LinkedShaders[i]->Type == GL_FRAGMENT_SHADER) { 1849 shader = (struct brw_shader *)prog->_LinkedShaders[i]; 1850 break; 1851 } 1852 } 1853 if (!shader) 1854 return GL_FALSE; 1855 1856 /* We always use 8-wide mode, at least for now. For one, flow 1857 * control only works in 8-wide. Also, when we're fragment shader 1858 * bound, we're almost always under register pressure as well, so 1859 * 8-wide would save us from the performance cliff of spilling 1860 * regs. 1861 */ 1862 c->dispatch_width = 8; 1863 1864 if (INTEL_DEBUG & DEBUG_WM) { 1865 printf("GLSL IR for native fragment shader %d:\n", prog->Name); 1866 _mesa_print_ir(shader->ir, NULL); 1867 printf("\n"); 1868 } 1869 1870 /* Now the main event: Visit the shader IR and generate our FS IR for it. 1871 */ 1872 fs_visitor v(c, shader); 1873 1874 if (0) { 1875 v.emit_dummy_fs(); 1876 } else { 1877 v.emit_interpolation(); 1878 1879 /* Generate FS IR for main(). (the visitor only descends into 1880 * functions called "main"). 1881 */ 1882 foreach_iter(exec_list_iterator, iter, *shader->ir) { 1883 ir_instruction *ir = (ir_instruction *)iter.get(); 1884 v.base_ir = ir; 1885 ir->accept(&v); 1886 } 1887 1888 v.emit_fb_writes(); 1889 v.assign_curb_setup(); 1890 v.assign_urb_setup(); 1891 v.assign_regs(); 1892 } 1893 1894 v.generate_code(); 1895 1896 assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */ 1897 1898 if (v.fail) 1899 return GL_FALSE; 1900 1901 if (INTEL_DEBUG & DEBUG_WM) { 1902 const char *last_annotation_string = NULL; 1903 ir_instruction *last_annotation_ir = NULL; 1904 1905 printf("Native code for fragment shader %d:\n", prog->Name); 1906 for (unsigned int i = 0; i < p->nr_insn; i++) { 1907 if (last_annotation_ir != v.annotation_ir[i]) { 1908 last_annotation_ir = v.annotation_ir[i]; 1909 if (last_annotation_ir) { 1910 printf(" "); 1911 last_annotation_ir->print(); 1912 printf("\n"); 1913 } 1914 } 1915 if (last_annotation_string != v.annotation_string[i]) { 1916 last_annotation_string = v.annotation_string[i]; 1917 if (last_annotation_string) 1918 printf(" %s\n", last_annotation_string); 1919 } 1920 brw_disasm(stdout, &p->store[i], intel->gen); 1921 } 1922 printf("\n"); 1923 } 1924 1925 c->prog_data.total_grf = v.grf_used; 1926 c->prog_data.total_scratch = 0; 1927 1928 return GL_TRUE; 1929} 1930