brw_fs.cpp revision cac04a93974e7ae773b84e000a2b26391ee2f4bb
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28extern "C" { 29 30#include <sys/types.h> 31 32#include "main/macros.h" 33#include "main/shaderobj.h" 34#include "main/uniforms.h" 35#include "program/prog_parameter.h" 36#include "program/prog_print.h" 37#include "program/prog_optimize.h" 38#include "program/register_allocate.h" 39#include "program/sampler.h" 40#include "program/hash_table.h" 41#include "brw_context.h" 42#include "brw_eu.h" 43#include "brw_wm.h" 44#include "talloc.h" 45} 46#include "../glsl/glsl_types.h" 47#include "../glsl/ir_optimization.h" 48#include "../glsl/ir_print_visitor.h" 49 50enum register_file { 51 ARF = BRW_ARCHITECTURE_REGISTER_FILE, 52 GRF = BRW_GENERAL_REGISTER_FILE, 53 MRF = BRW_MESSAGE_REGISTER_FILE, 54 IMM = BRW_IMMEDIATE_VALUE, 55 FIXED_HW_REG, /* a struct brw_reg */ 56 UNIFORM, /* prog_data->params[hw_reg] */ 57 BAD_FILE 58}; 59 60enum fs_opcodes { 61 FS_OPCODE_FB_WRITE = 256, 62 FS_OPCODE_RCP, 63 FS_OPCODE_RSQ, 64 FS_OPCODE_SQRT, 65 FS_OPCODE_EXP2, 66 FS_OPCODE_LOG2, 67 FS_OPCODE_POW, 68 FS_OPCODE_SIN, 69 FS_OPCODE_COS, 70 FS_OPCODE_DDX, 71 FS_OPCODE_DDY, 72 FS_OPCODE_LINTERP, 73 FS_OPCODE_TEX, 74 FS_OPCODE_TXB, 75 FS_OPCODE_TXL, 76 FS_OPCODE_DISCARD, 77}; 78 79static int using_new_fs = -1; 80static struct brw_reg brw_reg_from_fs_reg(class fs_reg *reg); 81 82struct gl_shader * 83brw_new_shader(GLcontext *ctx, GLuint name, GLuint type) 84{ 85 struct brw_shader *shader; 86 87 shader = talloc_zero(NULL, struct brw_shader); 88 if (shader) { 89 shader->base.Type = type; 90 shader->base.Name = name; 91 _mesa_init_shader(ctx, &shader->base); 92 } 93 94 return &shader->base; 95} 96 97struct gl_shader_program * 98brw_new_shader_program(GLcontext *ctx, GLuint name) 99{ 100 struct brw_shader_program *prog; 101 prog = talloc_zero(NULL, struct brw_shader_program); 102 if (prog) { 103 prog->base.Name = name; 104 _mesa_init_shader_program(ctx, &prog->base); 105 } 106 return &prog->base; 107} 108 109GLboolean 110brw_compile_shader(GLcontext *ctx, struct gl_shader *shader) 111{ 112 if (!_mesa_ir_compile_shader(ctx, shader)) 113 return GL_FALSE; 114 115 return GL_TRUE; 116} 117 118GLboolean 119brw_link_shader(GLcontext *ctx, struct gl_shader_program *prog) 120{ 121 struct intel_context *intel = intel_context(ctx); 122 if (using_new_fs == -1) 123 using_new_fs = getenv("INTEL_NEW_FS") != NULL; 124 125 for (unsigned i = 0; i < prog->_NumLinkedShaders; i++) { 126 struct brw_shader *shader = (struct brw_shader *)prog->_LinkedShaders[i]; 127 128 if (using_new_fs && shader->base.Type == GL_FRAGMENT_SHADER) { 129 void *mem_ctx = talloc_new(NULL); 130 bool progress; 131 132 if (shader->ir) 133 talloc_free(shader->ir); 134 shader->ir = new(shader) exec_list; 135 clone_ir_list(mem_ctx, shader->ir, shader->base.ir); 136 137 do_mat_op_to_vec(shader->ir); 138 do_mod_to_fract(shader->ir); 139 do_div_to_mul_rcp(shader->ir); 140 do_sub_to_add_neg(shader->ir); 141 do_explog_to_explog2(shader->ir); 142 do_lower_texture_projection(shader->ir); 143 brw_do_cubemap_normalize(shader->ir); 144 145 do { 146 progress = false; 147 148 brw_do_channel_expressions(shader->ir); 149 brw_do_vector_splitting(shader->ir); 150 151 progress = do_lower_jumps(shader->ir, true, true, 152 true, /* main return */ 153 false, /* continue */ 154 false /* loops */ 155 ) || progress; 156 157 progress = do_common_optimization(shader->ir, true, 32) || progress; 158 159 progress = lower_noise(shader->ir) || progress; 160 progress = 161 lower_variable_index_to_cond_assign(shader->ir, 162 GL_TRUE, /* input */ 163 GL_TRUE, /* output */ 164 GL_TRUE, /* temp */ 165 GL_TRUE /* uniform */ 166 ) || progress; 167 if (intel->gen == 6) { 168 progress = do_if_to_cond_assign(shader->ir) || progress; 169 } 170 } while (progress); 171 172 validate_ir_tree(shader->ir); 173 174 reparent_ir(shader->ir, shader->ir); 175 talloc_free(mem_ctx); 176 } 177 } 178 179 if (!_mesa_ir_link_shader(ctx, prog)) 180 return GL_FALSE; 181 182 return GL_TRUE; 183} 184 185static int 186type_size(const struct glsl_type *type) 187{ 188 unsigned int size, i; 189 190 switch (type->base_type) { 191 case GLSL_TYPE_UINT: 192 case GLSL_TYPE_INT: 193 case GLSL_TYPE_FLOAT: 194 case GLSL_TYPE_BOOL: 195 return type->components(); 196 case GLSL_TYPE_ARRAY: 197 return type_size(type->fields.array) * type->length; 198 case GLSL_TYPE_STRUCT: 199 size = 0; 200 for (i = 0; i < type->length; i++) { 201 size += type_size(type->fields.structure[i].type); 202 } 203 return size; 204 case GLSL_TYPE_SAMPLER: 205 /* Samplers take up no register space, since they're baked in at 206 * link time. 207 */ 208 return 0; 209 default: 210 assert(!"not reached"); 211 return 0; 212 } 213} 214 215class fs_reg { 216public: 217 /* Callers of this talloc-based new need not call delete. It's 218 * easier to just talloc_free 'ctx' (or any of its ancestors). */ 219 static void* operator new(size_t size, void *ctx) 220 { 221 void *node; 222 223 node = talloc_size(ctx, size); 224 assert(node != NULL); 225 226 return node; 227 } 228 229 void init() 230 { 231 this->reg = 0; 232 this->reg_offset = 0; 233 this->negate = 0; 234 this->abs = 0; 235 this->hw_reg = -1; 236 } 237 238 /** Generic unset register constructor. */ 239 fs_reg() 240 { 241 init(); 242 this->file = BAD_FILE; 243 } 244 245 /** Immediate value constructor. */ 246 fs_reg(float f) 247 { 248 init(); 249 this->file = IMM; 250 this->type = BRW_REGISTER_TYPE_F; 251 this->imm.f = f; 252 } 253 254 /** Immediate value constructor. */ 255 fs_reg(int32_t i) 256 { 257 init(); 258 this->file = IMM; 259 this->type = BRW_REGISTER_TYPE_D; 260 this->imm.i = i; 261 } 262 263 /** Immediate value constructor. */ 264 fs_reg(uint32_t u) 265 { 266 init(); 267 this->file = IMM; 268 this->type = BRW_REGISTER_TYPE_UD; 269 this->imm.u = u; 270 } 271 272 /** Fixed brw_reg Immediate value constructor. */ 273 fs_reg(struct brw_reg fixed_hw_reg) 274 { 275 init(); 276 this->file = FIXED_HW_REG; 277 this->fixed_hw_reg = fixed_hw_reg; 278 this->type = fixed_hw_reg.type; 279 } 280 281 fs_reg(enum register_file file, int hw_reg); 282 fs_reg(class fs_visitor *v, const struct glsl_type *type); 283 284 /** Register file: ARF, GRF, MRF, IMM. */ 285 enum register_file file; 286 /** virtual register number. 0 = fixed hw reg */ 287 int reg; 288 /** Offset within the virtual register. */ 289 int reg_offset; 290 /** HW register number. Generally unset until register allocation. */ 291 int hw_reg; 292 /** Register type. BRW_REGISTER_TYPE_* */ 293 int type; 294 bool negate; 295 bool abs; 296 struct brw_reg fixed_hw_reg; 297 298 /** Value for file == BRW_IMMMEDIATE_FILE */ 299 union { 300 int32_t i; 301 uint32_t u; 302 float f; 303 } imm; 304}; 305 306static const fs_reg reg_undef; 307static const fs_reg reg_null(ARF, BRW_ARF_NULL); 308 309class fs_inst : public exec_node { 310public: 311 /* Callers of this talloc-based new need not call delete. It's 312 * easier to just talloc_free 'ctx' (or any of its ancestors). */ 313 static void* operator new(size_t size, void *ctx) 314 { 315 void *node; 316 317 node = talloc_zero_size(ctx, size); 318 assert(node != NULL); 319 320 return node; 321 } 322 323 void init() 324 { 325 this->opcode = BRW_OPCODE_NOP; 326 this->saturate = false; 327 this->conditional_mod = BRW_CONDITIONAL_NONE; 328 this->predicated = false; 329 this->sampler = 0; 330 this->target = 0; 331 this->eot = false; 332 this->header_present = false; 333 this->shadow_compare = false; 334 } 335 336 fs_inst() 337 { 338 init(); 339 } 340 341 fs_inst(int opcode) 342 { 343 init(); 344 this->opcode = opcode; 345 } 346 347 fs_inst(int opcode, fs_reg dst, fs_reg src0) 348 { 349 init(); 350 this->opcode = opcode; 351 this->dst = dst; 352 this->src[0] = src0; 353 } 354 355 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1) 356 { 357 init(); 358 this->opcode = opcode; 359 this->dst = dst; 360 this->src[0] = src0; 361 this->src[1] = src1; 362 } 363 364 fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2) 365 { 366 init(); 367 this->opcode = opcode; 368 this->dst = dst; 369 this->src[0] = src0; 370 this->src[1] = src1; 371 this->src[2] = src2; 372 } 373 374 int opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ 375 fs_reg dst; 376 fs_reg src[3]; 377 bool saturate; 378 bool predicated; 379 int conditional_mod; /**< BRW_CONDITIONAL_* */ 380 381 int mlen; /**< SEND message length */ 382 int sampler; 383 int target; /**< MRT target. */ 384 bool eot; 385 bool header_present; 386 bool shadow_compare; 387 388 /** @{ 389 * Annotation for the generated IR. One of the two can be set. 390 */ 391 ir_instruction *ir; 392 const char *annotation; 393 /** @} */ 394}; 395 396class fs_visitor : public ir_visitor 397{ 398public: 399 400 fs_visitor(struct brw_wm_compile *c, struct brw_shader *shader) 401 { 402 this->c = c; 403 this->p = &c->func; 404 this->brw = p->brw; 405 this->fp = brw->fragment_program; 406 this->intel = &brw->intel; 407 this->ctx = &intel->ctx; 408 this->mem_ctx = talloc_new(NULL); 409 this->shader = shader; 410 this->fail = false; 411 this->variable_ht = hash_table_ctor(0, 412 hash_table_pointer_hash, 413 hash_table_pointer_compare); 414 415 this->frag_color = NULL; 416 this->frag_data = NULL; 417 this->frag_depth = NULL; 418 this->first_non_payload_grf = 0; 419 420 this->current_annotation = NULL; 421 this->annotation_string = NULL; 422 this->annotation_ir = NULL; 423 this->base_ir = NULL; 424 425 this->virtual_grf_sizes = NULL; 426 this->virtual_grf_next = 1; 427 this->virtual_grf_array_size = 0; 428 this->virtual_grf_def = NULL; 429 this->virtual_grf_use = NULL; 430 431 this->kill_emitted = false; 432 } 433 434 ~fs_visitor() 435 { 436 talloc_free(this->mem_ctx); 437 hash_table_dtor(this->variable_ht); 438 } 439 440 fs_reg *variable_storage(ir_variable *var); 441 int virtual_grf_alloc(int size); 442 443 void visit(ir_variable *ir); 444 void visit(ir_assignment *ir); 445 void visit(ir_dereference_variable *ir); 446 void visit(ir_dereference_record *ir); 447 void visit(ir_dereference_array *ir); 448 void visit(ir_expression *ir); 449 void visit(ir_texture *ir); 450 void visit(ir_if *ir); 451 void visit(ir_constant *ir); 452 void visit(ir_swizzle *ir); 453 void visit(ir_return *ir); 454 void visit(ir_loop *ir); 455 void visit(ir_loop_jump *ir); 456 void visit(ir_discard *ir); 457 void visit(ir_call *ir); 458 void visit(ir_function *ir); 459 void visit(ir_function_signature *ir); 460 461 fs_inst *emit(fs_inst inst); 462 void assign_curb_setup(); 463 void calculate_urb_setup(); 464 void assign_urb_setup(); 465 void assign_regs(); 466 void assign_regs_trivial(); 467 void calculate_live_intervals(); 468 bool propagate_constants(); 469 bool dead_code_eliminate(); 470 bool virtual_grf_interferes(int a, int b); 471 void generate_code(); 472 void generate_fb_write(fs_inst *inst); 473 void generate_linterp(fs_inst *inst, struct brw_reg dst, 474 struct brw_reg *src); 475 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src); 476 void generate_math(fs_inst *inst, struct brw_reg dst, struct brw_reg *src); 477 void generate_discard(fs_inst *inst, struct brw_reg temp); 478 void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src); 479 void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src); 480 481 void emit_dummy_fs(); 482 fs_reg *emit_fragcoord_interpolation(ir_variable *ir); 483 fs_reg *emit_frontfacing_interpolation(ir_variable *ir); 484 fs_reg *emit_general_interpolation(ir_variable *ir); 485 void emit_interpolation_setup_gen4(); 486 void emit_interpolation_setup_gen6(); 487 fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate); 488 fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate); 489 void emit_fb_writes(); 490 void emit_assignment_writes(fs_reg &l, fs_reg &r, 491 const glsl_type *type, bool predicated); 492 493 struct brw_reg interp_reg(int location, int channel); 494 int setup_uniform_values(int loc, const glsl_type *type); 495 void setup_builtin_uniform_values(ir_variable *ir); 496 497 struct brw_context *brw; 498 const struct gl_fragment_program *fp; 499 struct intel_context *intel; 500 GLcontext *ctx; 501 struct brw_wm_compile *c; 502 struct brw_compile *p; 503 struct brw_shader *shader; 504 void *mem_ctx; 505 exec_list instructions; 506 507 int *virtual_grf_sizes; 508 int virtual_grf_next; 509 int virtual_grf_array_size; 510 int *virtual_grf_def; 511 int *virtual_grf_use; 512 513 struct hash_table *variable_ht; 514 ir_variable *frag_color, *frag_data, *frag_depth; 515 int first_non_payload_grf; 516 int urb_setup[FRAG_ATTRIB_MAX]; 517 bool kill_emitted; 518 519 /** @{ debug annotation info */ 520 const char *current_annotation; 521 ir_instruction *base_ir; 522 const char **annotation_string; 523 ir_instruction **annotation_ir; 524 /** @} */ 525 526 bool fail; 527 528 /* Result of last visit() method. */ 529 fs_reg result; 530 531 fs_reg pixel_x; 532 fs_reg pixel_y; 533 fs_reg wpos_w; 534 fs_reg pixel_w; 535 fs_reg delta_x; 536 fs_reg delta_y; 537 538 int grf_used; 539 540}; 541 542int 543fs_visitor::virtual_grf_alloc(int size) 544{ 545 if (virtual_grf_array_size <= virtual_grf_next) { 546 if (virtual_grf_array_size == 0) 547 virtual_grf_array_size = 16; 548 else 549 virtual_grf_array_size *= 2; 550 virtual_grf_sizes = talloc_realloc(mem_ctx, virtual_grf_sizes, 551 int, virtual_grf_array_size); 552 553 /* This slot is always unused. */ 554 virtual_grf_sizes[0] = 0; 555 } 556 virtual_grf_sizes[virtual_grf_next] = size; 557 return virtual_grf_next++; 558} 559 560/** Fixed HW reg constructor. */ 561fs_reg::fs_reg(enum register_file file, int hw_reg) 562{ 563 init(); 564 this->file = file; 565 this->hw_reg = hw_reg; 566 this->type = BRW_REGISTER_TYPE_F; 567} 568 569int 570brw_type_for_base_type(const struct glsl_type *type) 571{ 572 switch (type->base_type) { 573 case GLSL_TYPE_FLOAT: 574 return BRW_REGISTER_TYPE_F; 575 case GLSL_TYPE_INT: 576 case GLSL_TYPE_BOOL: 577 return BRW_REGISTER_TYPE_D; 578 case GLSL_TYPE_UINT: 579 return BRW_REGISTER_TYPE_UD; 580 case GLSL_TYPE_ARRAY: 581 case GLSL_TYPE_STRUCT: 582 /* These should be overridden with the type of the member when 583 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely 584 * way to trip up if we don't. 585 */ 586 return BRW_REGISTER_TYPE_UD; 587 default: 588 assert(!"not reached"); 589 return BRW_REGISTER_TYPE_F; 590 } 591} 592 593/** Automatic reg constructor. */ 594fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type) 595{ 596 init(); 597 598 this->file = GRF; 599 this->reg = v->virtual_grf_alloc(type_size(type)); 600 this->reg_offset = 0; 601 this->type = brw_type_for_base_type(type); 602} 603 604fs_reg * 605fs_visitor::variable_storage(ir_variable *var) 606{ 607 return (fs_reg *)hash_table_find(this->variable_ht, var); 608} 609 610/* Our support for uniforms is piggy-backed on the struct 611 * gl_fragment_program, because that's where the values actually 612 * get stored, rather than in some global gl_shader_program uniform 613 * store. 614 */ 615int 616fs_visitor::setup_uniform_values(int loc, const glsl_type *type) 617{ 618 unsigned int offset = 0; 619 float *vec_values; 620 621 if (type->is_matrix()) { 622 const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT, 623 type->vector_elements, 624 1); 625 626 for (unsigned int i = 0; i < type->matrix_columns; i++) { 627 offset += setup_uniform_values(loc + offset, column); 628 } 629 630 return offset; 631 } 632 633 switch (type->base_type) { 634 case GLSL_TYPE_FLOAT: 635 case GLSL_TYPE_UINT: 636 case GLSL_TYPE_INT: 637 case GLSL_TYPE_BOOL: 638 vec_values = fp->Base.Parameters->ParameterValues[loc]; 639 for (unsigned int i = 0; i < type->vector_elements; i++) { 640 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[i]; 641 } 642 return 1; 643 644 case GLSL_TYPE_STRUCT: 645 for (unsigned int i = 0; i < type->length; i++) { 646 offset += setup_uniform_values(loc + offset, 647 type->fields.structure[i].type); 648 } 649 return offset; 650 651 case GLSL_TYPE_ARRAY: 652 for (unsigned int i = 0; i < type->length; i++) { 653 offset += setup_uniform_values(loc + offset, type->fields.array); 654 } 655 return offset; 656 657 case GLSL_TYPE_SAMPLER: 658 /* The sampler takes up a slot, but we don't use any values from it. */ 659 return 1; 660 661 default: 662 assert(!"not reached"); 663 return 0; 664 } 665} 666 667 668/* Our support for builtin uniforms is even scarier than non-builtin. 669 * It sits on top of the PROG_STATE_VAR parameters that are 670 * automatically updated from GL context state. 671 */ 672void 673fs_visitor::setup_builtin_uniform_values(ir_variable *ir) 674{ 675 const struct gl_builtin_uniform_desc *statevar = NULL; 676 677 for (unsigned int i = 0; _mesa_builtin_uniform_desc[i].name; i++) { 678 statevar = &_mesa_builtin_uniform_desc[i]; 679 if (strcmp(ir->name, _mesa_builtin_uniform_desc[i].name) == 0) 680 break; 681 } 682 683 if (!statevar->name) { 684 this->fail = true; 685 printf("Failed to find builtin uniform `%s'\n", ir->name); 686 return; 687 } 688 689 int array_count; 690 if (ir->type->is_array()) { 691 array_count = ir->type->length; 692 } else { 693 array_count = 1; 694 } 695 696 for (int a = 0; a < array_count; a++) { 697 for (unsigned int i = 0; i < statevar->num_elements; i++) { 698 struct gl_builtin_uniform_element *element = &statevar->elements[i]; 699 int tokens[STATE_LENGTH]; 700 701 memcpy(tokens, element->tokens, sizeof(element->tokens)); 702 if (ir->type->is_array()) { 703 tokens[1] = a; 704 } 705 706 /* This state reference has already been setup by ir_to_mesa, 707 * but we'll get the same index back here. 708 */ 709 int index = _mesa_add_state_reference(this->fp->Base.Parameters, 710 (gl_state_index *)tokens); 711 float *vec_values = this->fp->Base.Parameters->ParameterValues[index]; 712 713 /* Add each of the unique swizzles of the element as a 714 * parameter. This'll end up matching the expected layout of 715 * the array/matrix/structure we're trying to fill in. 716 */ 717 int last_swiz = -1; 718 for (unsigned int i = 0; i < 4; i++) { 719 int swiz = GET_SWZ(element->swizzle, i); 720 if (swiz == last_swiz) 721 break; 722 last_swiz = swiz; 723 724 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[swiz]; 725 } 726 } 727 } 728} 729 730fs_reg * 731fs_visitor::emit_fragcoord_interpolation(ir_variable *ir) 732{ 733 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); 734 fs_reg wpos = *reg; 735 fs_reg neg_y = this->pixel_y; 736 neg_y.negate = true; 737 738 /* gl_FragCoord.x */ 739 if (ir->pixel_center_integer) { 740 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_x)); 741 } else { 742 emit(fs_inst(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f))); 743 } 744 wpos.reg_offset++; 745 746 /* gl_FragCoord.y */ 747 if (ir->origin_upper_left && ir->pixel_center_integer) { 748 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y)); 749 } else { 750 fs_reg pixel_y = this->pixel_y; 751 float offset = (ir->pixel_center_integer ? 0.0 : 0.5); 752 753 if (!ir->origin_upper_left) { 754 pixel_y.negate = true; 755 offset += c->key.drawable_height - 1.0; 756 } 757 758 emit(fs_inst(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset))); 759 } 760 wpos.reg_offset++; 761 762 /* gl_FragCoord.z */ 763 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y, 764 interp_reg(FRAG_ATTRIB_WPOS, 2))); 765 wpos.reg_offset++; 766 767 /* gl_FragCoord.w: Already set up in emit_interpolation */ 768 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->wpos_w)); 769 770 return reg; 771} 772 773fs_reg * 774fs_visitor::emit_general_interpolation(ir_variable *ir) 775{ 776 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); 777 /* Interpolation is always in floating point regs. */ 778 reg->type = BRW_REGISTER_TYPE_F; 779 fs_reg attr = *reg; 780 781 unsigned int array_elements; 782 const glsl_type *type; 783 784 if (ir->type->is_array()) { 785 array_elements = ir->type->length; 786 if (array_elements == 0) { 787 this->fail = true; 788 } 789 type = ir->type->fields.array; 790 } else { 791 array_elements = 1; 792 type = ir->type; 793 } 794 795 int location = ir->location; 796 for (unsigned int i = 0; i < array_elements; i++) { 797 for (unsigned int j = 0; j < type->matrix_columns; j++) { 798 if (urb_setup[location] == -1) { 799 /* If there's no incoming setup data for this slot, don't 800 * emit interpolation for it. 801 */ 802 attr.reg_offset += type->vector_elements; 803 location++; 804 continue; 805 } 806 807 for (unsigned int c = 0; c < type->vector_elements; c++) { 808 struct brw_reg interp = interp_reg(location, c); 809 emit(fs_inst(FS_OPCODE_LINTERP, 810 attr, 811 this->delta_x, 812 this->delta_y, 813 fs_reg(interp))); 814 attr.reg_offset++; 815 } 816 817 if (intel->gen < 6) { 818 attr.reg_offset -= type->vector_elements; 819 for (unsigned int c = 0; c < type->vector_elements; c++) { 820 emit(fs_inst(BRW_OPCODE_MUL, 821 attr, 822 attr, 823 this->pixel_w)); 824 attr.reg_offset++; 825 } 826 } 827 location++; 828 } 829 } 830 831 return reg; 832} 833 834fs_reg * 835fs_visitor::emit_frontfacing_interpolation(ir_variable *ir) 836{ 837 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); 838 839 /* The frontfacing comes in as a bit in the thread payload. */ 840 if (intel->gen >= 6) { 841 emit(fs_inst(BRW_OPCODE_ASR, 842 *reg, 843 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)), 844 fs_reg(15))); 845 emit(fs_inst(BRW_OPCODE_NOT, 846 *reg, 847 *reg)); 848 emit(fs_inst(BRW_OPCODE_AND, 849 *reg, 850 *reg, 851 fs_reg(1))); 852 } else { 853 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); 854 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); 855 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives 856 * us front face 857 */ 858 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, 859 *reg, 860 fs_reg(r1_6ud), 861 fs_reg(1u << 31))); 862 inst->conditional_mod = BRW_CONDITIONAL_L; 863 emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u))); 864 } 865 866 return reg; 867} 868 869void 870fs_visitor::visit(ir_variable *ir) 871{ 872 fs_reg *reg = NULL; 873 874 if (variable_storage(ir)) 875 return; 876 877 if (strcmp(ir->name, "gl_FragColor") == 0) { 878 this->frag_color = ir; 879 } else if (strcmp(ir->name, "gl_FragData") == 0) { 880 this->frag_data = ir; 881 } else if (strcmp(ir->name, "gl_FragDepth") == 0) { 882 this->frag_depth = ir; 883 } 884 885 if (ir->mode == ir_var_in) { 886 if (!strcmp(ir->name, "gl_FragCoord")) { 887 reg = emit_fragcoord_interpolation(ir); 888 } else if (!strcmp(ir->name, "gl_FrontFacing")) { 889 reg = emit_frontfacing_interpolation(ir); 890 } else { 891 reg = emit_general_interpolation(ir); 892 } 893 assert(reg); 894 hash_table_insert(this->variable_ht, reg, ir); 895 return; 896 } 897 898 if (ir->mode == ir_var_uniform) { 899 int param_index = c->prog_data.nr_params; 900 901 if (!strncmp(ir->name, "gl_", 3)) { 902 setup_builtin_uniform_values(ir); 903 } else { 904 setup_uniform_values(ir->location, ir->type); 905 } 906 907 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); 908 } 909 910 if (!reg) 911 reg = new(this->mem_ctx) fs_reg(this, ir->type); 912 913 hash_table_insert(this->variable_ht, reg, ir); 914} 915 916void 917fs_visitor::visit(ir_dereference_variable *ir) 918{ 919 fs_reg *reg = variable_storage(ir->var); 920 this->result = *reg; 921} 922 923void 924fs_visitor::visit(ir_dereference_record *ir) 925{ 926 const glsl_type *struct_type = ir->record->type; 927 928 ir->record->accept(this); 929 930 unsigned int offset = 0; 931 for (unsigned int i = 0; i < struct_type->length; i++) { 932 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) 933 break; 934 offset += type_size(struct_type->fields.structure[i].type); 935 } 936 this->result.reg_offset += offset; 937 this->result.type = brw_type_for_base_type(ir->type); 938} 939 940void 941fs_visitor::visit(ir_dereference_array *ir) 942{ 943 ir_constant *index; 944 int element_size; 945 946 ir->array->accept(this); 947 index = ir->array_index->as_constant(); 948 949 element_size = type_size(ir->type); 950 this->result.type = brw_type_for_base_type(ir->type); 951 952 if (index) { 953 assert(this->result.file == UNIFORM || 954 (this->result.file == GRF && 955 this->result.reg != 0)); 956 this->result.reg_offset += index->value.i[0] * element_size; 957 } else { 958 assert(!"FINISHME: non-constant array element"); 959 } 960} 961 962void 963fs_visitor::visit(ir_expression *ir) 964{ 965 unsigned int operand; 966 fs_reg op[2], temp; 967 fs_reg result; 968 fs_inst *inst; 969 970 for (operand = 0; operand < ir->get_num_operands(); operand++) { 971 ir->operands[operand]->accept(this); 972 if (this->result.file == BAD_FILE) { 973 ir_print_visitor v; 974 printf("Failed to get tree for expression operand:\n"); 975 ir->operands[operand]->accept(&v); 976 this->fail = true; 977 } 978 op[operand] = this->result; 979 980 /* Matrix expression operands should have been broken down to vector 981 * operations already. 982 */ 983 assert(!ir->operands[operand]->type->is_matrix()); 984 /* And then those vector operands should have been broken down to scalar. 985 */ 986 assert(!ir->operands[operand]->type->is_vector()); 987 } 988 989 /* Storage for our result. If our result goes into an assignment, it will 990 * just get copy-propagated out, so no worries. 991 */ 992 this->result = fs_reg(this, ir->type); 993 994 switch (ir->operation) { 995 case ir_unop_logic_not: 996 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], fs_reg(-1))); 997 break; 998 case ir_unop_neg: 999 op[0].negate = !op[0].negate; 1000 this->result = op[0]; 1001 break; 1002 case ir_unop_abs: 1003 op[0].abs = true; 1004 this->result = op[0]; 1005 break; 1006 case ir_unop_sign: 1007 temp = fs_reg(this, ir->type); 1008 1009 emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(0.0f))); 1010 1011 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f))); 1012 inst->conditional_mod = BRW_CONDITIONAL_G; 1013 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(1.0f))); 1014 inst->predicated = true; 1015 1016 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f))); 1017 inst->conditional_mod = BRW_CONDITIONAL_L; 1018 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f))); 1019 inst->predicated = true; 1020 1021 break; 1022 case ir_unop_rcp: 1023 emit(fs_inst(FS_OPCODE_RCP, this->result, op[0])); 1024 break; 1025 1026 case ir_unop_exp2: 1027 emit(fs_inst(FS_OPCODE_EXP2, this->result, op[0])); 1028 break; 1029 case ir_unop_log2: 1030 emit(fs_inst(FS_OPCODE_LOG2, this->result, op[0])); 1031 break; 1032 case ir_unop_exp: 1033 case ir_unop_log: 1034 assert(!"not reached: should be handled by ir_explog_to_explog2"); 1035 break; 1036 case ir_unop_sin: 1037 emit(fs_inst(FS_OPCODE_SIN, this->result, op[0])); 1038 break; 1039 case ir_unop_cos: 1040 emit(fs_inst(FS_OPCODE_COS, this->result, op[0])); 1041 break; 1042 1043 case ir_unop_dFdx: 1044 emit(fs_inst(FS_OPCODE_DDX, this->result, op[0])); 1045 break; 1046 case ir_unop_dFdy: 1047 emit(fs_inst(FS_OPCODE_DDY, this->result, op[0])); 1048 break; 1049 1050 case ir_binop_add: 1051 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], op[1])); 1052 break; 1053 case ir_binop_sub: 1054 assert(!"not reached: should be handled by ir_sub_to_add_neg"); 1055 break; 1056 1057 case ir_binop_mul: 1058 emit(fs_inst(BRW_OPCODE_MUL, this->result, op[0], op[1])); 1059 break; 1060 case ir_binop_div: 1061 assert(!"not reached: should be handled by ir_div_to_mul_rcp"); 1062 break; 1063 case ir_binop_mod: 1064 assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); 1065 break; 1066 1067 case ir_binop_less: 1068 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 1069 inst->conditional_mod = BRW_CONDITIONAL_L; 1070 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 1071 break; 1072 case ir_binop_greater: 1073 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 1074 inst->conditional_mod = BRW_CONDITIONAL_G; 1075 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 1076 break; 1077 case ir_binop_lequal: 1078 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 1079 inst->conditional_mod = BRW_CONDITIONAL_LE; 1080 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 1081 break; 1082 case ir_binop_gequal: 1083 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 1084 inst->conditional_mod = BRW_CONDITIONAL_GE; 1085 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 1086 break; 1087 case ir_binop_equal: 1088 case ir_binop_all_equal: /* same as nequal for scalars */ 1089 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 1090 inst->conditional_mod = BRW_CONDITIONAL_Z; 1091 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 1092 break; 1093 case ir_binop_nequal: 1094 case ir_binop_any_nequal: /* same as nequal for scalars */ 1095 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 1096 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1097 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1))); 1098 break; 1099 1100 case ir_binop_logic_xor: 1101 emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1])); 1102 break; 1103 1104 case ir_binop_logic_or: 1105 emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1])); 1106 break; 1107 1108 case ir_binop_logic_and: 1109 emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1])); 1110 break; 1111 1112 case ir_binop_dot: 1113 case ir_binop_cross: 1114 case ir_unop_any: 1115 assert(!"not reached: should be handled by brw_fs_channel_expressions"); 1116 break; 1117 1118 case ir_unop_noise: 1119 assert(!"not reached: should be handled by lower_noise"); 1120 break; 1121 1122 case ir_unop_sqrt: 1123 emit(fs_inst(FS_OPCODE_SQRT, this->result, op[0])); 1124 break; 1125 1126 case ir_unop_rsq: 1127 emit(fs_inst(FS_OPCODE_RSQ, this->result, op[0])); 1128 break; 1129 1130 case ir_unop_i2f: 1131 case ir_unop_b2f: 1132 case ir_unop_b2i: 1133 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0])); 1134 break; 1135 case ir_unop_f2i: 1136 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0])); 1137 break; 1138 case ir_unop_f2b: 1139 case ir_unop_i2b: 1140 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f))); 1141 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1142 1143 case ir_unop_trunc: 1144 emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0])); 1145 break; 1146 case ir_unop_ceil: 1147 op[0].negate = ~op[0].negate; 1148 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0])); 1149 this->result.negate = true; 1150 break; 1151 case ir_unop_floor: 1152 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0])); 1153 break; 1154 case ir_unop_fract: 1155 inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0])); 1156 break; 1157 1158 case ir_binop_min: 1159 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 1160 inst->conditional_mod = BRW_CONDITIONAL_L; 1161 1162 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1])); 1163 inst->predicated = true; 1164 break; 1165 case ir_binop_max: 1166 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1])); 1167 inst->conditional_mod = BRW_CONDITIONAL_G; 1168 1169 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1])); 1170 inst->predicated = true; 1171 break; 1172 1173 case ir_binop_pow: 1174 inst = emit(fs_inst(FS_OPCODE_POW, this->result, op[0], op[1])); 1175 break; 1176 1177 case ir_unop_bit_not: 1178 case ir_unop_u2f: 1179 case ir_binop_lshift: 1180 case ir_binop_rshift: 1181 case ir_binop_bit_and: 1182 case ir_binop_bit_xor: 1183 case ir_binop_bit_or: 1184 assert(!"GLSL 1.30 features unsupported"); 1185 break; 1186 } 1187} 1188 1189void 1190fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, 1191 const glsl_type *type, bool predicated) 1192{ 1193 switch (type->base_type) { 1194 case GLSL_TYPE_FLOAT: 1195 case GLSL_TYPE_UINT: 1196 case GLSL_TYPE_INT: 1197 case GLSL_TYPE_BOOL: 1198 for (unsigned int i = 0; i < type->components(); i++) { 1199 l.type = brw_type_for_base_type(type); 1200 r.type = brw_type_for_base_type(type); 1201 1202 fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, l, r)); 1203 inst->predicated = predicated; 1204 1205 l.reg_offset++; 1206 r.reg_offset++; 1207 } 1208 break; 1209 case GLSL_TYPE_ARRAY: 1210 for (unsigned int i = 0; i < type->length; i++) { 1211 emit_assignment_writes(l, r, type->fields.array, predicated); 1212 } 1213 1214 case GLSL_TYPE_STRUCT: 1215 for (unsigned int i = 0; i < type->length; i++) { 1216 emit_assignment_writes(l, r, type->fields.structure[i].type, 1217 predicated); 1218 } 1219 break; 1220 1221 case GLSL_TYPE_SAMPLER: 1222 break; 1223 1224 default: 1225 assert(!"not reached"); 1226 break; 1227 } 1228} 1229 1230void 1231fs_visitor::visit(ir_assignment *ir) 1232{ 1233 struct fs_reg l, r; 1234 fs_inst *inst; 1235 1236 /* FINISHME: arrays on the lhs */ 1237 ir->lhs->accept(this); 1238 l = this->result; 1239 1240 ir->rhs->accept(this); 1241 r = this->result; 1242 1243 assert(l.file != BAD_FILE); 1244 assert(r.file != BAD_FILE); 1245 1246 if (ir->condition) { 1247 /* Get the condition bool into the predicate. */ 1248 ir->condition->accept(this); 1249 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, this->result, fs_reg(0))); 1250 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1251 } 1252 1253 if (ir->lhs->type->is_scalar() || 1254 ir->lhs->type->is_vector()) { 1255 for (int i = 0; i < ir->lhs->type->vector_elements; i++) { 1256 if (ir->write_mask & (1 << i)) { 1257 inst = emit(fs_inst(BRW_OPCODE_MOV, l, r)); 1258 if (ir->condition) 1259 inst->predicated = true; 1260 r.reg_offset++; 1261 } 1262 l.reg_offset++; 1263 } 1264 } else { 1265 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); 1266 } 1267} 1268 1269fs_inst * 1270fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate) 1271{ 1272 int mlen; 1273 int base_mrf = 2; 1274 bool simd16 = false; 1275 fs_reg orig_dst; 1276 1277 if (ir->shadow_comparitor) { 1278 for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) { 1279 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 1280 coordinate)); 1281 coordinate.reg_offset++; 1282 } 1283 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 1284 mlen = 3; 1285 1286 if (ir->op == ir_tex) { 1287 /* There's no plain shadow compare message, so we use shadow 1288 * compare with a bias of 0.0. 1289 */ 1290 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 1291 fs_reg(0.0f))); 1292 mlen++; 1293 } else if (ir->op == ir_txb) { 1294 ir->lod_info.bias->accept(this); 1295 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 1296 this->result)); 1297 mlen++; 1298 } else { 1299 assert(ir->op == ir_txl); 1300 ir->lod_info.lod->accept(this); 1301 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 1302 this->result)); 1303 mlen++; 1304 } 1305 1306 ir->shadow_comparitor->accept(this); 1307 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result)); 1308 mlen++; 1309 } else if (ir->op == ir_tex) { 1310 for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) { 1311 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 1312 coordinate)); 1313 coordinate.reg_offset++; 1314 } 1315 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ 1316 mlen = 3; 1317 } else { 1318 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod 1319 * instructions. We'll need to do SIMD16 here. 1320 */ 1321 assert(ir->op == ir_txb || ir->op == ir_txl); 1322 1323 for (mlen = 0; mlen < ir->coordinate->type->vector_elements * 2;) { 1324 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 1325 coordinate)); 1326 coordinate.reg_offset++; 1327 mlen++; 1328 1329 /* The unused upper half. */ 1330 mlen++; 1331 } 1332 1333 /* lod/bias appears after u/v/r. */ 1334 mlen = 6; 1335 1336 if (ir->op == ir_txb) { 1337 ir->lod_info.bias->accept(this); 1338 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 1339 this->result)); 1340 mlen++; 1341 } else { 1342 ir->lod_info.lod->accept(this); 1343 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), 1344 this->result)); 1345 mlen++; 1346 } 1347 1348 /* The unused upper half. */ 1349 mlen++; 1350 1351 /* Now, since we're doing simd16, the return is 2 interleaved 1352 * vec4s where the odd-indexed ones are junk. We'll need to move 1353 * this weirdness around to the expected layout. 1354 */ 1355 simd16 = true; 1356 orig_dst = dst; 1357 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type, 1358 2)); 1359 dst.type = BRW_REGISTER_TYPE_F; 1360 } 1361 1362 fs_inst *inst = NULL; 1363 switch (ir->op) { 1364 case ir_tex: 1365 inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf))); 1366 break; 1367 case ir_txb: 1368 inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf))); 1369 break; 1370 case ir_txl: 1371 inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf))); 1372 break; 1373 case ir_txd: 1374 case ir_txf: 1375 assert(!"GLSL 1.30 features unsupported"); 1376 break; 1377 } 1378 inst->mlen = mlen; 1379 1380 if (simd16) { 1381 for (int i = 0; i < 4; i++) { 1382 emit(fs_inst(BRW_OPCODE_MOV, orig_dst, dst)); 1383 orig_dst.reg_offset++; 1384 dst.reg_offset += 2; 1385 } 1386 } 1387 1388 return inst; 1389} 1390 1391fs_inst * 1392fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate) 1393{ 1394 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then 1395 * optional parameters like shadow comparitor or LOD bias. If 1396 * optional parameters aren't present, those base slots are 1397 * optional and don't need to be included in the message. 1398 * 1399 * We don't fill in the unnecessary slots regardless, which may 1400 * look surprising in the disassembly. 1401 */ 1402 int mlen; 1403 int base_mrf = 2; 1404 1405 for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) { 1406 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate)); 1407 coordinate.reg_offset++; 1408 } 1409 1410 if (ir->shadow_comparitor) { 1411 mlen = MAX2(mlen, 4); 1412 1413 ir->shadow_comparitor->accept(this); 1414 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result)); 1415 mlen++; 1416 } 1417 1418 fs_inst *inst = NULL; 1419 switch (ir->op) { 1420 case ir_tex: 1421 inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf))); 1422 break; 1423 case ir_txb: 1424 ir->lod_info.bias->accept(this); 1425 mlen = MAX2(mlen, 4); 1426 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result)); 1427 mlen++; 1428 1429 inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf))); 1430 break; 1431 case ir_txl: 1432 ir->lod_info.lod->accept(this); 1433 mlen = MAX2(mlen, 4); 1434 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result)); 1435 mlen++; 1436 1437 inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf))); 1438 break; 1439 case ir_txd: 1440 case ir_txf: 1441 assert(!"GLSL 1.30 features unsupported"); 1442 break; 1443 } 1444 inst->mlen = mlen; 1445 1446 return inst; 1447} 1448 1449void 1450fs_visitor::visit(ir_texture *ir) 1451{ 1452 fs_inst *inst = NULL; 1453 1454 ir->coordinate->accept(this); 1455 fs_reg coordinate = this->result; 1456 1457 /* Should be lowered by do_lower_texture_projection */ 1458 assert(!ir->projector); 1459 1460 /* Writemasking doesn't eliminate channels on SIMD8 texture 1461 * samples, so don't worry about them. 1462 */ 1463 fs_reg dst = fs_reg(this, glsl_type::vec4_type); 1464 1465 if (intel->gen < 5) { 1466 inst = emit_texture_gen4(ir, dst, coordinate); 1467 } else { 1468 inst = emit_texture_gen5(ir, dst, coordinate); 1469 } 1470 1471 inst->sampler = 1472 _mesa_get_sampler_uniform_value(ir->sampler, 1473 ctx->Shader.CurrentProgram, 1474 &brw->fragment_program->Base); 1475 inst->sampler = c->fp->program.Base.SamplerUnits[inst->sampler]; 1476 1477 this->result = dst; 1478 1479 if (ir->shadow_comparitor) 1480 inst->shadow_compare = true; 1481 1482 if (c->key.tex_swizzles[inst->sampler] != SWIZZLE_NOOP) { 1483 fs_reg swizzle_dst = fs_reg(this, glsl_type::vec4_type); 1484 1485 for (int i = 0; i < 4; i++) { 1486 int swiz = GET_SWZ(c->key.tex_swizzles[inst->sampler], i); 1487 fs_reg l = swizzle_dst; 1488 l.reg_offset += i; 1489 1490 if (swiz == SWIZZLE_ZERO) { 1491 emit(fs_inst(BRW_OPCODE_MOV, l, fs_reg(0.0f))); 1492 } else if (swiz == SWIZZLE_ONE) { 1493 emit(fs_inst(BRW_OPCODE_MOV, l, fs_reg(1.0f))); 1494 } else { 1495 fs_reg r = dst; 1496 r.reg_offset += GET_SWZ(c->key.tex_swizzles[inst->sampler], i); 1497 emit(fs_inst(BRW_OPCODE_MOV, l, r)); 1498 } 1499 } 1500 this->result = swizzle_dst; 1501 } 1502} 1503 1504void 1505fs_visitor::visit(ir_swizzle *ir) 1506{ 1507 ir->val->accept(this); 1508 fs_reg val = this->result; 1509 1510 if (ir->type->vector_elements == 1) { 1511 this->result.reg_offset += ir->mask.x; 1512 return; 1513 } 1514 1515 fs_reg result = fs_reg(this, ir->type); 1516 this->result = result; 1517 1518 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1519 fs_reg channel = val; 1520 int swiz = 0; 1521 1522 switch (i) { 1523 case 0: 1524 swiz = ir->mask.x; 1525 break; 1526 case 1: 1527 swiz = ir->mask.y; 1528 break; 1529 case 2: 1530 swiz = ir->mask.z; 1531 break; 1532 case 3: 1533 swiz = ir->mask.w; 1534 break; 1535 } 1536 1537 channel.reg_offset += swiz; 1538 emit(fs_inst(BRW_OPCODE_MOV, result, channel)); 1539 result.reg_offset++; 1540 } 1541} 1542 1543void 1544fs_visitor::visit(ir_discard *ir) 1545{ 1546 fs_reg temp = fs_reg(this, glsl_type::uint_type); 1547 1548 assert(ir->condition == NULL); /* FINISHME */ 1549 1550 emit(fs_inst(FS_OPCODE_DISCARD, temp, temp)); 1551 kill_emitted = true; 1552} 1553 1554void 1555fs_visitor::visit(ir_constant *ir) 1556{ 1557 fs_reg reg(this, ir->type); 1558 this->result = reg; 1559 1560 for (unsigned int i = 0; i < ir->type->vector_elements; i++) { 1561 switch (ir->type->base_type) { 1562 case GLSL_TYPE_FLOAT: 1563 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.f[i]))); 1564 break; 1565 case GLSL_TYPE_UINT: 1566 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.u[i]))); 1567 break; 1568 case GLSL_TYPE_INT: 1569 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.i[i]))); 1570 break; 1571 case GLSL_TYPE_BOOL: 1572 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg((int)ir->value.b[i]))); 1573 break; 1574 default: 1575 assert(!"Non-float/uint/int/bool constant"); 1576 } 1577 reg.reg_offset++; 1578 } 1579} 1580 1581void 1582fs_visitor::visit(ir_if *ir) 1583{ 1584 fs_inst *inst; 1585 1586 /* Don't point the annotation at the if statement, because then it plus 1587 * the then and else blocks get printed. 1588 */ 1589 this->base_ir = ir->condition; 1590 1591 /* Generate the condition into the condition code. */ 1592 ir->condition->accept(this); 1593 inst = emit(fs_inst(BRW_OPCODE_MOV, fs_reg(brw_null_reg()), this->result)); 1594 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1595 1596 inst = emit(fs_inst(BRW_OPCODE_IF)); 1597 inst->predicated = true; 1598 1599 foreach_iter(exec_list_iterator, iter, ir->then_instructions) { 1600 ir_instruction *ir = (ir_instruction *)iter.get(); 1601 this->base_ir = ir; 1602 1603 ir->accept(this); 1604 } 1605 1606 if (!ir->else_instructions.is_empty()) { 1607 emit(fs_inst(BRW_OPCODE_ELSE)); 1608 1609 foreach_iter(exec_list_iterator, iter, ir->else_instructions) { 1610 ir_instruction *ir = (ir_instruction *)iter.get(); 1611 this->base_ir = ir; 1612 1613 ir->accept(this); 1614 } 1615 } 1616 1617 emit(fs_inst(BRW_OPCODE_ENDIF)); 1618} 1619 1620void 1621fs_visitor::visit(ir_loop *ir) 1622{ 1623 fs_reg counter = reg_undef; 1624 1625 if (ir->counter) { 1626 this->base_ir = ir->counter; 1627 ir->counter->accept(this); 1628 counter = *(variable_storage(ir->counter)); 1629 1630 if (ir->from) { 1631 this->base_ir = ir->from; 1632 ir->from->accept(this); 1633 1634 emit(fs_inst(BRW_OPCODE_MOV, counter, this->result)); 1635 } 1636 } 1637 1638 emit(fs_inst(BRW_OPCODE_DO)); 1639 1640 if (ir->to) { 1641 this->base_ir = ir->to; 1642 ir->to->accept(this); 1643 1644 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, 1645 counter, this->result)); 1646 switch (ir->cmp) { 1647 case ir_binop_equal: 1648 inst->conditional_mod = BRW_CONDITIONAL_Z; 1649 break; 1650 case ir_binop_nequal: 1651 inst->conditional_mod = BRW_CONDITIONAL_NZ; 1652 break; 1653 case ir_binop_gequal: 1654 inst->conditional_mod = BRW_CONDITIONAL_GE; 1655 break; 1656 case ir_binop_lequal: 1657 inst->conditional_mod = BRW_CONDITIONAL_LE; 1658 break; 1659 case ir_binop_greater: 1660 inst->conditional_mod = BRW_CONDITIONAL_G; 1661 break; 1662 case ir_binop_less: 1663 inst->conditional_mod = BRW_CONDITIONAL_L; 1664 break; 1665 default: 1666 assert(!"not reached: unknown loop condition"); 1667 this->fail = true; 1668 break; 1669 } 1670 1671 inst = emit(fs_inst(BRW_OPCODE_BREAK)); 1672 inst->predicated = true; 1673 } 1674 1675 foreach_iter(exec_list_iterator, iter, ir->body_instructions) { 1676 ir_instruction *ir = (ir_instruction *)iter.get(); 1677 1678 this->base_ir = ir; 1679 ir->accept(this); 1680 } 1681 1682 if (ir->increment) { 1683 this->base_ir = ir->increment; 1684 ir->increment->accept(this); 1685 emit(fs_inst(BRW_OPCODE_ADD, counter, counter, this->result)); 1686 } 1687 1688 emit(fs_inst(BRW_OPCODE_WHILE)); 1689} 1690 1691void 1692fs_visitor::visit(ir_loop_jump *ir) 1693{ 1694 switch (ir->mode) { 1695 case ir_loop_jump::jump_break: 1696 emit(fs_inst(BRW_OPCODE_BREAK)); 1697 break; 1698 case ir_loop_jump::jump_continue: 1699 emit(fs_inst(BRW_OPCODE_CONTINUE)); 1700 break; 1701 } 1702} 1703 1704void 1705fs_visitor::visit(ir_call *ir) 1706{ 1707 assert(!"FINISHME"); 1708} 1709 1710void 1711fs_visitor::visit(ir_return *ir) 1712{ 1713 assert(!"FINISHME"); 1714} 1715 1716void 1717fs_visitor::visit(ir_function *ir) 1718{ 1719 /* Ignore function bodies other than main() -- we shouldn't see calls to 1720 * them since they should all be inlined before we get to ir_to_mesa. 1721 */ 1722 if (strcmp(ir->name, "main") == 0) { 1723 const ir_function_signature *sig; 1724 exec_list empty; 1725 1726 sig = ir->matching_signature(&empty); 1727 1728 assert(sig); 1729 1730 foreach_iter(exec_list_iterator, iter, sig->body) { 1731 ir_instruction *ir = (ir_instruction *)iter.get(); 1732 this->base_ir = ir; 1733 1734 ir->accept(this); 1735 } 1736 } 1737} 1738 1739void 1740fs_visitor::visit(ir_function_signature *ir) 1741{ 1742 assert(!"not reached"); 1743 (void)ir; 1744} 1745 1746fs_inst * 1747fs_visitor::emit(fs_inst inst) 1748{ 1749 fs_inst *list_inst = new(mem_ctx) fs_inst; 1750 *list_inst = inst; 1751 1752 list_inst->annotation = this->current_annotation; 1753 list_inst->ir = this->base_ir; 1754 1755 this->instructions.push_tail(list_inst); 1756 1757 return list_inst; 1758} 1759 1760/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ 1761void 1762fs_visitor::emit_dummy_fs() 1763{ 1764 /* Everyone's favorite color. */ 1765 emit(fs_inst(BRW_OPCODE_MOV, 1766 fs_reg(MRF, 2), 1767 fs_reg(1.0f))); 1768 emit(fs_inst(BRW_OPCODE_MOV, 1769 fs_reg(MRF, 3), 1770 fs_reg(0.0f))); 1771 emit(fs_inst(BRW_OPCODE_MOV, 1772 fs_reg(MRF, 4), 1773 fs_reg(1.0f))); 1774 emit(fs_inst(BRW_OPCODE_MOV, 1775 fs_reg(MRF, 5), 1776 fs_reg(0.0f))); 1777 1778 fs_inst *write; 1779 write = emit(fs_inst(FS_OPCODE_FB_WRITE, 1780 fs_reg(0), 1781 fs_reg(0))); 1782} 1783 1784/* The register location here is relative to the start of the URB 1785 * data. It will get adjusted to be a real location before 1786 * generate_code() time. 1787 */ 1788struct brw_reg 1789fs_visitor::interp_reg(int location, int channel) 1790{ 1791 int regnr = urb_setup[location] * 2 + channel / 2; 1792 int stride = (channel & 1) * 4; 1793 1794 assert(urb_setup[location] != -1); 1795 1796 return brw_vec1_grf(regnr, stride); 1797} 1798 1799/** Emits the interpolation for the varying inputs. */ 1800void 1801fs_visitor::emit_interpolation_setup_gen4() 1802{ 1803 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1804 1805 this->current_annotation = "compute pixel centers"; 1806 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1807 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1808 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1809 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1810 emit(fs_inst(BRW_OPCODE_ADD, 1811 this->pixel_x, 1812 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1813 fs_reg(brw_imm_v(0x10101010)))); 1814 emit(fs_inst(BRW_OPCODE_ADD, 1815 this->pixel_y, 1816 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1817 fs_reg(brw_imm_v(0x11001100)))); 1818 1819 this->current_annotation = "compute pixel deltas from v0"; 1820 if (brw->has_pln) { 1821 this->delta_x = fs_reg(this, glsl_type::vec2_type); 1822 this->delta_y = this->delta_x; 1823 this->delta_y.reg_offset++; 1824 } else { 1825 this->delta_x = fs_reg(this, glsl_type::float_type); 1826 this->delta_y = fs_reg(this, glsl_type::float_type); 1827 } 1828 emit(fs_inst(BRW_OPCODE_ADD, 1829 this->delta_x, 1830 this->pixel_x, 1831 fs_reg(negate(brw_vec1_grf(1, 0))))); 1832 emit(fs_inst(BRW_OPCODE_ADD, 1833 this->delta_y, 1834 this->pixel_y, 1835 fs_reg(negate(brw_vec1_grf(1, 1))))); 1836 1837 this->current_annotation = "compute pos.w and 1/pos.w"; 1838 /* Compute wpos.w. It's always in our setup, since it's needed to 1839 * interpolate the other attributes. 1840 */ 1841 this->wpos_w = fs_reg(this, glsl_type::float_type); 1842 emit(fs_inst(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, 1843 interp_reg(FRAG_ATTRIB_WPOS, 3))); 1844 /* Compute the pixel 1/W value from wpos.w. */ 1845 this->pixel_w = fs_reg(this, glsl_type::float_type); 1846 emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos_w)); 1847 this->current_annotation = NULL; 1848} 1849 1850/** Emits the interpolation for the varying inputs. */ 1851void 1852fs_visitor::emit_interpolation_setup_gen6() 1853{ 1854 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); 1855 1856 /* If the pixel centers end up used, the setup is the same as for gen4. */ 1857 this->current_annotation = "compute pixel centers"; 1858 this->pixel_x = fs_reg(this, glsl_type::uint_type); 1859 this->pixel_y = fs_reg(this, glsl_type::uint_type); 1860 this->pixel_x.type = BRW_REGISTER_TYPE_UW; 1861 this->pixel_y.type = BRW_REGISTER_TYPE_UW; 1862 emit(fs_inst(BRW_OPCODE_ADD, 1863 this->pixel_x, 1864 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), 1865 fs_reg(brw_imm_v(0x10101010)))); 1866 emit(fs_inst(BRW_OPCODE_ADD, 1867 this->pixel_y, 1868 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), 1869 fs_reg(brw_imm_v(0x11001100)))); 1870 1871 this->current_annotation = "compute 1/pos.w"; 1872 this->wpos_w = fs_reg(brw_vec8_grf(c->key.source_w_reg, 0)); 1873 this->pixel_w = fs_reg(this, glsl_type::float_type); 1874 emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos_w)); 1875 1876 this->delta_x = fs_reg(brw_vec8_grf(2, 0)); 1877 this->delta_y = fs_reg(brw_vec8_grf(3, 0)); 1878 1879 this->current_annotation = NULL; 1880} 1881 1882void 1883fs_visitor::emit_fb_writes() 1884{ 1885 this->current_annotation = "FB write header"; 1886 GLboolean header_present = GL_TRUE; 1887 int nr = 0; 1888 1889 if (intel->gen >= 6 && 1890 !this->kill_emitted && 1891 c->key.nr_color_regions == 1) { 1892 header_present = false; 1893 } 1894 1895 if (header_present) { 1896 /* m0, m1 header */ 1897 nr += 2; 1898 } 1899 1900 if (c->key.aa_dest_stencil_reg) { 1901 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1902 fs_reg(brw_vec8_grf(c->key.aa_dest_stencil_reg, 0)))); 1903 } 1904 1905 /* Reserve space for color. It'll be filled in per MRT below. */ 1906 int color_mrf = nr; 1907 nr += 4; 1908 1909 if (c->key.source_depth_to_render_target) { 1910 if (c->key.computes_depth) { 1911 /* Hand over gl_FragDepth. */ 1912 assert(this->frag_depth); 1913 fs_reg depth = *(variable_storage(this->frag_depth)); 1914 1915 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++), depth)); 1916 } else { 1917 /* Pass through the payload depth. */ 1918 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1919 fs_reg(brw_vec8_grf(c->key.source_depth_reg, 0)))); 1920 } 1921 } 1922 1923 if (c->key.dest_depth_reg) { 1924 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++), 1925 fs_reg(brw_vec8_grf(c->key.dest_depth_reg, 0)))); 1926 } 1927 1928 fs_reg color = reg_undef; 1929 if (this->frag_color) 1930 color = *(variable_storage(this->frag_color)); 1931 else if (this->frag_data) 1932 color = *(variable_storage(this->frag_data)); 1933 1934 for (int target = 0; target < c->key.nr_color_regions; target++) { 1935 this->current_annotation = talloc_asprintf(this->mem_ctx, 1936 "FB write target %d", 1937 target); 1938 if (this->frag_color || this->frag_data) { 1939 for (int i = 0; i < 4; i++) { 1940 emit(fs_inst(BRW_OPCODE_MOV, 1941 fs_reg(MRF, color_mrf + i), 1942 color)); 1943 color.reg_offset++; 1944 } 1945 } 1946 1947 if (this->frag_color) 1948 color.reg_offset -= 4; 1949 1950 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE, 1951 reg_undef, reg_undef)); 1952 inst->target = target; 1953 inst->mlen = nr; 1954 if (target == c->key.nr_color_regions - 1) 1955 inst->eot = true; 1956 inst->header_present = header_present; 1957 } 1958 1959 if (c->key.nr_color_regions == 0) { 1960 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE, 1961 reg_undef, reg_undef)); 1962 inst->mlen = nr; 1963 inst->eot = true; 1964 inst->header_present = header_present; 1965 } 1966 1967 this->current_annotation = NULL; 1968} 1969 1970void 1971fs_visitor::generate_fb_write(fs_inst *inst) 1972{ 1973 GLboolean eot = inst->eot; 1974 struct brw_reg implied_header; 1975 1976 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied 1977 * move, here's g1. 1978 */ 1979 brw_push_insn_state(p); 1980 brw_set_mask_control(p, BRW_MASK_DISABLE); 1981 brw_set_compression_control(p, BRW_COMPRESSION_NONE); 1982 1983 if (inst->header_present) { 1984 if (intel->gen >= 6) { 1985 brw_MOV(p, 1986 brw_message_reg(0), 1987 brw_vec8_grf(0, 0)); 1988 implied_header = brw_null_reg(); 1989 } else { 1990 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW); 1991 } 1992 1993 brw_MOV(p, 1994 brw_message_reg(1), 1995 brw_vec8_grf(1, 0)); 1996 } else { 1997 implied_header = brw_null_reg(); 1998 } 1999 2000 brw_pop_insn_state(p); 2001 2002 brw_fb_WRITE(p, 2003 8, /* dispatch_width */ 2004 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW), 2005 0, /* base MRF */ 2006 implied_header, 2007 inst->target, 2008 inst->mlen, 2009 0, 2010 eot); 2011} 2012 2013void 2014fs_visitor::generate_linterp(fs_inst *inst, 2015 struct brw_reg dst, struct brw_reg *src) 2016{ 2017 struct brw_reg delta_x = src[0]; 2018 struct brw_reg delta_y = src[1]; 2019 struct brw_reg interp = src[2]; 2020 2021 if (brw->has_pln && 2022 delta_y.nr == delta_x.nr + 1 && 2023 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) { 2024 brw_PLN(p, dst, interp, delta_x); 2025 } else { 2026 brw_LINE(p, brw_null_reg(), interp, delta_x); 2027 brw_MAC(p, dst, suboffset(interp, 1), delta_y); 2028 } 2029} 2030 2031void 2032fs_visitor::generate_math(fs_inst *inst, 2033 struct brw_reg dst, struct brw_reg *src) 2034{ 2035 int op; 2036 2037 switch (inst->opcode) { 2038 case FS_OPCODE_RCP: 2039 op = BRW_MATH_FUNCTION_INV; 2040 break; 2041 case FS_OPCODE_RSQ: 2042 op = BRW_MATH_FUNCTION_RSQ; 2043 break; 2044 case FS_OPCODE_SQRT: 2045 op = BRW_MATH_FUNCTION_SQRT; 2046 break; 2047 case FS_OPCODE_EXP2: 2048 op = BRW_MATH_FUNCTION_EXP; 2049 break; 2050 case FS_OPCODE_LOG2: 2051 op = BRW_MATH_FUNCTION_LOG; 2052 break; 2053 case FS_OPCODE_POW: 2054 op = BRW_MATH_FUNCTION_POW; 2055 break; 2056 case FS_OPCODE_SIN: 2057 op = BRW_MATH_FUNCTION_SIN; 2058 break; 2059 case FS_OPCODE_COS: 2060 op = BRW_MATH_FUNCTION_COS; 2061 break; 2062 default: 2063 assert(!"not reached: unknown math function"); 2064 op = 0; 2065 break; 2066 } 2067 2068 if (inst->opcode == FS_OPCODE_POW) { 2069 brw_MOV(p, brw_message_reg(3), src[1]); 2070 } 2071 2072 brw_math(p, dst, 2073 op, 2074 inst->saturate ? BRW_MATH_SATURATE_SATURATE : 2075 BRW_MATH_SATURATE_NONE, 2076 2, src[0], 2077 BRW_MATH_DATA_VECTOR, 2078 BRW_MATH_PRECISION_FULL); 2079} 2080 2081void 2082fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) 2083{ 2084 int msg_type = -1; 2085 int rlen = 4; 2086 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; 2087 2088 if (intel->gen >= 5) { 2089 switch (inst->opcode) { 2090 case FS_OPCODE_TEX: 2091 if (inst->shadow_compare) { 2092 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5; 2093 } else { 2094 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5; 2095 } 2096 break; 2097 case FS_OPCODE_TXB: 2098 if (inst->shadow_compare) { 2099 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5; 2100 } else { 2101 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5; 2102 } 2103 break; 2104 } 2105 } else { 2106 switch (inst->opcode) { 2107 case FS_OPCODE_TEX: 2108 /* Note that G45 and older determines shadow compare and dispatch width 2109 * from message length for most messages. 2110 */ 2111 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE; 2112 if (inst->shadow_compare) { 2113 assert(inst->mlen == 5); 2114 } else { 2115 assert(inst->mlen <= 6); 2116 } 2117 break; 2118 case FS_OPCODE_TXB: 2119 if (inst->shadow_compare) { 2120 assert(inst->mlen == 5); 2121 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE; 2122 } else { 2123 assert(inst->mlen == 8); 2124 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; 2125 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; 2126 } 2127 break; 2128 } 2129 } 2130 assert(msg_type != -1); 2131 2132 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) { 2133 rlen = 8; 2134 dst = vec16(dst); 2135 } 2136 2137 /* g0 header. */ 2138 src.nr--; 2139 2140 brw_SAMPLE(p, 2141 retype(dst, BRW_REGISTER_TYPE_UW), 2142 src.nr, 2143 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), 2144 SURF_INDEX_TEXTURE(inst->sampler), 2145 inst->sampler, 2146 WRITEMASK_XYZW, 2147 msg_type, 2148 rlen, 2149 inst->mlen + 1, 2150 0, 2151 1, 2152 simd_mode); 2153} 2154 2155 2156/* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input 2157 * looking like: 2158 * 2159 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br 2160 * 2161 * and we're trying to produce: 2162 * 2163 * DDX DDY 2164 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl) 2165 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br) 2166 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl) 2167 * (ss0.br - ss0.bl) (ss0.tr - ss0.br) 2168 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl) 2169 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br) 2170 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl) 2171 * (ss1.br - ss1.bl) (ss1.tr - ss1.br) 2172 * 2173 * and add another set of two more subspans if in 16-pixel dispatch mode. 2174 * 2175 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result 2176 * for each pair, and vertstride = 2 jumps us 2 elements after processing a 2177 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled 2178 * between each other. We could probably do it like ddx and swizzle the right 2179 * order later, but bail for now and just produce 2180 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4) 2181 */ 2182void 2183fs_visitor::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src) 2184{ 2185 struct brw_reg src0 = brw_reg(src.file, src.nr, 1, 2186 BRW_REGISTER_TYPE_F, 2187 BRW_VERTICAL_STRIDE_2, 2188 BRW_WIDTH_2, 2189 BRW_HORIZONTAL_STRIDE_0, 2190 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); 2191 struct brw_reg src1 = brw_reg(src.file, src.nr, 0, 2192 BRW_REGISTER_TYPE_F, 2193 BRW_VERTICAL_STRIDE_2, 2194 BRW_WIDTH_2, 2195 BRW_HORIZONTAL_STRIDE_0, 2196 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); 2197 brw_ADD(p, dst, src0, negate(src1)); 2198} 2199 2200void 2201fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src) 2202{ 2203 struct brw_reg src0 = brw_reg(src.file, src.nr, 0, 2204 BRW_REGISTER_TYPE_F, 2205 BRW_VERTICAL_STRIDE_4, 2206 BRW_WIDTH_4, 2207 BRW_HORIZONTAL_STRIDE_0, 2208 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); 2209 struct brw_reg src1 = brw_reg(src.file, src.nr, 2, 2210 BRW_REGISTER_TYPE_F, 2211 BRW_VERTICAL_STRIDE_4, 2212 BRW_WIDTH_4, 2213 BRW_HORIZONTAL_STRIDE_0, 2214 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); 2215 brw_ADD(p, dst, src0, negate(src1)); 2216} 2217 2218void 2219fs_visitor::generate_discard(fs_inst *inst, struct brw_reg temp) 2220{ 2221 struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); 2222 temp = brw_uw1_reg(temp.file, temp.nr, 0); 2223 2224 brw_push_insn_state(p); 2225 brw_set_mask_control(p, BRW_MASK_DISABLE); 2226 brw_NOT(p, temp, brw_mask_reg(1)); /* IMASK */ 2227 brw_AND(p, g0, temp, g0); 2228 brw_pop_insn_state(p); 2229} 2230 2231void 2232fs_visitor::assign_curb_setup() 2233{ 2234 c->prog_data.first_curbe_grf = c->key.nr_payload_regs; 2235 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8; 2236 2237 /* Map the offsets in the UNIFORM file to fixed HW regs. */ 2238 foreach_iter(exec_list_iterator, iter, this->instructions) { 2239 fs_inst *inst = (fs_inst *)iter.get(); 2240 2241 for (unsigned int i = 0; i < 3; i++) { 2242 if (inst->src[i].file == UNIFORM) { 2243 int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset; 2244 struct brw_reg brw_reg = brw_vec1_grf(c->prog_data.first_curbe_grf + 2245 constant_nr / 8, 2246 constant_nr % 8); 2247 2248 inst->src[i].file = FIXED_HW_REG; 2249 inst->src[i].fixed_hw_reg = brw_reg; 2250 } 2251 } 2252 } 2253} 2254 2255void 2256fs_visitor::calculate_urb_setup() 2257{ 2258 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) { 2259 urb_setup[i] = -1; 2260 } 2261 2262 int urb_next = 0; 2263 /* Figure out where each of the incoming setup attributes lands. */ 2264 if (intel->gen >= 6) { 2265 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) { 2266 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i)) { 2267 urb_setup[i] = urb_next++; 2268 } 2269 } 2270 } else { 2271 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */ 2272 for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) { 2273 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) { 2274 int fp_index; 2275 2276 if (i >= VERT_RESULT_VAR0) 2277 fp_index = i - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0); 2278 else if (i <= VERT_RESULT_TEX7) 2279 fp_index = i; 2280 else 2281 fp_index = -1; 2282 2283 if (fp_index >= 0) 2284 urb_setup[fp_index] = urb_next++; 2285 } 2286 } 2287 } 2288 2289 /* Each attribute is 4 setup channels, each of which is half a reg. */ 2290 c->prog_data.urb_read_length = urb_next * 2; 2291} 2292 2293void 2294fs_visitor::assign_urb_setup() 2295{ 2296 int urb_start = c->prog_data.first_curbe_grf + c->prog_data.curb_read_length; 2297 2298 /* Offset all the urb_setup[] index by the actual position of the 2299 * setup regs, now that the location of the constants has been chosen. 2300 */ 2301 foreach_iter(exec_list_iterator, iter, this->instructions) { 2302 fs_inst *inst = (fs_inst *)iter.get(); 2303 2304 if (inst->opcode != FS_OPCODE_LINTERP) 2305 continue; 2306 2307 assert(inst->src[2].file == FIXED_HW_REG); 2308 2309 inst->src[2].fixed_hw_reg.nr += urb_start; 2310 } 2311 2312 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length; 2313} 2314 2315static void 2316assign_reg(int *reg_hw_locations, fs_reg *reg) 2317{ 2318 if (reg->file == GRF && reg->reg != 0) { 2319 reg->hw_reg = reg_hw_locations[reg->reg] + reg->reg_offset; 2320 reg->reg = 0; 2321 } 2322} 2323 2324void 2325fs_visitor::assign_regs_trivial() 2326{ 2327 int last_grf = 0; 2328 int hw_reg_mapping[this->virtual_grf_next]; 2329 int i; 2330 2331 hw_reg_mapping[0] = 0; 2332 hw_reg_mapping[1] = this->first_non_payload_grf; 2333 for (i = 2; i < this->virtual_grf_next; i++) { 2334 hw_reg_mapping[i] = (hw_reg_mapping[i - 1] + 2335 this->virtual_grf_sizes[i - 1]); 2336 } 2337 last_grf = hw_reg_mapping[i - 1] + this->virtual_grf_sizes[i - 1]; 2338 2339 foreach_iter(exec_list_iterator, iter, this->instructions) { 2340 fs_inst *inst = (fs_inst *)iter.get(); 2341 2342 assign_reg(hw_reg_mapping, &inst->dst); 2343 assign_reg(hw_reg_mapping, &inst->src[0]); 2344 assign_reg(hw_reg_mapping, &inst->src[1]); 2345 } 2346 2347 this->grf_used = last_grf + 1; 2348} 2349 2350void 2351fs_visitor::assign_regs() 2352{ 2353 int last_grf = 0; 2354 int hw_reg_mapping[this->virtual_grf_next + 1]; 2355 int base_reg_count = BRW_MAX_GRF - this->first_non_payload_grf; 2356 int class_sizes[base_reg_count]; 2357 int class_count = 0; 2358 int aligned_pair_class = -1; 2359 2360 /* Set up the register classes. 2361 * 2362 * The base registers store a scalar value. For texture samples, 2363 * we get virtual GRFs composed of 4 contiguous hw register. For 2364 * structures and arrays, we store them as contiguous larger things 2365 * than that, though we should be able to do better most of the 2366 * time. 2367 */ 2368 class_sizes[class_count++] = 1; 2369 if (brw->has_pln && intel->gen < 6) { 2370 /* Always set up the (unaligned) pairs for gen5, so we can find 2371 * them for making the aligned pair class. 2372 */ 2373 class_sizes[class_count++] = 2; 2374 } 2375 for (int r = 1; r < this->virtual_grf_next; r++) { 2376 int i; 2377 2378 for (i = 0; i < class_count; i++) { 2379 if (class_sizes[i] == this->virtual_grf_sizes[r]) 2380 break; 2381 } 2382 if (i == class_count) { 2383 if (this->virtual_grf_sizes[r] >= base_reg_count) { 2384 fprintf(stderr, "Object too large to register allocate.\n"); 2385 this->fail = true; 2386 } 2387 2388 class_sizes[class_count++] = this->virtual_grf_sizes[r]; 2389 } 2390 } 2391 2392 int ra_reg_count = 0; 2393 int class_base_reg[class_count]; 2394 int class_reg_count[class_count]; 2395 int classes[class_count + 1]; 2396 2397 for (int i = 0; i < class_count; i++) { 2398 class_base_reg[i] = ra_reg_count; 2399 class_reg_count[i] = base_reg_count - (class_sizes[i] - 1); 2400 ra_reg_count += class_reg_count[i]; 2401 } 2402 2403 struct ra_regs *regs = ra_alloc_reg_set(ra_reg_count); 2404 for (int i = 0; i < class_count; i++) { 2405 classes[i] = ra_alloc_reg_class(regs); 2406 2407 for (int i_r = 0; i_r < class_reg_count[i]; i_r++) { 2408 ra_class_add_reg(regs, classes[i], class_base_reg[i] + i_r); 2409 } 2410 2411 /* Add conflicts between our contiguous registers aliasing 2412 * base regs and other register classes' contiguous registers 2413 * that alias base regs, or the base regs themselves for classes[0]. 2414 */ 2415 for (int c = 0; c <= i; c++) { 2416 for (int i_r = 0; i_r < class_reg_count[i]; i_r++) { 2417 for (int c_r = MAX2(0, i_r - (class_sizes[c] - 1)); 2418 c_r < MIN2(class_reg_count[c], i_r + class_sizes[i]); 2419 c_r++) { 2420 2421 if (0) { 2422 printf("%d/%d conflicts %d/%d\n", 2423 class_sizes[i], this->first_non_payload_grf + i_r, 2424 class_sizes[c], this->first_non_payload_grf + c_r); 2425 } 2426 2427 ra_add_reg_conflict(regs, 2428 class_base_reg[i] + i_r, 2429 class_base_reg[c] + c_r); 2430 } 2431 } 2432 } 2433 } 2434 2435 /* Add a special class for aligned pairs, which we'll put delta_x/y 2436 * in on gen5 so that we can do PLN. 2437 */ 2438 if (brw->has_pln && intel->gen < 6) { 2439 int reg_count = (base_reg_count - 1) / 2; 2440 int unaligned_pair_class = 1; 2441 assert(class_sizes[unaligned_pair_class] == 2); 2442 2443 aligned_pair_class = class_count; 2444 classes[aligned_pair_class] = ra_alloc_reg_class(regs); 2445 class_base_reg[aligned_pair_class] = 0; 2446 class_reg_count[aligned_pair_class] = 0; 2447 int start = (this->first_non_payload_grf & 1) ? 1 : 0; 2448 2449 for (int i = 0; i < reg_count; i++) { 2450 ra_class_add_reg(regs, classes[aligned_pair_class], 2451 class_base_reg[unaligned_pair_class] + i * 2 + start); 2452 } 2453 class_count++; 2454 } 2455 2456 ra_set_finalize(regs); 2457 2458 struct ra_graph *g = ra_alloc_interference_graph(regs, 2459 this->virtual_grf_next); 2460 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1 2461 * with nodes. 2462 */ 2463 ra_set_node_class(g, 0, classes[0]); 2464 2465 for (int i = 1; i < this->virtual_grf_next; i++) { 2466 for (int c = 0; c < class_count; c++) { 2467 if (class_sizes[c] == this->virtual_grf_sizes[i]) { 2468 if (aligned_pair_class >= 0 && 2469 this->delta_x.reg == i) { 2470 ra_set_node_class(g, i, classes[aligned_pair_class]); 2471 } else { 2472 ra_set_node_class(g, i, classes[c]); 2473 } 2474 break; 2475 } 2476 } 2477 2478 for (int j = 1; j < i; j++) { 2479 if (virtual_grf_interferes(i, j)) { 2480 ra_add_node_interference(g, i, j); 2481 } 2482 } 2483 } 2484 2485 /* FINISHME: Handle spilling */ 2486 if (!ra_allocate_no_spills(g)) { 2487 fprintf(stderr, "Failed to allocate registers.\n"); 2488 this->fail = true; 2489 return; 2490 } 2491 2492 /* Get the chosen virtual registers for each node, and map virtual 2493 * regs in the register classes back down to real hardware reg 2494 * numbers. 2495 */ 2496 hw_reg_mapping[0] = 0; /* unused */ 2497 for (int i = 1; i < this->virtual_grf_next; i++) { 2498 int reg = ra_get_node_reg(g, i); 2499 int hw_reg = -1; 2500 2501 for (int c = 0; c < class_count; c++) { 2502 if (reg >= class_base_reg[c] && 2503 reg < class_base_reg[c] + class_reg_count[c]) { 2504 hw_reg = reg - class_base_reg[c]; 2505 break; 2506 } 2507 } 2508 2509 assert(hw_reg != -1); 2510 hw_reg_mapping[i] = this->first_non_payload_grf + hw_reg; 2511 last_grf = MAX2(last_grf, 2512 hw_reg_mapping[i] + this->virtual_grf_sizes[i] - 1); 2513 } 2514 2515 foreach_iter(exec_list_iterator, iter, this->instructions) { 2516 fs_inst *inst = (fs_inst *)iter.get(); 2517 2518 assign_reg(hw_reg_mapping, &inst->dst); 2519 assign_reg(hw_reg_mapping, &inst->src[0]); 2520 assign_reg(hw_reg_mapping, &inst->src[1]); 2521 } 2522 2523 this->grf_used = last_grf + 1; 2524 2525 talloc_free(g); 2526 talloc_free(regs); 2527} 2528 2529void 2530fs_visitor::calculate_live_intervals() 2531{ 2532 int num_vars = this->virtual_grf_next; 2533 int *def = talloc_array(mem_ctx, int, num_vars); 2534 int *use = talloc_array(mem_ctx, int, num_vars); 2535 int loop_depth = 0; 2536 int loop_start = 0; 2537 2538 for (int i = 0; i < num_vars; i++) { 2539 def[i] = 1 << 30; 2540 use[i] = -1; 2541 } 2542 2543 int ip = 0; 2544 foreach_iter(exec_list_iterator, iter, this->instructions) { 2545 fs_inst *inst = (fs_inst *)iter.get(); 2546 2547 if (inst->opcode == BRW_OPCODE_DO) { 2548 if (loop_depth++ == 0) 2549 loop_start = ip; 2550 } else if (inst->opcode == BRW_OPCODE_WHILE) { 2551 loop_depth--; 2552 2553 if (loop_depth == 0) { 2554 /* FINISHME: 2555 * 2556 * Patches up any vars marked for use within the loop as 2557 * live until the end. This is conservative, as there 2558 * will often be variables defined and used inside the 2559 * loop but dead at the end of the loop body. 2560 */ 2561 for (int i = 0; i < num_vars; i++) { 2562 if (use[i] == loop_start) { 2563 use[i] = ip; 2564 } 2565 } 2566 } 2567 } else { 2568 int eip = ip; 2569 2570 if (loop_depth) 2571 eip = loop_start; 2572 2573 for (unsigned int i = 0; i < 3; i++) { 2574 if (inst->src[i].file == GRF && inst->src[i].reg != 0) { 2575 use[inst->src[i].reg] = MAX2(use[inst->src[i].reg], eip); 2576 } 2577 } 2578 if (inst->dst.file == GRF && inst->dst.reg != 0) { 2579 def[inst->dst.reg] = MIN2(def[inst->dst.reg], eip); 2580 } 2581 } 2582 2583 ip++; 2584 } 2585 2586 talloc_free(this->virtual_grf_def); 2587 talloc_free(this->virtual_grf_use); 2588 this->virtual_grf_def = def; 2589 this->virtual_grf_use = use; 2590} 2591 2592/** 2593 * Attempts to move immediate constants into the immediate 2594 * constant slot of following instructions. 2595 * 2596 * Immediate constants are a bit tricky -- they have to be in the last 2597 * operand slot, you can't do abs/negate on them, 2598 */ 2599 2600bool 2601fs_visitor::propagate_constants() 2602{ 2603 bool progress = false; 2604 2605 foreach_iter(exec_list_iterator, iter, this->instructions) { 2606 fs_inst *inst = (fs_inst *)iter.get(); 2607 2608 if (inst->opcode != BRW_OPCODE_MOV || 2609 inst->predicated || 2610 inst->dst.file != GRF || inst->src[0].file != IMM || 2611 inst->dst.type != inst->src[0].type) 2612 continue; 2613 2614 /* Don't bother with cases where we should have had the 2615 * operation on the constant folded in GLSL already. 2616 */ 2617 if (inst->saturate) 2618 continue; 2619 2620 /* Found a move of a constant to a GRF. Find anything else using the GRF 2621 * before it's written, and replace it with the constant if we can. 2622 */ 2623 exec_list_iterator scan_iter = iter; 2624 scan_iter.next(); 2625 for (; scan_iter.has_next(); scan_iter.next()) { 2626 fs_inst *scan_inst = (fs_inst *)scan_iter.get(); 2627 2628 if (scan_inst->opcode == BRW_OPCODE_DO || 2629 scan_inst->opcode == BRW_OPCODE_WHILE || 2630 scan_inst->opcode == BRW_OPCODE_ELSE || 2631 scan_inst->opcode == BRW_OPCODE_ENDIF) { 2632 break; 2633 } 2634 2635 for (int i = 2; i >= 0; i--) { 2636 if (scan_inst->src[i].file != GRF || 2637 scan_inst->src[i].reg != inst->dst.reg || 2638 scan_inst->src[i].reg_offset != inst->dst.reg_offset) 2639 continue; 2640 2641 /* Don't bother with cases where we should have had the 2642 * operation on the constant folded in GLSL already. 2643 */ 2644 if (scan_inst->src[i].negate || scan_inst->src[i].abs) 2645 continue; 2646 2647 switch (scan_inst->opcode) { 2648 case BRW_OPCODE_MOV: 2649 scan_inst->src[i] = inst->src[0]; 2650 progress = true; 2651 break; 2652 2653 case BRW_OPCODE_MUL: 2654 case BRW_OPCODE_ADD: 2655 if (i == 1) { 2656 scan_inst->src[i] = inst->src[0]; 2657 progress = true; 2658 } else if (i == 0 && scan_inst->src[1].file != IMM) { 2659 /* Fit this constant in by commuting the operands */ 2660 scan_inst->src[0] = scan_inst->src[1]; 2661 scan_inst->src[1] = inst->src[0]; 2662 } 2663 break; 2664 case BRW_OPCODE_CMP: 2665 if (i == 1) { 2666 scan_inst->src[i] = inst->src[0]; 2667 progress = true; 2668 } 2669 } 2670 } 2671 2672 if (scan_inst->dst.file == GRF && 2673 scan_inst->dst.reg == inst->dst.reg && 2674 (scan_inst->dst.reg_offset == inst->dst.reg_offset || 2675 scan_inst->opcode == FS_OPCODE_TEX)) { 2676 break; 2677 } 2678 } 2679 } 2680 2681 return progress; 2682} 2683/** 2684 * Must be called after calculate_live_intervales() to remove unused 2685 * writes to registers -- register allocation will fail otherwise 2686 * because something deffed but not used won't be considered to 2687 * interfere with other regs. 2688 */ 2689bool 2690fs_visitor::dead_code_eliminate() 2691{ 2692 bool progress = false; 2693 int num_vars = this->virtual_grf_next; 2694 bool dead[num_vars]; 2695 2696 for (int i = 0; i < num_vars; i++) { 2697 /* This would be ">=", but FS_OPCODE_DISCARD has a src == dst where 2698 * it writes dst then reads it as src. 2699 */ 2700 dead[i] = this->virtual_grf_def[i] > this->virtual_grf_use[i]; 2701 2702 if (dead[i]) { 2703 /* Mark off its interval so it won't interfere with anything. */ 2704 this->virtual_grf_def[i] = -1; 2705 this->virtual_grf_use[i] = -1; 2706 } 2707 } 2708 2709 foreach_iter(exec_list_iterator, iter, this->instructions) { 2710 fs_inst *inst = (fs_inst *)iter.get(); 2711 2712 if (inst->dst.file == GRF && dead[inst->dst.reg]) { 2713 inst->remove(); 2714 progress = true; 2715 } 2716 } 2717 2718 return progress; 2719} 2720 2721bool 2722fs_visitor::virtual_grf_interferes(int a, int b) 2723{ 2724 int start = MAX2(this->virtual_grf_def[a], this->virtual_grf_def[b]); 2725 int end = MIN2(this->virtual_grf_use[a], this->virtual_grf_use[b]); 2726 2727 /* For dead code, just check if the def interferes with the other range. */ 2728 if (this->virtual_grf_use[a] == -1) { 2729 return (this->virtual_grf_def[a] >= this->virtual_grf_def[b] && 2730 this->virtual_grf_def[a] < this->virtual_grf_use[b]); 2731 } 2732 if (this->virtual_grf_use[b] == -1) { 2733 return (this->virtual_grf_def[b] >= this->virtual_grf_def[a] && 2734 this->virtual_grf_def[b] < this->virtual_grf_use[a]); 2735 } 2736 2737 return start <= end; 2738} 2739 2740static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg) 2741{ 2742 struct brw_reg brw_reg; 2743 2744 switch (reg->file) { 2745 case GRF: 2746 case ARF: 2747 case MRF: 2748 brw_reg = brw_vec8_reg(reg->file, 2749 reg->hw_reg, 0); 2750 brw_reg = retype(brw_reg, reg->type); 2751 break; 2752 case IMM: 2753 switch (reg->type) { 2754 case BRW_REGISTER_TYPE_F: 2755 brw_reg = brw_imm_f(reg->imm.f); 2756 break; 2757 case BRW_REGISTER_TYPE_D: 2758 brw_reg = brw_imm_d(reg->imm.i); 2759 break; 2760 case BRW_REGISTER_TYPE_UD: 2761 brw_reg = brw_imm_ud(reg->imm.u); 2762 break; 2763 default: 2764 assert(!"not reached"); 2765 break; 2766 } 2767 break; 2768 case FIXED_HW_REG: 2769 brw_reg = reg->fixed_hw_reg; 2770 break; 2771 case BAD_FILE: 2772 /* Probably unused. */ 2773 brw_reg = brw_null_reg(); 2774 break; 2775 case UNIFORM: 2776 assert(!"not reached"); 2777 brw_reg = brw_null_reg(); 2778 break; 2779 } 2780 if (reg->abs) 2781 brw_reg = brw_abs(brw_reg); 2782 if (reg->negate) 2783 brw_reg = negate(brw_reg); 2784 2785 return brw_reg; 2786} 2787 2788void 2789fs_visitor::generate_code() 2790{ 2791 unsigned int annotation_len = 0; 2792 int last_native_inst = 0; 2793 struct brw_instruction *if_stack[16], *loop_stack[16]; 2794 int if_stack_depth = 0, loop_stack_depth = 0; 2795 int if_depth_in_loop[16]; 2796 2797 if_depth_in_loop[loop_stack_depth] = 0; 2798 2799 memset(&if_stack, 0, sizeof(if_stack)); 2800 foreach_iter(exec_list_iterator, iter, this->instructions) { 2801 fs_inst *inst = (fs_inst *)iter.get(); 2802 struct brw_reg src[3], dst; 2803 2804 for (unsigned int i = 0; i < 3; i++) { 2805 src[i] = brw_reg_from_fs_reg(&inst->src[i]); 2806 } 2807 dst = brw_reg_from_fs_reg(&inst->dst); 2808 2809 brw_set_conditionalmod(p, inst->conditional_mod); 2810 brw_set_predicate_control(p, inst->predicated); 2811 2812 switch (inst->opcode) { 2813 case BRW_OPCODE_MOV: 2814 brw_MOV(p, dst, src[0]); 2815 break; 2816 case BRW_OPCODE_ADD: 2817 brw_ADD(p, dst, src[0], src[1]); 2818 break; 2819 case BRW_OPCODE_MUL: 2820 brw_MUL(p, dst, src[0], src[1]); 2821 break; 2822 2823 case BRW_OPCODE_FRC: 2824 brw_FRC(p, dst, src[0]); 2825 break; 2826 case BRW_OPCODE_RNDD: 2827 brw_RNDD(p, dst, src[0]); 2828 break; 2829 case BRW_OPCODE_RNDZ: 2830 brw_RNDZ(p, dst, src[0]); 2831 break; 2832 2833 case BRW_OPCODE_AND: 2834 brw_AND(p, dst, src[0], src[1]); 2835 break; 2836 case BRW_OPCODE_OR: 2837 brw_OR(p, dst, src[0], src[1]); 2838 break; 2839 case BRW_OPCODE_XOR: 2840 brw_XOR(p, dst, src[0], src[1]); 2841 break; 2842 case BRW_OPCODE_NOT: 2843 brw_NOT(p, dst, src[0]); 2844 break; 2845 case BRW_OPCODE_ASR: 2846 brw_ASR(p, dst, src[0], src[1]); 2847 break; 2848 case BRW_OPCODE_SHR: 2849 brw_SHR(p, dst, src[0], src[1]); 2850 break; 2851 case BRW_OPCODE_SHL: 2852 brw_SHL(p, dst, src[0], src[1]); 2853 break; 2854 2855 case BRW_OPCODE_CMP: 2856 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); 2857 break; 2858 case BRW_OPCODE_SEL: 2859 brw_SEL(p, dst, src[0], src[1]); 2860 break; 2861 2862 case BRW_OPCODE_IF: 2863 assert(if_stack_depth < 16); 2864 if_stack[if_stack_depth] = brw_IF(p, BRW_EXECUTE_8); 2865 if_depth_in_loop[loop_stack_depth]++; 2866 if_stack_depth++; 2867 break; 2868 case BRW_OPCODE_ELSE: 2869 if_stack[if_stack_depth - 1] = 2870 brw_ELSE(p, if_stack[if_stack_depth - 1]); 2871 break; 2872 case BRW_OPCODE_ENDIF: 2873 if_stack_depth--; 2874 brw_ENDIF(p , if_stack[if_stack_depth]); 2875 if_depth_in_loop[loop_stack_depth]--; 2876 break; 2877 2878 case BRW_OPCODE_DO: 2879 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8); 2880 if_depth_in_loop[loop_stack_depth] = 0; 2881 break; 2882 2883 case BRW_OPCODE_BREAK: 2884 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]); 2885 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 2886 break; 2887 case BRW_OPCODE_CONTINUE: 2888 brw_CONT(p, if_depth_in_loop[loop_stack_depth]); 2889 brw_set_predicate_control(p, BRW_PREDICATE_NONE); 2890 break; 2891 2892 case BRW_OPCODE_WHILE: { 2893 struct brw_instruction *inst0, *inst1; 2894 GLuint br = 1; 2895 2896 if (intel->gen >= 5) 2897 br = 2; 2898 2899 assert(loop_stack_depth > 0); 2900 loop_stack_depth--; 2901 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]); 2902 /* patch all the BREAK/CONT instructions from last BGNLOOP */ 2903 while (inst0 > loop_stack[loop_stack_depth]) { 2904 inst0--; 2905 if (inst0->header.opcode == BRW_OPCODE_BREAK && 2906 inst0->bits3.if_else.jump_count == 0) { 2907 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); 2908 } 2909 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE && 2910 inst0->bits3.if_else.jump_count == 0) { 2911 inst0->bits3.if_else.jump_count = br * (inst1 - inst0); 2912 } 2913 } 2914 } 2915 break; 2916 2917 case FS_OPCODE_RCP: 2918 case FS_OPCODE_RSQ: 2919 case FS_OPCODE_SQRT: 2920 case FS_OPCODE_EXP2: 2921 case FS_OPCODE_LOG2: 2922 case FS_OPCODE_POW: 2923 case FS_OPCODE_SIN: 2924 case FS_OPCODE_COS: 2925 generate_math(inst, dst, src); 2926 break; 2927 case FS_OPCODE_LINTERP: 2928 generate_linterp(inst, dst, src); 2929 break; 2930 case FS_OPCODE_TEX: 2931 case FS_OPCODE_TXB: 2932 case FS_OPCODE_TXL: 2933 generate_tex(inst, dst, src[0]); 2934 break; 2935 case FS_OPCODE_DISCARD: 2936 generate_discard(inst, dst /* src0 == dst */); 2937 break; 2938 case FS_OPCODE_DDX: 2939 generate_ddx(inst, dst, src[0]); 2940 break; 2941 case FS_OPCODE_DDY: 2942 generate_ddy(inst, dst, src[0]); 2943 break; 2944 case FS_OPCODE_FB_WRITE: 2945 generate_fb_write(inst); 2946 break; 2947 default: 2948 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { 2949 _mesa_problem(ctx, "Unsupported opcode `%s' in FS", 2950 brw_opcodes[inst->opcode].name); 2951 } else { 2952 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode); 2953 } 2954 this->fail = true; 2955 } 2956 2957 if (annotation_len < p->nr_insn) { 2958 annotation_len *= 2; 2959 if (annotation_len < 16) 2960 annotation_len = 16; 2961 2962 this->annotation_string = talloc_realloc(this->mem_ctx, 2963 annotation_string, 2964 const char *, 2965 annotation_len); 2966 this->annotation_ir = talloc_realloc(this->mem_ctx, 2967 annotation_ir, 2968 ir_instruction *, 2969 annotation_len); 2970 } 2971 2972 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { 2973 this->annotation_string[i] = inst->annotation; 2974 this->annotation_ir[i] = inst->ir; 2975 } 2976 last_native_inst = p->nr_insn; 2977 } 2978} 2979 2980GLboolean 2981brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c) 2982{ 2983 struct brw_compile *p = &c->func; 2984 struct intel_context *intel = &brw->intel; 2985 GLcontext *ctx = &intel->ctx; 2986 struct brw_shader *shader = NULL; 2987 struct gl_shader_program *prog = ctx->Shader.CurrentProgram; 2988 2989 if (!prog) 2990 return GL_FALSE; 2991 2992 if (!using_new_fs) 2993 return GL_FALSE; 2994 2995 for (unsigned int i = 0; i < prog->_NumLinkedShaders; i++) { 2996 if (prog->_LinkedShaders[i]->Type == GL_FRAGMENT_SHADER) { 2997 shader = (struct brw_shader *)prog->_LinkedShaders[i]; 2998 break; 2999 } 3000 } 3001 if (!shader) 3002 return GL_FALSE; 3003 3004 /* We always use 8-wide mode, at least for now. For one, flow 3005 * control only works in 8-wide. Also, when we're fragment shader 3006 * bound, we're almost always under register pressure as well, so 3007 * 8-wide would save us from the performance cliff of spilling 3008 * regs. 3009 */ 3010 c->dispatch_width = 8; 3011 3012 if (INTEL_DEBUG & DEBUG_WM) { 3013 printf("GLSL IR for native fragment shader %d:\n", prog->Name); 3014 _mesa_print_ir(shader->ir, NULL); 3015 printf("\n"); 3016 } 3017 3018 /* Now the main event: Visit the shader IR and generate our FS IR for it. 3019 */ 3020 fs_visitor v(c, shader); 3021 3022 if (0) { 3023 v.emit_dummy_fs(); 3024 } else { 3025 v.calculate_urb_setup(); 3026 if (intel->gen < 6) 3027 v.emit_interpolation_setup_gen4(); 3028 else 3029 v.emit_interpolation_setup_gen6(); 3030 3031 /* Generate FS IR for main(). (the visitor only descends into 3032 * functions called "main"). 3033 */ 3034 foreach_iter(exec_list_iterator, iter, *shader->ir) { 3035 ir_instruction *ir = (ir_instruction *)iter.get(); 3036 v.base_ir = ir; 3037 ir->accept(&v); 3038 } 3039 3040 v.emit_fb_writes(); 3041 v.assign_curb_setup(); 3042 v.assign_urb_setup(); 3043 3044 bool progress; 3045 do { 3046 progress = false; 3047 3048 v.calculate_live_intervals(); 3049 progress = v.propagate_constants() || progress; 3050 progress = v.dead_code_eliminate() || progress; 3051 } while (progress); 3052 3053 if (0) 3054 v.assign_regs_trivial(); 3055 else 3056 v.assign_regs(); 3057 } 3058 3059 if (!v.fail) 3060 v.generate_code(); 3061 3062 assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */ 3063 3064 if (v.fail) 3065 return GL_FALSE; 3066 3067 if (INTEL_DEBUG & DEBUG_WM) { 3068 const char *last_annotation_string = NULL; 3069 ir_instruction *last_annotation_ir = NULL; 3070 3071 printf("Native code for fragment shader %d:\n", prog->Name); 3072 for (unsigned int i = 0; i < p->nr_insn; i++) { 3073 if (last_annotation_ir != v.annotation_ir[i]) { 3074 last_annotation_ir = v.annotation_ir[i]; 3075 if (last_annotation_ir) { 3076 printf(" "); 3077 last_annotation_ir->print(); 3078 printf("\n"); 3079 } 3080 } 3081 if (last_annotation_string != v.annotation_string[i]) { 3082 last_annotation_string = v.annotation_string[i]; 3083 if (last_annotation_string) 3084 printf(" %s\n", last_annotation_string); 3085 } 3086 brw_disasm(stdout, &p->store[i], intel->gen); 3087 } 3088 printf("\n"); 3089 } 3090 3091 c->prog_data.total_grf = v.grf_used; 3092 c->prog_data.total_scratch = 0; 3093 3094 return GL_TRUE; 3095} 3096