brw_fs.cpp revision fe27916ddf41b9fb60c334c47c1aa81b8dd9005e
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** @file brw_fs.cpp 25 * 26 * This file drives the GLSL IR -> LIR translation, contains the 27 * optimizations on the LIR, and drives the generation of native code 28 * from the LIR. 29 */ 30 31extern "C" { 32 33#include <sys/types.h> 34 35#include "main/macros.h" 36#include "main/shaderobj.h" 37#include "main/uniforms.h" 38#include "main/fbobject.h" 39#include "program/prog_parameter.h" 40#include "program/prog_print.h" 41#include "program/register_allocate.h" 42#include "program/sampler.h" 43#include "program/hash_table.h" 44#include "brw_context.h" 45#include "brw_eu.h" 46#include "brw_wm.h" 47} 48#include "brw_shader.h" 49#include "brw_fs.h" 50#include "glsl/glsl_types.h" 51#include "glsl/ir_print_visitor.h" 52 53void 54fs_inst::init() 55{ 56 memset(this, 0, sizeof(*this)); 57 this->opcode = BRW_OPCODE_NOP; 58 this->conditional_mod = BRW_CONDITIONAL_NONE; 59 60 this->dst = reg_undef; 61 this->src[0] = reg_undef; 62 this->src[1] = reg_undef; 63 this->src[2] = reg_undef; 64} 65 66fs_inst::fs_inst() 67{ 68 init(); 69} 70 71fs_inst::fs_inst(enum opcode opcode) 72{ 73 init(); 74 this->opcode = opcode; 75} 76 77fs_inst::fs_inst(enum opcode opcode, fs_reg dst) 78{ 79 init(); 80 this->opcode = opcode; 81 this->dst = dst; 82 83 if (dst.file == GRF) 84 assert(dst.reg_offset >= 0); 85} 86 87fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0) 88{ 89 init(); 90 this->opcode = opcode; 91 this->dst = dst; 92 this->src[0] = src0; 93 94 if (dst.file == GRF) 95 assert(dst.reg_offset >= 0); 96 if (src[0].file == GRF) 97 assert(src[0].reg_offset >= 0); 98} 99 100fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1) 101{ 102 init(); 103 this->opcode = opcode; 104 this->dst = dst; 105 this->src[0] = src0; 106 this->src[1] = src1; 107 108 if (dst.file == GRF) 109 assert(dst.reg_offset >= 0); 110 if (src[0].file == GRF) 111 assert(src[0].reg_offset >= 0); 112 if (src[1].file == GRF) 113 assert(src[1].reg_offset >= 0); 114} 115 116fs_inst::fs_inst(enum opcode opcode, fs_reg dst, 117 fs_reg src0, fs_reg src1, fs_reg src2) 118{ 119 init(); 120 this->opcode = opcode; 121 this->dst = dst; 122 this->src[0] = src0; 123 this->src[1] = src1; 124 this->src[2] = src2; 125 126 if (dst.file == GRF) 127 assert(dst.reg_offset >= 0); 128 if (src[0].file == GRF) 129 assert(src[0].reg_offset >= 0); 130 if (src[1].file == GRF) 131 assert(src[1].reg_offset >= 0); 132 if (src[2].file == GRF) 133 assert(src[2].reg_offset >= 0); 134} 135 136bool 137fs_inst::equals(fs_inst *inst) 138{ 139 return (opcode == inst->opcode && 140 dst.equals(inst->dst) && 141 src[0].equals(inst->src[0]) && 142 src[1].equals(inst->src[1]) && 143 src[2].equals(inst->src[2]) && 144 saturate == inst->saturate && 145 predicated == inst->predicated && 146 conditional_mod == inst->conditional_mod && 147 mlen == inst->mlen && 148 base_mrf == inst->base_mrf && 149 sampler == inst->sampler && 150 target == inst->target && 151 eot == inst->eot && 152 header_present == inst->header_present && 153 shadow_compare == inst->shadow_compare && 154 offset == inst->offset); 155} 156 157int 158fs_inst::regs_written() 159{ 160 if (is_tex()) 161 return 4; 162 163 /* The SINCOS and INT_DIV_QUOTIENT_AND_REMAINDER math functions return 2, 164 * but we don't currently use them...nor do we have an opcode for them. 165 */ 166 167 return 1; 168} 169 170bool 171fs_inst::is_tex() 172{ 173 return (opcode == SHADER_OPCODE_TEX || 174 opcode == FS_OPCODE_TXB || 175 opcode == SHADER_OPCODE_TXD || 176 opcode == SHADER_OPCODE_TXF || 177 opcode == SHADER_OPCODE_TXL || 178 opcode == SHADER_OPCODE_TXS); 179} 180 181bool 182fs_inst::is_math() 183{ 184 return (opcode == SHADER_OPCODE_RCP || 185 opcode == SHADER_OPCODE_RSQ || 186 opcode == SHADER_OPCODE_SQRT || 187 opcode == SHADER_OPCODE_EXP2 || 188 opcode == SHADER_OPCODE_LOG2 || 189 opcode == SHADER_OPCODE_SIN || 190 opcode == SHADER_OPCODE_COS || 191 opcode == SHADER_OPCODE_INT_QUOTIENT || 192 opcode == SHADER_OPCODE_INT_REMAINDER || 193 opcode == SHADER_OPCODE_POW); 194} 195 196void 197fs_reg::init() 198{ 199 memset(this, 0, sizeof(*this)); 200 this->smear = -1; 201} 202 203/** Generic unset register constructor. */ 204fs_reg::fs_reg() 205{ 206 init(); 207 this->file = BAD_FILE; 208} 209 210/** Immediate value constructor. */ 211fs_reg::fs_reg(float f) 212{ 213 init(); 214 this->file = IMM; 215 this->type = BRW_REGISTER_TYPE_F; 216 this->imm.f = f; 217} 218 219/** Immediate value constructor. */ 220fs_reg::fs_reg(int32_t i) 221{ 222 init(); 223 this->file = IMM; 224 this->type = BRW_REGISTER_TYPE_D; 225 this->imm.i = i; 226} 227 228/** Immediate value constructor. */ 229fs_reg::fs_reg(uint32_t u) 230{ 231 init(); 232 this->file = IMM; 233 this->type = BRW_REGISTER_TYPE_UD; 234 this->imm.u = u; 235} 236 237/** Fixed brw_reg Immediate value constructor. */ 238fs_reg::fs_reg(struct brw_reg fixed_hw_reg) 239{ 240 init(); 241 this->file = FIXED_HW_REG; 242 this->fixed_hw_reg = fixed_hw_reg; 243 this->type = fixed_hw_reg.type; 244} 245 246bool 247fs_reg::equals(const fs_reg &r) const 248{ 249 return (file == r.file && 250 reg == r.reg && 251 reg_offset == r.reg_offset && 252 type == r.type && 253 negate == r.negate && 254 abs == r.abs && 255 memcmp(&fixed_hw_reg, &r.fixed_hw_reg, 256 sizeof(fixed_hw_reg)) == 0 && 257 smear == r.smear && 258 imm.u == r.imm.u); 259} 260 261int 262fs_visitor::type_size(const struct glsl_type *type) 263{ 264 unsigned int size, i; 265 266 switch (type->base_type) { 267 case GLSL_TYPE_UINT: 268 case GLSL_TYPE_INT: 269 case GLSL_TYPE_FLOAT: 270 case GLSL_TYPE_BOOL: 271 return type->components(); 272 case GLSL_TYPE_ARRAY: 273 return type_size(type->fields.array) * type->length; 274 case GLSL_TYPE_STRUCT: 275 size = 0; 276 for (i = 0; i < type->length; i++) { 277 size += type_size(type->fields.structure[i].type); 278 } 279 return size; 280 case GLSL_TYPE_SAMPLER: 281 /* Samplers take up no register space, since they're baked in at 282 * link time. 283 */ 284 return 0; 285 default: 286 assert(!"not reached"); 287 return 0; 288 } 289} 290 291void 292fs_visitor::fail(const char *format, ...) 293{ 294 va_list va; 295 char *msg; 296 297 if (failed) 298 return; 299 300 failed = true; 301 302 va_start(va, format); 303 msg = ralloc_vasprintf(mem_ctx, format, va); 304 va_end(va); 305 msg = ralloc_asprintf(mem_ctx, "FS compile failed: %s\n", msg); 306 307 this->fail_msg = msg; 308 309 if (INTEL_DEBUG & DEBUG_WM) { 310 fprintf(stderr, "%s", msg); 311 } 312} 313 314fs_inst * 315fs_visitor::emit(enum opcode opcode) 316{ 317 return emit(fs_inst(opcode)); 318} 319 320fs_inst * 321fs_visitor::emit(enum opcode opcode, fs_reg dst) 322{ 323 return emit(fs_inst(opcode, dst)); 324} 325 326fs_inst * 327fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0) 328{ 329 return emit(fs_inst(opcode, dst, src0)); 330} 331 332fs_inst * 333fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1) 334{ 335 return emit(fs_inst(opcode, dst, src0, src1)); 336} 337 338fs_inst * 339fs_visitor::emit(enum opcode opcode, fs_reg dst, 340 fs_reg src0, fs_reg src1, fs_reg src2) 341{ 342 return emit(fs_inst(opcode, dst, src0, src1, src2)); 343} 344 345void 346fs_visitor::push_force_uncompressed() 347{ 348 force_uncompressed_stack++; 349} 350 351void 352fs_visitor::pop_force_uncompressed() 353{ 354 force_uncompressed_stack--; 355 assert(force_uncompressed_stack >= 0); 356} 357 358void 359fs_visitor::push_force_sechalf() 360{ 361 force_sechalf_stack++; 362} 363 364void 365fs_visitor::pop_force_sechalf() 366{ 367 force_sechalf_stack--; 368 assert(force_sechalf_stack >= 0); 369} 370 371/** 372 * Returns how many MRFs an FS opcode will write over. 373 * 374 * Note that this is not the 0 or 1 implied writes in an actual gen 375 * instruction -- the FS opcodes often generate MOVs in addition. 376 */ 377int 378fs_visitor::implied_mrf_writes(fs_inst *inst) 379{ 380 if (inst->mlen == 0) 381 return 0; 382 383 switch (inst->opcode) { 384 case SHADER_OPCODE_RCP: 385 case SHADER_OPCODE_RSQ: 386 case SHADER_OPCODE_SQRT: 387 case SHADER_OPCODE_EXP2: 388 case SHADER_OPCODE_LOG2: 389 case SHADER_OPCODE_SIN: 390 case SHADER_OPCODE_COS: 391 return 1 * c->dispatch_width / 8; 392 case SHADER_OPCODE_POW: 393 case SHADER_OPCODE_INT_QUOTIENT: 394 case SHADER_OPCODE_INT_REMAINDER: 395 return 2 * c->dispatch_width / 8; 396 case SHADER_OPCODE_TEX: 397 case FS_OPCODE_TXB: 398 case SHADER_OPCODE_TXD: 399 case SHADER_OPCODE_TXF: 400 case SHADER_OPCODE_TXL: 401 case SHADER_OPCODE_TXS: 402 return 1; 403 case FS_OPCODE_FB_WRITE: 404 return 2; 405 case FS_OPCODE_PULL_CONSTANT_LOAD: 406 case FS_OPCODE_UNSPILL: 407 return 1; 408 case FS_OPCODE_SPILL: 409 return 2; 410 default: 411 assert(!"not reached"); 412 return inst->mlen; 413 } 414} 415 416int 417fs_visitor::virtual_grf_alloc(int size) 418{ 419 if (virtual_grf_array_size <= virtual_grf_next) { 420 if (virtual_grf_array_size == 0) 421 virtual_grf_array_size = 16; 422 else 423 virtual_grf_array_size *= 2; 424 virtual_grf_sizes = reralloc(mem_ctx, virtual_grf_sizes, int, 425 virtual_grf_array_size); 426 } 427 virtual_grf_sizes[virtual_grf_next] = size; 428 return virtual_grf_next++; 429} 430 431/** Fixed HW reg constructor. */ 432fs_reg::fs_reg(enum register_file file, int reg) 433{ 434 init(); 435 this->file = file; 436 this->reg = reg; 437 this->type = BRW_REGISTER_TYPE_F; 438} 439 440/** Fixed HW reg constructor. */ 441fs_reg::fs_reg(enum register_file file, int reg, uint32_t type) 442{ 443 init(); 444 this->file = file; 445 this->reg = reg; 446 this->type = type; 447} 448 449/** Automatic reg constructor. */ 450fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type) 451{ 452 init(); 453 454 this->file = GRF; 455 this->reg = v->virtual_grf_alloc(v->type_size(type)); 456 this->reg_offset = 0; 457 this->type = brw_type_for_base_type(type); 458} 459 460fs_reg * 461fs_visitor::variable_storage(ir_variable *var) 462{ 463 return (fs_reg *)hash_table_find(this->variable_ht, var); 464} 465 466void 467import_uniforms_callback(const void *key, 468 void *data, 469 void *closure) 470{ 471 struct hash_table *dst_ht = (struct hash_table *)closure; 472 const fs_reg *reg = (const fs_reg *)data; 473 474 if (reg->file != UNIFORM) 475 return; 476 477 hash_table_insert(dst_ht, data, key); 478} 479 480/* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch. 481 * This brings in those uniform definitions 482 */ 483void 484fs_visitor::import_uniforms(fs_visitor *v) 485{ 486 hash_table_call_foreach(v->variable_ht, 487 import_uniforms_callback, 488 variable_ht); 489 this->params_remap = v->params_remap; 490} 491 492/* Our support for uniforms is piggy-backed on the struct 493 * gl_fragment_program, because that's where the values actually 494 * get stored, rather than in some global gl_shader_program uniform 495 * store. 496 */ 497int 498fs_visitor::setup_uniform_values(int loc, const glsl_type *type) 499{ 500 unsigned int offset = 0; 501 502 if (type->is_matrix()) { 503 const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT, 504 type->vector_elements, 505 1); 506 507 for (unsigned int i = 0; i < type->matrix_columns; i++) { 508 offset += setup_uniform_values(loc + offset, column); 509 } 510 511 return offset; 512 } 513 514 switch (type->base_type) { 515 case GLSL_TYPE_FLOAT: 516 case GLSL_TYPE_UINT: 517 case GLSL_TYPE_INT: 518 case GLSL_TYPE_BOOL: 519 for (unsigned int i = 0; i < type->vector_elements; i++) { 520 unsigned int param = c->prog_data.nr_params++; 521 522 assert(param < ARRAY_SIZE(c->prog_data.param)); 523 524 if (ctx->Const.NativeIntegers) { 525 c->prog_data.param_convert[param] = PARAM_NO_CONVERT; 526 } else { 527 switch (type->base_type) { 528 case GLSL_TYPE_FLOAT: 529 c->prog_data.param_convert[param] = PARAM_NO_CONVERT; 530 break; 531 case GLSL_TYPE_UINT: 532 c->prog_data.param_convert[param] = PARAM_CONVERT_F2U; 533 break; 534 case GLSL_TYPE_INT: 535 c->prog_data.param_convert[param] = PARAM_CONVERT_F2I; 536 break; 537 case GLSL_TYPE_BOOL: 538 c->prog_data.param_convert[param] = PARAM_CONVERT_F2B; 539 break; 540 default: 541 assert(!"not reached"); 542 c->prog_data.param_convert[param] = PARAM_NO_CONVERT; 543 break; 544 } 545 } 546 this->param_index[param] = loc; 547 this->param_offset[param] = i; 548 } 549 return 1; 550 551 case GLSL_TYPE_STRUCT: 552 for (unsigned int i = 0; i < type->length; i++) { 553 offset += setup_uniform_values(loc + offset, 554 type->fields.structure[i].type); 555 } 556 return offset; 557 558 case GLSL_TYPE_ARRAY: 559 for (unsigned int i = 0; i < type->length; i++) { 560 offset += setup_uniform_values(loc + offset, type->fields.array); 561 } 562 return offset; 563 564 case GLSL_TYPE_SAMPLER: 565 /* The sampler takes up a slot, but we don't use any values from it. */ 566 return 1; 567 568 default: 569 assert(!"not reached"); 570 return 0; 571 } 572} 573 574 575/* Our support for builtin uniforms is even scarier than non-builtin. 576 * It sits on top of the PROG_STATE_VAR parameters that are 577 * automatically updated from GL context state. 578 */ 579void 580fs_visitor::setup_builtin_uniform_values(ir_variable *ir) 581{ 582 const ir_state_slot *const slots = ir->state_slots; 583 assert(ir->state_slots != NULL); 584 585 for (unsigned int i = 0; i < ir->num_state_slots; i++) { 586 /* This state reference has already been setup by ir_to_mesa, but we'll 587 * get the same index back here. 588 */ 589 int index = _mesa_add_state_reference(this->fp->Base.Parameters, 590 (gl_state_index *)slots[i].tokens); 591 592 /* Add each of the unique swizzles of the element as a parameter. 593 * This'll end up matching the expected layout of the 594 * array/matrix/structure we're trying to fill in. 595 */ 596 int last_swiz = -1; 597 for (unsigned int j = 0; j < 4; j++) { 598 int swiz = GET_SWZ(slots[i].swizzle, j); 599 if (swiz == last_swiz) 600 break; 601 last_swiz = swiz; 602 603 c->prog_data.param_convert[c->prog_data.nr_params] = 604 PARAM_NO_CONVERT; 605 this->param_index[c->prog_data.nr_params] = index; 606 this->param_offset[c->prog_data.nr_params] = swiz; 607 c->prog_data.nr_params++; 608 } 609 } 610} 611 612fs_reg * 613fs_visitor::emit_fragcoord_interpolation(ir_variable *ir) 614{ 615 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); 616 fs_reg wpos = *reg; 617 bool flip = !ir->origin_upper_left ^ c->key.render_to_fbo; 618 619 /* gl_FragCoord.x */ 620 if (ir->pixel_center_integer) { 621 emit(BRW_OPCODE_MOV, wpos, this->pixel_x); 622 } else { 623 emit(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f)); 624 } 625 wpos.reg_offset++; 626 627 /* gl_FragCoord.y */ 628 if (!flip && ir->pixel_center_integer) { 629 emit(BRW_OPCODE_MOV, wpos, this->pixel_y); 630 } else { 631 fs_reg pixel_y = this->pixel_y; 632 float offset = (ir->pixel_center_integer ? 0.0 : 0.5); 633 634 if (flip) { 635 pixel_y.negate = true; 636 offset += c->key.drawable_height - 1.0; 637 } 638 639 emit(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset)); 640 } 641 wpos.reg_offset++; 642 643 /* gl_FragCoord.z */ 644 if (intel->gen >= 6) { 645 emit(BRW_OPCODE_MOV, wpos, 646 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); 647 } else { 648 emit(FS_OPCODE_LINTERP, wpos, 649 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 650 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 651 interp_reg(FRAG_ATTRIB_WPOS, 2)); 652 } 653 wpos.reg_offset++; 654 655 /* gl_FragCoord.w: Already set up in emit_interpolation */ 656 emit(BRW_OPCODE_MOV, wpos, this->wpos_w); 657 658 return reg; 659} 660 661fs_inst * 662fs_visitor::emit_linterp(const fs_reg &attr, const fs_reg &interp, 663 glsl_interp_qualifier interpolation_mode, 664 bool is_centroid) 665{ 666 brw_wm_barycentric_interp_mode barycoord_mode; 667 if (is_centroid) { 668 if (interpolation_mode == INTERP_QUALIFIER_SMOOTH) 669 barycoord_mode = BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC; 670 else 671 barycoord_mode = BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC; 672 } else { 673 if (interpolation_mode == INTERP_QUALIFIER_SMOOTH) 674 barycoord_mode = BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC; 675 else 676 barycoord_mode = BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC; 677 } 678 return emit(FS_OPCODE_LINTERP, attr, 679 this->delta_x[barycoord_mode], 680 this->delta_y[barycoord_mode], interp); 681} 682 683fs_reg * 684fs_visitor::emit_general_interpolation(ir_variable *ir) 685{ 686 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); 687 reg->type = brw_type_for_base_type(ir->type->get_scalar_type()); 688 fs_reg attr = *reg; 689 690 unsigned int array_elements; 691 const glsl_type *type; 692 693 if (ir->type->is_array()) { 694 array_elements = ir->type->length; 695 if (array_elements == 0) { 696 fail("dereferenced array '%s' has length 0\n", ir->name); 697 } 698 type = ir->type->fields.array; 699 } else { 700 array_elements = 1; 701 type = ir->type; 702 } 703 704 glsl_interp_qualifier interpolation_mode = 705 ir->determine_interpolation_mode(c->key.flat_shade); 706 707 int location = ir->location; 708 for (unsigned int i = 0; i < array_elements; i++) { 709 for (unsigned int j = 0; j < type->matrix_columns; j++) { 710 if (urb_setup[location] == -1) { 711 /* If there's no incoming setup data for this slot, don't 712 * emit interpolation for it. 713 */ 714 attr.reg_offset += type->vector_elements; 715 location++; 716 continue; 717 } 718 719 if (interpolation_mode == INTERP_QUALIFIER_FLAT) { 720 /* Constant interpolation (flat shading) case. The SF has 721 * handed us defined values in only the constant offset 722 * field of the setup reg. 723 */ 724 for (unsigned int k = 0; k < type->vector_elements; k++) { 725 struct brw_reg interp = interp_reg(location, k); 726 interp = suboffset(interp, 3); 727 interp.type = reg->type; 728 emit(FS_OPCODE_CINTERP, attr, fs_reg(interp)); 729 attr.reg_offset++; 730 } 731 } else { 732 /* Smooth/noperspective interpolation case. */ 733 for (unsigned int k = 0; k < type->vector_elements; k++) { 734 /* FINISHME: At some point we probably want to push 735 * this farther by giving similar treatment to the 736 * other potentially constant components of the 737 * attribute, as well as making brw_vs_constval.c 738 * handle varyings other than gl_TexCoord. 739 */ 740 if (location >= FRAG_ATTRIB_TEX0 && 741 location <= FRAG_ATTRIB_TEX7 && 742 k == 3 && !(c->key.proj_attrib_mask & (1 << location))) { 743 emit(BRW_OPCODE_MOV, attr, fs_reg(1.0f)); 744 } else { 745 struct brw_reg interp = interp_reg(location, k); 746 emit_linterp(attr, fs_reg(interp), interpolation_mode, 747 ir->centroid); 748 if (brw->needs_unlit_centroid_workaround && ir->centroid) { 749 /* Get the pixel/sample mask into f0 so that we know 750 * which pixels are lit. Then, for each channel that is 751 * unlit, replace the centroid data with non-centroid 752 * data. 753 */ 754 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS, attr); 755 fs_inst *inst = emit_linterp(attr, fs_reg(interp), 756 interpolation_mode, false); 757 inst->predicated = true; 758 inst->predicate_inverse = true; 759 } 760 if (intel->gen < 6) { 761 emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w); 762 } 763 } 764 attr.reg_offset++; 765 } 766 767 } 768 location++; 769 } 770 } 771 772 return reg; 773} 774 775fs_reg * 776fs_visitor::emit_frontfacing_interpolation(ir_variable *ir) 777{ 778 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); 779 780 /* The frontfacing comes in as a bit in the thread payload. */ 781 if (intel->gen >= 6) { 782 emit(BRW_OPCODE_ASR, *reg, 783 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)), 784 fs_reg(15)); 785 emit(BRW_OPCODE_NOT, *reg, *reg); 786 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1)); 787 } else { 788 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); 789 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives 790 * us front face 791 */ 792 fs_inst *inst = emit(BRW_OPCODE_CMP, *reg, 793 fs_reg(r1_6ud), 794 fs_reg(1u << 31)); 795 inst->conditional_mod = BRW_CONDITIONAL_L; 796 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u)); 797 } 798 799 return reg; 800} 801 802fs_inst * 803fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src) 804{ 805 switch (opcode) { 806 case SHADER_OPCODE_RCP: 807 case SHADER_OPCODE_RSQ: 808 case SHADER_OPCODE_SQRT: 809 case SHADER_OPCODE_EXP2: 810 case SHADER_OPCODE_LOG2: 811 case SHADER_OPCODE_SIN: 812 case SHADER_OPCODE_COS: 813 break; 814 default: 815 assert(!"not reached: bad math opcode"); 816 return NULL; 817 } 818 819 /* Can't do hstride == 0 args to gen6 math, so expand it out. We 820 * might be able to do better by doing execsize = 1 math and then 821 * expanding that result out, but we would need to be careful with 822 * masking. 823 * 824 * Gen 6 hardware ignores source modifiers (negate and abs) on math 825 * instructions, so we also move to a temp to set those up. 826 */ 827 if (intel->gen == 6 && (src.file == UNIFORM || 828 src.abs || 829 src.negate)) { 830 fs_reg expanded = fs_reg(this, glsl_type::float_type); 831 emit(BRW_OPCODE_MOV, expanded, src); 832 src = expanded; 833 } 834 835 fs_inst *inst = emit(opcode, dst, src); 836 837 if (intel->gen < 6) { 838 inst->base_mrf = 2; 839 inst->mlen = c->dispatch_width / 8; 840 } 841 842 return inst; 843} 844 845fs_inst * 846fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1) 847{ 848 int base_mrf = 2; 849 fs_inst *inst; 850 851 switch (opcode) { 852 case SHADER_OPCODE_POW: 853 case SHADER_OPCODE_INT_QUOTIENT: 854 case SHADER_OPCODE_INT_REMAINDER: 855 break; 856 default: 857 assert(!"not reached: unsupported binary math opcode."); 858 return NULL; 859 } 860 861 if (intel->gen >= 7) { 862 inst = emit(opcode, dst, src0, src1); 863 } else if (intel->gen == 6) { 864 /* Can't do hstride == 0 args to gen6 math, so expand it out. 865 * 866 * The hardware ignores source modifiers (negate and abs) on math 867 * instructions, so we also move to a temp to set those up. 868 */ 869 if (src0.file == UNIFORM || src0.abs || src0.negate) { 870 fs_reg expanded = fs_reg(this, glsl_type::float_type); 871 expanded.type = src0.type; 872 emit(BRW_OPCODE_MOV, expanded, src0); 873 src0 = expanded; 874 } 875 876 if (src1.file == UNIFORM || src1.abs || src1.negate) { 877 fs_reg expanded = fs_reg(this, glsl_type::float_type); 878 expanded.type = src1.type; 879 emit(BRW_OPCODE_MOV, expanded, src1); 880 src1 = expanded; 881 } 882 883 inst = emit(opcode, dst, src0, src1); 884 } else { 885 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13 886 * "Message Payload": 887 * 888 * "Operand0[7]. For the INT DIV functions, this operand is the 889 * denominator." 890 * ... 891 * "Operand1[7]. For the INT DIV functions, this operand is the 892 * numerator." 893 */ 894 bool is_int_div = opcode != SHADER_OPCODE_POW; 895 fs_reg &op0 = is_int_div ? src1 : src0; 896 fs_reg &op1 = is_int_div ? src0 : src1; 897 898 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1, op1.type), op1); 899 inst = emit(opcode, dst, op0, reg_null_f); 900 901 inst->base_mrf = base_mrf; 902 inst->mlen = 2 * c->dispatch_width / 8; 903 } 904 return inst; 905} 906 907/** 908 * To be called after the last _mesa_add_state_reference() call, to 909 * set up prog_data.param[] for assign_curb_setup() and 910 * setup_pull_constants(). 911 */ 912void 913fs_visitor::setup_paramvalues_refs() 914{ 915 if (c->dispatch_width != 8) 916 return; 917 918 /* Set up the pointers to ParamValues now that that array is finalized. */ 919 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) { 920 c->prog_data.param[i] = 921 (const float *)fp->Base.Parameters->ParameterValues[this->param_index[i]] + 922 this->param_offset[i]; 923 } 924} 925 926void 927fs_visitor::assign_curb_setup() 928{ 929 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8; 930 if (c->dispatch_width == 8) { 931 c->prog_data.first_curbe_grf = c->nr_payload_regs; 932 } else { 933 c->prog_data.first_curbe_grf_16 = c->nr_payload_regs; 934 } 935 936 /* Map the offsets in the UNIFORM file to fixed HW regs. */ 937 foreach_list(node, &this->instructions) { 938 fs_inst *inst = (fs_inst *)node; 939 940 for (unsigned int i = 0; i < 3; i++) { 941 if (inst->src[i].file == UNIFORM) { 942 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset; 943 struct brw_reg brw_reg = brw_vec1_grf(c->nr_payload_regs + 944 constant_nr / 8, 945 constant_nr % 8); 946 947 inst->src[i].file = FIXED_HW_REG; 948 inst->src[i].fixed_hw_reg = retype(brw_reg, inst->src[i].type); 949 } 950 } 951 } 952} 953 954void 955fs_visitor::calculate_urb_setup() 956{ 957 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) { 958 urb_setup[i] = -1; 959 } 960 961 int urb_next = 0; 962 /* Figure out where each of the incoming setup attributes lands. */ 963 if (intel->gen >= 6) { 964 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) { 965 if (fp->Base.InputsRead & BITFIELD64_BIT(i)) { 966 urb_setup[i] = urb_next++; 967 } 968 } 969 } else { 970 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */ 971 for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) { 972 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) { 973 int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i); 974 975 if (fp_index >= 0) 976 urb_setup[fp_index] = urb_next++; 977 } 978 } 979 980 /* 981 * It's a FS only attribute, and we did interpolation for this attribute 982 * in SF thread. So, count it here, too. 983 * 984 * See compile_sf_prog() for more info. 985 */ 986 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(FRAG_ATTRIB_PNTC)) 987 urb_setup[FRAG_ATTRIB_PNTC] = urb_next++; 988 } 989 990 /* Each attribute is 4 setup channels, each of which is half a reg. */ 991 c->prog_data.urb_read_length = urb_next * 2; 992} 993 994void 995fs_visitor::assign_urb_setup() 996{ 997 int urb_start = c->nr_payload_regs + c->prog_data.curb_read_length; 998 999 /* Offset all the urb_setup[] index by the actual position of the 1000 * setup regs, now that the location of the constants has been chosen. 1001 */ 1002 foreach_list(node, &this->instructions) { 1003 fs_inst *inst = (fs_inst *)node; 1004 1005 if (inst->opcode == FS_OPCODE_LINTERP) { 1006 assert(inst->src[2].file == FIXED_HW_REG); 1007 inst->src[2].fixed_hw_reg.nr += urb_start; 1008 } 1009 1010 if (inst->opcode == FS_OPCODE_CINTERP) { 1011 assert(inst->src[0].file == FIXED_HW_REG); 1012 inst->src[0].fixed_hw_reg.nr += urb_start; 1013 } 1014 } 1015 1016 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length; 1017} 1018 1019/** 1020 * Split large virtual GRFs into separate components if we can. 1021 * 1022 * This is mostly duplicated with what brw_fs_vector_splitting does, 1023 * but that's really conservative because it's afraid of doing 1024 * splitting that doesn't result in real progress after the rest of 1025 * the optimization phases, which would cause infinite looping in 1026 * optimization. We can do it once here, safely. This also has the 1027 * opportunity to split interpolated values, or maybe even uniforms, 1028 * which we don't have at the IR level. 1029 * 1030 * We want to split, because virtual GRFs are what we register 1031 * allocate and spill (due to contiguousness requirements for some 1032 * instructions), and they're what we naturally generate in the 1033 * codegen process, but most virtual GRFs don't actually need to be 1034 * contiguous sets of GRFs. If we split, we'll end up with reduced 1035 * live intervals and better dead code elimination and coalescing. 1036 */ 1037void 1038fs_visitor::split_virtual_grfs() 1039{ 1040 int num_vars = this->virtual_grf_next; 1041 bool split_grf[num_vars]; 1042 int new_virtual_grf[num_vars]; 1043 1044 /* Try to split anything > 0 sized. */ 1045 for (int i = 0; i < num_vars; i++) { 1046 if (this->virtual_grf_sizes[i] != 1) 1047 split_grf[i] = true; 1048 else 1049 split_grf[i] = false; 1050 } 1051 1052 if (brw->has_pln && 1053 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == GRF) { 1054 /* PLN opcodes rely on the delta_xy being contiguous. We only have to 1055 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to 1056 * Gen6, that was the only supported interpolation mode, and since Gen6, 1057 * delta_x and delta_y are in fixed hardware registers. 1058 */ 1059 split_grf[this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg] = 1060 false; 1061 } 1062 1063 foreach_list(node, &this->instructions) { 1064 fs_inst *inst = (fs_inst *)node; 1065 1066 /* Texturing produces 4 contiguous registers, so no splitting. */ 1067 if (inst->is_tex()) { 1068 split_grf[inst->dst.reg] = false; 1069 } 1070 } 1071 1072 /* Allocate new space for split regs. Note that the virtual 1073 * numbers will be contiguous. 1074 */ 1075 for (int i = 0; i < num_vars; i++) { 1076 if (split_grf[i]) { 1077 new_virtual_grf[i] = virtual_grf_alloc(1); 1078 for (int j = 2; j < this->virtual_grf_sizes[i]; j++) { 1079 int reg = virtual_grf_alloc(1); 1080 assert(reg == new_virtual_grf[i] + j - 1); 1081 (void) reg; 1082 } 1083 this->virtual_grf_sizes[i] = 1; 1084 } 1085 } 1086 1087 foreach_list(node, &this->instructions) { 1088 fs_inst *inst = (fs_inst *)node; 1089 1090 if (inst->dst.file == GRF && 1091 split_grf[inst->dst.reg] && 1092 inst->dst.reg_offset != 0) { 1093 inst->dst.reg = (new_virtual_grf[inst->dst.reg] + 1094 inst->dst.reg_offset - 1); 1095 inst->dst.reg_offset = 0; 1096 } 1097 for (int i = 0; i < 3; i++) { 1098 if (inst->src[i].file == GRF && 1099 split_grf[inst->src[i].reg] && 1100 inst->src[i].reg_offset != 0) { 1101 inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] + 1102 inst->src[i].reg_offset - 1); 1103 inst->src[i].reg_offset = 0; 1104 } 1105 } 1106 } 1107 this->live_intervals_valid = false; 1108} 1109 1110bool 1111fs_visitor::remove_dead_constants() 1112{ 1113 if (c->dispatch_width == 8) { 1114 this->params_remap = ralloc_array(mem_ctx, int, c->prog_data.nr_params); 1115 1116 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) 1117 this->params_remap[i] = -1; 1118 1119 /* Find which params are still in use. */ 1120 foreach_list(node, &this->instructions) { 1121 fs_inst *inst = (fs_inst *)node; 1122 1123 for (int i = 0; i < 3; i++) { 1124 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset; 1125 1126 if (inst->src[i].file != UNIFORM) 1127 continue; 1128 1129 assert(constant_nr < (int)c->prog_data.nr_params); 1130 1131 /* For now, set this to non-negative. We'll give it the 1132 * actual new number in a moment, in order to keep the 1133 * register numbers nicely ordered. 1134 */ 1135 this->params_remap[constant_nr] = 0; 1136 } 1137 } 1138 1139 /* Figure out what the new numbers for the params will be. At some 1140 * point when we're doing uniform array access, we're going to want 1141 * to keep the distinction between .reg and .reg_offset, but for 1142 * now we don't care. 1143 */ 1144 unsigned int new_nr_params = 0; 1145 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) { 1146 if (this->params_remap[i] != -1) { 1147 this->params_remap[i] = new_nr_params++; 1148 } 1149 } 1150 1151 /* Update the list of params to be uploaded to match our new numbering. */ 1152 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) { 1153 int remapped = this->params_remap[i]; 1154 1155 if (remapped == -1) 1156 continue; 1157 1158 /* We've already done setup_paramvalues_refs() so no need to worry 1159 * about param_index and param_offset. 1160 */ 1161 c->prog_data.param[remapped] = c->prog_data.param[i]; 1162 c->prog_data.param_convert[remapped] = c->prog_data.param_convert[i]; 1163 } 1164 1165 c->prog_data.nr_params = new_nr_params; 1166 } else { 1167 /* This should have been generated in the 8-wide pass already. */ 1168 assert(this->params_remap); 1169 } 1170 1171 /* Now do the renumbering of the shader to remove unused params. */ 1172 foreach_list(node, &this->instructions) { 1173 fs_inst *inst = (fs_inst *)node; 1174 1175 for (int i = 0; i < 3; i++) { 1176 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset; 1177 1178 if (inst->src[i].file != UNIFORM) 1179 continue; 1180 1181 assert(this->params_remap[constant_nr] != -1); 1182 inst->src[i].reg = this->params_remap[constant_nr]; 1183 inst->src[i].reg_offset = 0; 1184 } 1185 } 1186 1187 return true; 1188} 1189 1190/** 1191 * Choose accesses from the UNIFORM file to demote to using the pull 1192 * constant buffer. 1193 * 1194 * We allow a fragment shader to have more than the specified minimum 1195 * maximum number of fragment shader uniform components (64). If 1196 * there are too many of these, they'd fill up all of register space. 1197 * So, this will push some of them out to the pull constant buffer and 1198 * update the program to load them. 1199 */ 1200void 1201fs_visitor::setup_pull_constants() 1202{ 1203 /* Only allow 16 registers (128 uniform components) as push constants. */ 1204 unsigned int max_uniform_components = 16 * 8; 1205 if (c->prog_data.nr_params <= max_uniform_components) 1206 return; 1207 1208 if (c->dispatch_width == 16) { 1209 fail("Pull constants not supported in 16-wide\n"); 1210 return; 1211 } 1212 1213 /* Just demote the end of the list. We could probably do better 1214 * here, demoting things that are rarely used in the program first. 1215 */ 1216 int pull_uniform_base = max_uniform_components; 1217 int pull_uniform_count = c->prog_data.nr_params - pull_uniform_base; 1218 1219 foreach_list(node, &this->instructions) { 1220 fs_inst *inst = (fs_inst *)node; 1221 1222 for (int i = 0; i < 3; i++) { 1223 if (inst->src[i].file != UNIFORM) 1224 continue; 1225 1226 int uniform_nr = inst->src[i].reg + inst->src[i].reg_offset; 1227 if (uniform_nr < pull_uniform_base) 1228 continue; 1229 1230 fs_reg dst = fs_reg(this, glsl_type::float_type); 1231 fs_inst *pull = new(mem_ctx) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD, 1232 dst); 1233 pull->offset = ((uniform_nr - pull_uniform_base) * 4) & ~15; 1234 pull->ir = inst->ir; 1235 pull->annotation = inst->annotation; 1236 pull->base_mrf = 14; 1237 pull->mlen = 1; 1238 1239 inst->insert_before(pull); 1240 1241 inst->src[i].file = GRF; 1242 inst->src[i].reg = dst.reg; 1243 inst->src[i].reg_offset = 0; 1244 inst->src[i].smear = (uniform_nr - pull_uniform_base) & 3; 1245 } 1246 } 1247 1248 for (int i = 0; i < pull_uniform_count; i++) { 1249 c->prog_data.pull_param[i] = c->prog_data.param[pull_uniform_base + i]; 1250 c->prog_data.pull_param_convert[i] = 1251 c->prog_data.param_convert[pull_uniform_base + i]; 1252 } 1253 c->prog_data.nr_params -= pull_uniform_count; 1254 c->prog_data.nr_pull_params = pull_uniform_count; 1255} 1256 1257/** 1258 * Attempts to move immediate constants into the immediate 1259 * constant slot of following instructions. 1260 * 1261 * Immediate constants are a bit tricky -- they have to be in the last 1262 * operand slot, you can't do abs/negate on them, 1263 */ 1264 1265bool 1266fs_visitor::propagate_constants() 1267{ 1268 bool progress = false; 1269 1270 calculate_live_intervals(); 1271 1272 foreach_list(node, &this->instructions) { 1273 fs_inst *inst = (fs_inst *)node; 1274 1275 if (inst->opcode != BRW_OPCODE_MOV || 1276 inst->predicated || 1277 inst->dst.file != GRF || inst->src[0].file != IMM || 1278 inst->dst.type != inst->src[0].type || 1279 (c->dispatch_width == 16 && 1280 (inst->force_uncompressed || inst->force_sechalf))) 1281 continue; 1282 1283 /* Don't bother with cases where we should have had the 1284 * operation on the constant folded in GLSL already. 1285 */ 1286 if (inst->saturate) 1287 continue; 1288 1289 /* Found a move of a constant to a GRF. Find anything else using the GRF 1290 * before it's written, and replace it with the constant if we can. 1291 */ 1292 for (fs_inst *scan_inst = (fs_inst *)inst->next; 1293 !scan_inst->is_tail_sentinel(); 1294 scan_inst = (fs_inst *)scan_inst->next) { 1295 if (scan_inst->opcode == BRW_OPCODE_DO || 1296 scan_inst->opcode == BRW_OPCODE_WHILE || 1297 scan_inst->opcode == BRW_OPCODE_ELSE || 1298 scan_inst->opcode == BRW_OPCODE_ENDIF) { 1299 break; 1300 } 1301 1302 for (int i = 2; i >= 0; i--) { 1303 if (scan_inst->src[i].file != GRF || 1304 scan_inst->src[i].reg != inst->dst.reg || 1305 scan_inst->src[i].reg_offset != inst->dst.reg_offset) 1306 continue; 1307 1308 /* Don't bother with cases where we should have had the 1309 * operation on the constant folded in GLSL already. 1310 */ 1311 if (scan_inst->src[i].negate || scan_inst->src[i].abs) 1312 continue; 1313 1314 switch (scan_inst->opcode) { 1315 case BRW_OPCODE_MOV: 1316 scan_inst->src[i] = inst->src[0]; 1317 progress = true; 1318 break; 1319 1320 case BRW_OPCODE_MUL: 1321 case BRW_OPCODE_ADD: 1322 if (i == 1) { 1323 scan_inst->src[i] = inst->src[0]; 1324 progress = true; 1325 } else if (i == 0 && scan_inst->src[1].file != IMM) { 1326 /* Fit this constant in by commuting the operands. 1327 * Exception: we can't do this for 32-bit integer MUL 1328 * because it's asymmetric. 1329 */ 1330 if (scan_inst->opcode == BRW_OPCODE_MUL && 1331 (scan_inst->src[1].type == BRW_REGISTER_TYPE_D || 1332 scan_inst->src[1].type == BRW_REGISTER_TYPE_UD)) 1333 break; 1334 scan_inst->src[0] = scan_inst->src[1]; 1335 scan_inst->src[1] = inst->src[0]; 1336 progress = true; 1337 } 1338 break; 1339 1340 case BRW_OPCODE_CMP: 1341 case BRW_OPCODE_IF: 1342 if (i == 1) { 1343 scan_inst->src[i] = inst->src[0]; 1344 progress = true; 1345 } else if (i == 0 && scan_inst->src[1].file != IMM) { 1346 uint32_t new_cmod; 1347 1348 new_cmod = brw_swap_cmod(scan_inst->conditional_mod); 1349 if (new_cmod != ~0u) { 1350 /* Fit this constant in by swapping the operands and 1351 * flipping the test 1352 */ 1353 scan_inst->src[0] = scan_inst->src[1]; 1354 scan_inst->src[1] = inst->src[0]; 1355 scan_inst->conditional_mod = new_cmod; 1356 progress = true; 1357 } 1358 } 1359 break; 1360 1361 case BRW_OPCODE_SEL: 1362 if (i == 1) { 1363 scan_inst->src[i] = inst->src[0]; 1364 progress = true; 1365 } else if (i == 0 && scan_inst->src[1].file != IMM) { 1366 scan_inst->src[0] = scan_inst->src[1]; 1367 scan_inst->src[1] = inst->src[0]; 1368 1369 /* If this was predicated, flipping operands means 1370 * we also need to flip the predicate. 1371 */ 1372 if (scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) { 1373 scan_inst->predicate_inverse = 1374 !scan_inst->predicate_inverse; 1375 } 1376 progress = true; 1377 } 1378 break; 1379 1380 case SHADER_OPCODE_RCP: 1381 /* The hardware doesn't do math on immediate values 1382 * (because why are you doing that, seriously?), but 1383 * the correct answer is to just constant fold it 1384 * anyway. 1385 */ 1386 assert(i == 0); 1387 if (inst->src[0].imm.f != 0.0f) { 1388 scan_inst->opcode = BRW_OPCODE_MOV; 1389 scan_inst->src[0] = inst->src[0]; 1390 scan_inst->src[0].imm.f = 1.0f / scan_inst->src[0].imm.f; 1391 progress = true; 1392 } 1393 break; 1394 1395 default: 1396 break; 1397 } 1398 } 1399 1400 if (scan_inst->dst.file == GRF && 1401 scan_inst->dst.reg == inst->dst.reg && 1402 (scan_inst->dst.reg_offset == inst->dst.reg_offset || 1403 scan_inst->is_tex())) { 1404 break; 1405 } 1406 } 1407 } 1408 1409 if (progress) 1410 this->live_intervals_valid = false; 1411 1412 return progress; 1413} 1414 1415 1416/** 1417 * Attempts to move immediate constants into the immediate 1418 * constant slot of following instructions. 1419 * 1420 * Immediate constants are a bit tricky -- they have to be in the last 1421 * operand slot, you can't do abs/negate on them, 1422 */ 1423 1424bool 1425fs_visitor::opt_algebraic() 1426{ 1427 bool progress = false; 1428 1429 calculate_live_intervals(); 1430 1431 foreach_list(node, &this->instructions) { 1432 fs_inst *inst = (fs_inst *)node; 1433 1434 switch (inst->opcode) { 1435 case BRW_OPCODE_MUL: 1436 if (inst->src[1].file != IMM) 1437 continue; 1438 1439 /* a * 1.0 = a */ 1440 if (inst->src[1].type == BRW_REGISTER_TYPE_F && 1441 inst->src[1].imm.f == 1.0) { 1442 inst->opcode = BRW_OPCODE_MOV; 1443 inst->src[1] = reg_undef; 1444 progress = true; 1445 break; 1446 } 1447 1448 break; 1449 default: 1450 break; 1451 } 1452 } 1453 1454 return progress; 1455} 1456 1457/** 1458 * Must be called after calculate_live_intervales() to remove unused 1459 * writes to registers -- register allocation will fail otherwise 1460 * because something deffed but not used won't be considered to 1461 * interfere with other regs. 1462 */ 1463bool 1464fs_visitor::dead_code_eliminate() 1465{ 1466 bool progress = false; 1467 int pc = 0; 1468 1469 calculate_live_intervals(); 1470 1471 foreach_list_safe(node, &this->instructions) { 1472 fs_inst *inst = (fs_inst *)node; 1473 1474 if (inst->dst.file == GRF && this->virtual_grf_use[inst->dst.reg] <= pc) { 1475 inst->remove(); 1476 progress = true; 1477 } 1478 1479 pc++; 1480 } 1481 1482 if (progress) 1483 live_intervals_valid = false; 1484 1485 return progress; 1486} 1487 1488/** 1489 * Implements a second type of register coalescing: This one checks if 1490 * the two regs involved in a raw move don't interfere, in which case 1491 * they can both by stored in the same place and the MOV removed. 1492 */ 1493bool 1494fs_visitor::register_coalesce_2() 1495{ 1496 bool progress = false; 1497 1498 calculate_live_intervals(); 1499 1500 foreach_list_safe(node, &this->instructions) { 1501 fs_inst *inst = (fs_inst *)node; 1502 1503 if (inst->opcode != BRW_OPCODE_MOV || 1504 inst->predicated || 1505 inst->saturate || 1506 inst->src[0].file != GRF || 1507 inst->src[0].negate || 1508 inst->src[0].abs || 1509 inst->src[0].smear != -1 || 1510 inst->dst.file != GRF || 1511 inst->dst.type != inst->src[0].type || 1512 virtual_grf_sizes[inst->src[0].reg] != 1 || 1513 virtual_grf_interferes(inst->dst.reg, inst->src[0].reg)) { 1514 continue; 1515 } 1516 1517 int reg_from = inst->src[0].reg; 1518 assert(inst->src[0].reg_offset == 0); 1519 int reg_to = inst->dst.reg; 1520 int reg_to_offset = inst->dst.reg_offset; 1521 1522 foreach_list_safe(node, &this->instructions) { 1523 fs_inst *scan_inst = (fs_inst *)node; 1524 1525 if (scan_inst->dst.file == GRF && 1526 scan_inst->dst.reg == reg_from) { 1527 scan_inst->dst.reg = reg_to; 1528 scan_inst->dst.reg_offset = reg_to_offset; 1529 } 1530 for (int i = 0; i < 3; i++) { 1531 if (scan_inst->src[i].file == GRF && 1532 scan_inst->src[i].reg == reg_from) { 1533 scan_inst->src[i].reg = reg_to; 1534 scan_inst->src[i].reg_offset = reg_to_offset; 1535 } 1536 } 1537 } 1538 1539 inst->remove(); 1540 live_intervals_valid = false; 1541 progress = true; 1542 continue; 1543 } 1544 1545 return progress; 1546} 1547 1548bool 1549fs_visitor::register_coalesce() 1550{ 1551 bool progress = false; 1552 int if_depth = 0; 1553 int loop_depth = 0; 1554 1555 foreach_list_safe(node, &this->instructions) { 1556 fs_inst *inst = (fs_inst *)node; 1557 1558 /* Make sure that we dominate the instructions we're going to 1559 * scan for interfering with our coalescing, or we won't have 1560 * scanned enough to see if anything interferes with our 1561 * coalescing. We don't dominate the following instructions if 1562 * we're in a loop or an if block. 1563 */ 1564 switch (inst->opcode) { 1565 case BRW_OPCODE_DO: 1566 loop_depth++; 1567 break; 1568 case BRW_OPCODE_WHILE: 1569 loop_depth--; 1570 break; 1571 case BRW_OPCODE_IF: 1572 if_depth++; 1573 break; 1574 case BRW_OPCODE_ENDIF: 1575 if_depth--; 1576 break; 1577 default: 1578 break; 1579 } 1580 if (loop_depth || if_depth) 1581 continue; 1582 1583 if (inst->opcode != BRW_OPCODE_MOV || 1584 inst->predicated || 1585 inst->saturate || 1586 inst->dst.file != GRF || (inst->src[0].file != GRF && 1587 inst->src[0].file != UNIFORM)|| 1588 inst->dst.type != inst->src[0].type) 1589 continue; 1590 1591 bool has_source_modifiers = inst->src[0].abs || inst->src[0].negate; 1592 1593 /* Found a move of a GRF to a GRF. Let's see if we can coalesce 1594 * them: check for no writes to either one until the exit of the 1595 * program. 1596 */ 1597 bool interfered = false; 1598 1599 for (fs_inst *scan_inst = (fs_inst *)inst->next; 1600 !scan_inst->is_tail_sentinel(); 1601 scan_inst = (fs_inst *)scan_inst->next) { 1602 if (scan_inst->dst.file == GRF) { 1603 if (scan_inst->dst.reg == inst->dst.reg && 1604 (scan_inst->dst.reg_offset == inst->dst.reg_offset || 1605 scan_inst->is_tex())) { 1606 interfered = true; 1607 break; 1608 } 1609 if (inst->src[0].file == GRF && 1610 scan_inst->dst.reg == inst->src[0].reg && 1611 (scan_inst->dst.reg_offset == inst->src[0].reg_offset || 1612 scan_inst->is_tex())) { 1613 interfered = true; 1614 break; 1615 } 1616 } 1617 1618 /* The gen6 MATH instruction can't handle source modifiers or 1619 * unusual register regions, so avoid coalescing those for 1620 * now. We should do something more specific. 1621 */ 1622 if (intel->gen >= 6 && 1623 scan_inst->is_math() && 1624 (has_source_modifiers || inst->src[0].file == UNIFORM)) { 1625 interfered = true; 1626 break; 1627 } 1628 1629 /* The accumulator result appears to get used for the 1630 * conditional modifier generation. When negating a UD 1631 * value, there is a 33rd bit generated for the sign in the 1632 * accumulator value, so now you can't check, for example, 1633 * equality with a 32-bit value. See piglit fs-op-neg-uint. 1634 */ 1635 if (scan_inst->conditional_mod && 1636 inst->src[0].negate && 1637 inst->src[0].type == BRW_REGISTER_TYPE_UD) { 1638 interfered = true; 1639 break; 1640 } 1641 } 1642 if (interfered) { 1643 continue; 1644 } 1645 1646 /* Rewrite the later usage to point at the source of the move to 1647 * be removed. 1648 */ 1649 for (fs_inst *scan_inst = inst; 1650 !scan_inst->is_tail_sentinel(); 1651 scan_inst = (fs_inst *)scan_inst->next) { 1652 for (int i = 0; i < 3; i++) { 1653 if (scan_inst->src[i].file == GRF && 1654 scan_inst->src[i].reg == inst->dst.reg && 1655 scan_inst->src[i].reg_offset == inst->dst.reg_offset) { 1656 fs_reg new_src = inst->src[0]; 1657 if (scan_inst->src[i].abs) { 1658 new_src.negate = 0; 1659 new_src.abs = 1; 1660 } 1661 new_src.negate ^= scan_inst->src[i].negate; 1662 scan_inst->src[i] = new_src; 1663 } 1664 } 1665 } 1666 1667 inst->remove(); 1668 progress = true; 1669 } 1670 1671 if (progress) 1672 live_intervals_valid = false; 1673 1674 return progress; 1675} 1676 1677 1678bool 1679fs_visitor::compute_to_mrf() 1680{ 1681 bool progress = false; 1682 int next_ip = 0; 1683 1684 calculate_live_intervals(); 1685 1686 foreach_list_safe(node, &this->instructions) { 1687 fs_inst *inst = (fs_inst *)node; 1688 1689 int ip = next_ip; 1690 next_ip++; 1691 1692 if (inst->opcode != BRW_OPCODE_MOV || 1693 inst->predicated || 1694 inst->dst.file != MRF || inst->src[0].file != GRF || 1695 inst->dst.type != inst->src[0].type || 1696 inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1) 1697 continue; 1698 1699 /* Work out which hardware MRF registers are written by this 1700 * instruction. 1701 */ 1702 int mrf_low = inst->dst.reg & ~BRW_MRF_COMPR4; 1703 int mrf_high; 1704 if (inst->dst.reg & BRW_MRF_COMPR4) { 1705 mrf_high = mrf_low + 4; 1706 } else if (c->dispatch_width == 16 && 1707 (!inst->force_uncompressed && !inst->force_sechalf)) { 1708 mrf_high = mrf_low + 1; 1709 } else { 1710 mrf_high = mrf_low; 1711 } 1712 1713 /* Can't compute-to-MRF this GRF if someone else was going to 1714 * read it later. 1715 */ 1716 if (this->virtual_grf_use[inst->src[0].reg] > ip) 1717 continue; 1718 1719 /* Found a move of a GRF to a MRF. Let's see if we can go 1720 * rewrite the thing that made this GRF to write into the MRF. 1721 */ 1722 fs_inst *scan_inst; 1723 for (scan_inst = (fs_inst *)inst->prev; 1724 scan_inst->prev != NULL; 1725 scan_inst = (fs_inst *)scan_inst->prev) { 1726 if (scan_inst->dst.file == GRF && 1727 scan_inst->dst.reg == inst->src[0].reg) { 1728 /* Found the last thing to write our reg we want to turn 1729 * into a compute-to-MRF. 1730 */ 1731 1732 if (scan_inst->is_tex()) { 1733 /* texturing writes several continuous regs, so we can't 1734 * compute-to-mrf that. 1735 */ 1736 break; 1737 } 1738 1739 /* If it's predicated, it (probably) didn't populate all 1740 * the channels. We might be able to rewrite everything 1741 * that writes that reg, but it would require smarter 1742 * tracking to delay the rewriting until complete success. 1743 */ 1744 if (scan_inst->predicated) 1745 break; 1746 1747 /* If it's half of register setup and not the same half as 1748 * our MOV we're trying to remove, bail for now. 1749 */ 1750 if (scan_inst->force_uncompressed != inst->force_uncompressed || 1751 scan_inst->force_sechalf != inst->force_sechalf) { 1752 break; 1753 } 1754 1755 /* SEND instructions can't have MRF as a destination. */ 1756 if (scan_inst->mlen) 1757 break; 1758 1759 if (intel->gen >= 6) { 1760 /* gen6 math instructions must have the destination be 1761 * GRF, so no compute-to-MRF for them. 1762 */ 1763 if (scan_inst->is_math()) { 1764 break; 1765 } 1766 } 1767 1768 if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) { 1769 /* Found the creator of our MRF's source value. */ 1770 scan_inst->dst.file = MRF; 1771 scan_inst->dst.reg = inst->dst.reg; 1772 scan_inst->saturate |= inst->saturate; 1773 inst->remove(); 1774 progress = true; 1775 } 1776 break; 1777 } 1778 1779 /* We don't handle flow control here. Most computation of 1780 * values that end up in MRFs are shortly before the MRF 1781 * write anyway. 1782 */ 1783 if (scan_inst->opcode == BRW_OPCODE_DO || 1784 scan_inst->opcode == BRW_OPCODE_WHILE || 1785 scan_inst->opcode == BRW_OPCODE_ELSE || 1786 scan_inst->opcode == BRW_OPCODE_ENDIF) { 1787 break; 1788 } 1789 1790 /* You can't read from an MRF, so if someone else reads our 1791 * MRF's source GRF that we wanted to rewrite, that stops us. 1792 */ 1793 bool interfered = false; 1794 for (int i = 0; i < 3; i++) { 1795 if (scan_inst->src[i].file == GRF && 1796 scan_inst->src[i].reg == inst->src[0].reg && 1797 scan_inst->src[i].reg_offset == inst->src[0].reg_offset) { 1798 interfered = true; 1799 } 1800 } 1801 if (interfered) 1802 break; 1803 1804 if (scan_inst->dst.file == MRF) { 1805 /* If somebody else writes our MRF here, we can't 1806 * compute-to-MRF before that. 1807 */ 1808 int scan_mrf_low = scan_inst->dst.reg & ~BRW_MRF_COMPR4; 1809 int scan_mrf_high; 1810 1811 if (scan_inst->dst.reg & BRW_MRF_COMPR4) { 1812 scan_mrf_high = scan_mrf_low + 4; 1813 } else if (c->dispatch_width == 16 && 1814 (!scan_inst->force_uncompressed && 1815 !scan_inst->force_sechalf)) { 1816 scan_mrf_high = scan_mrf_low + 1; 1817 } else { 1818 scan_mrf_high = scan_mrf_low; 1819 } 1820 1821 if (mrf_low == scan_mrf_low || 1822 mrf_low == scan_mrf_high || 1823 mrf_high == scan_mrf_low || 1824 mrf_high == scan_mrf_high) { 1825 break; 1826 } 1827 } 1828 1829 if (scan_inst->mlen > 0) { 1830 /* Found a SEND instruction, which means that there are 1831 * live values in MRFs from base_mrf to base_mrf + 1832 * scan_inst->mlen - 1. Don't go pushing our MRF write up 1833 * above it. 1834 */ 1835 if (mrf_low >= scan_inst->base_mrf && 1836 mrf_low < scan_inst->base_mrf + scan_inst->mlen) { 1837 break; 1838 } 1839 if (mrf_high >= scan_inst->base_mrf && 1840 mrf_high < scan_inst->base_mrf + scan_inst->mlen) { 1841 break; 1842 } 1843 } 1844 } 1845 } 1846 1847 return progress; 1848} 1849 1850/** 1851 * Walks through basic blocks, looking for repeated MRF writes and 1852 * removing the later ones. 1853 */ 1854bool 1855fs_visitor::remove_duplicate_mrf_writes() 1856{ 1857 fs_inst *last_mrf_move[16]; 1858 bool progress = false; 1859 1860 /* Need to update the MRF tracking for compressed instructions. */ 1861 if (c->dispatch_width == 16) 1862 return false; 1863 1864 memset(last_mrf_move, 0, sizeof(last_mrf_move)); 1865 1866 foreach_list_safe(node, &this->instructions) { 1867 fs_inst *inst = (fs_inst *)node; 1868 1869 switch (inst->opcode) { 1870 case BRW_OPCODE_DO: 1871 case BRW_OPCODE_WHILE: 1872 case BRW_OPCODE_IF: 1873 case BRW_OPCODE_ELSE: 1874 case BRW_OPCODE_ENDIF: 1875 memset(last_mrf_move, 0, sizeof(last_mrf_move)); 1876 continue; 1877 default: 1878 break; 1879 } 1880 1881 if (inst->opcode == BRW_OPCODE_MOV && 1882 inst->dst.file == MRF) { 1883 fs_inst *prev_inst = last_mrf_move[inst->dst.reg]; 1884 if (prev_inst && inst->equals(prev_inst)) { 1885 inst->remove(); 1886 progress = true; 1887 continue; 1888 } 1889 } 1890 1891 /* Clear out the last-write records for MRFs that were overwritten. */ 1892 if (inst->dst.file == MRF) { 1893 last_mrf_move[inst->dst.reg] = NULL; 1894 } 1895 1896 if (inst->mlen > 0) { 1897 /* Found a SEND instruction, which will include two or fewer 1898 * implied MRF writes. We could do better here. 1899 */ 1900 for (int i = 0; i < implied_mrf_writes(inst); i++) { 1901 last_mrf_move[inst->base_mrf + i] = NULL; 1902 } 1903 } 1904 1905 /* Clear out any MRF move records whose sources got overwritten. */ 1906 if (inst->dst.file == GRF) { 1907 for (unsigned int i = 0; i < Elements(last_mrf_move); i++) { 1908 if (last_mrf_move[i] && 1909 last_mrf_move[i]->src[0].reg == inst->dst.reg) { 1910 last_mrf_move[i] = NULL; 1911 } 1912 } 1913 } 1914 1915 if (inst->opcode == BRW_OPCODE_MOV && 1916 inst->dst.file == MRF && 1917 inst->src[0].file == GRF && 1918 !inst->predicated) { 1919 last_mrf_move[inst->dst.reg] = inst; 1920 } 1921 } 1922 1923 return progress; 1924} 1925 1926/** 1927 * Possibly returns an instruction that set up @param reg. 1928 * 1929 * Sometimes we want to take the result of some expression/variable 1930 * dereference tree and rewrite the instruction generating the result 1931 * of the tree. When processing the tree, we know that the 1932 * instructions generated are all writing temporaries that are dead 1933 * outside of this tree. So, if we have some instructions that write 1934 * a temporary, we're free to point that temp write somewhere else. 1935 * 1936 * Note that this doesn't guarantee that the instruction generated 1937 * only reg -- it might be the size=4 destination of a texture instruction. 1938 */ 1939fs_inst * 1940fs_visitor::get_instruction_generating_reg(fs_inst *start, 1941 fs_inst *end, 1942 fs_reg reg) 1943{ 1944 if (end == start || 1945 end->predicated || 1946 end->force_uncompressed || 1947 end->force_sechalf || 1948 !reg.equals(end->dst)) { 1949 return NULL; 1950 } else { 1951 return end; 1952 } 1953} 1954 1955bool 1956fs_visitor::run() 1957{ 1958 uint32_t prog_offset_16 = 0; 1959 uint32_t orig_nr_params = c->prog_data.nr_params; 1960 1961 brw_wm_payload_setup(brw, c); 1962 1963 if (c->dispatch_width == 16) { 1964 /* align to 64 byte boundary. */ 1965 while ((c->func.nr_insn * sizeof(struct brw_instruction)) % 64) { 1966 brw_NOP(p); 1967 } 1968 1969 /* Save off the start of this 16-wide program in case we succeed. */ 1970 prog_offset_16 = c->func.nr_insn * sizeof(struct brw_instruction); 1971 1972 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); 1973 } 1974 1975 if (0) { 1976 emit_dummy_fs(); 1977 } else { 1978 calculate_urb_setup(); 1979 if (intel->gen < 6) 1980 emit_interpolation_setup_gen4(); 1981 else 1982 emit_interpolation_setup_gen6(); 1983 1984 /* Generate FS IR for main(). (the visitor only descends into 1985 * functions called "main"). 1986 */ 1987 foreach_list(node, &*shader->ir) { 1988 ir_instruction *ir = (ir_instruction *)node; 1989 base_ir = ir; 1990 this->result = reg_undef; 1991 ir->accept(this); 1992 } 1993 if (failed) 1994 return false; 1995 1996 emit_fb_writes(); 1997 1998 split_virtual_grfs(); 1999 2000 setup_paramvalues_refs(); 2001 setup_pull_constants(); 2002 2003 bool progress; 2004 do { 2005 progress = false; 2006 2007 progress = remove_duplicate_mrf_writes() || progress; 2008 2009 progress = propagate_constants() || progress; 2010 progress = opt_algebraic() || progress; 2011 progress = opt_cse() || progress; 2012 progress = opt_copy_propagate() || progress; 2013 progress = register_coalesce() || progress; 2014 progress = register_coalesce_2() || progress; 2015 progress = compute_to_mrf() || progress; 2016 progress = dead_code_eliminate() || progress; 2017 } while (progress); 2018 2019 remove_dead_constants(); 2020 2021 schedule_instructions(); 2022 2023 assign_curb_setup(); 2024 assign_urb_setup(); 2025 2026 if (0) { 2027 /* Debug of register spilling: Go spill everything. */ 2028 int virtual_grf_count = virtual_grf_next; 2029 for (int i = 0; i < virtual_grf_count; i++) { 2030 spill_reg(i); 2031 } 2032 } 2033 2034 if (0) 2035 assign_regs_trivial(); 2036 else { 2037 while (!assign_regs()) { 2038 if (failed) 2039 break; 2040 } 2041 } 2042 } 2043 assert(force_uncompressed_stack == 0); 2044 assert(force_sechalf_stack == 0); 2045 2046 if (failed) 2047 return false; 2048 2049 generate_code(); 2050 2051 if (c->dispatch_width == 8) { 2052 c->prog_data.reg_blocks = brw_register_blocks(grf_used); 2053 } else { 2054 c->prog_data.reg_blocks_16 = brw_register_blocks(grf_used); 2055 c->prog_data.prog_offset_16 = prog_offset_16; 2056 2057 /* Make sure we didn't try to sneak in an extra uniform */ 2058 assert(orig_nr_params == c->prog_data.nr_params); 2059 (void) orig_nr_params; 2060 } 2061 2062 return !failed; 2063} 2064 2065bool 2066brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c, 2067 struct gl_shader_program *prog) 2068{ 2069 struct intel_context *intel = &brw->intel; 2070 2071 if (!prog) 2072 return false; 2073 2074 struct brw_shader *shader = 2075 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT]; 2076 if (!shader) 2077 return false; 2078 2079 if (unlikely(INTEL_DEBUG & DEBUG_WM)) { 2080 printf("GLSL IR for native fragment shader %d:\n", prog->Name); 2081 _mesa_print_ir(shader->ir, NULL); 2082 printf("\n\n"); 2083 } 2084 2085 /* Now the main event: Visit the shader IR and generate our FS IR for it. 2086 */ 2087 c->dispatch_width = 8; 2088 2089 fs_visitor v(c, prog, shader); 2090 if (!v.run()) { 2091 prog->LinkStatus = false; 2092 ralloc_strcat(&prog->InfoLog, v.fail_msg); 2093 2094 _mesa_problem(NULL, "Failed to compile fragment shader: %s\n", 2095 v.fail_msg); 2096 2097 return false; 2098 } 2099 2100 if (intel->gen >= 5 && c->prog_data.nr_pull_params == 0) { 2101 c->dispatch_width = 16; 2102 fs_visitor v2(c, prog, shader); 2103 v2.import_uniforms(&v); 2104 v2.run(); 2105 } 2106 2107 c->prog_data.dispatch_width = 8; 2108 2109 return true; 2110} 2111 2112bool 2113brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog) 2114{ 2115 struct brw_context *brw = brw_context(ctx); 2116 struct brw_wm_prog_key key; 2117 2118 /* As a temporary measure we assume that all programs use dFdy() (and hence 2119 * need to be compiled differently depending on whether we're rendering to 2120 * an FBO). FIXME: set this bool correctly based on the contents of the 2121 * program. 2122 */ 2123 bool program_uses_dfdy = true; 2124 2125 if (!prog->_LinkedShaders[MESA_SHADER_FRAGMENT]) 2126 return true; 2127 2128 struct gl_fragment_program *fp = (struct gl_fragment_program *) 2129 prog->_LinkedShaders[MESA_SHADER_FRAGMENT]->Program; 2130 struct brw_fragment_program *bfp = brw_fragment_program(fp); 2131 2132 memset(&key, 0, sizeof(key)); 2133 2134 if (fp->UsesKill) 2135 key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT; 2136 2137 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) 2138 key.iz_lookup |= IZ_PS_COMPUTES_DEPTH_BIT; 2139 2140 /* Just assume depth testing. */ 2141 key.iz_lookup |= IZ_DEPTH_TEST_ENABLE_BIT; 2142 key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT; 2143 2144 key.vp_outputs_written |= BITFIELD64_BIT(FRAG_ATTRIB_WPOS); 2145 for (int i = 0; i < FRAG_ATTRIB_MAX; i++) { 2146 if (!(fp->Base.InputsRead & BITFIELD64_BIT(i))) 2147 continue; 2148 2149 key.proj_attrib_mask |= 1 << i; 2150 2151 int vp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i); 2152 2153 if (vp_index >= 0) 2154 key.vp_outputs_written |= BITFIELD64_BIT(vp_index); 2155 } 2156 2157 key.clamp_fragment_color = true; 2158 2159 for (int i = 0; i < BRW_MAX_TEX_UNIT; i++) { 2160 if (fp->Base.ShadowSamplers & (1 << i)) 2161 key.tex.compare_funcs[i] = GL_LESS; 2162 2163 /* FINISHME: depth compares might use (0,0,0,W) for example */ 2164 key.tex.swizzles[i] = SWIZZLE_XYZW; 2165 } 2166 2167 if (fp->Base.InputsRead & FRAG_BIT_WPOS) { 2168 key.drawable_height = ctx->DrawBuffer->Height; 2169 } 2170 2171 if ((fp->Base.InputsRead & FRAG_BIT_WPOS) || program_uses_dfdy) { 2172 key.render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer); 2173 } 2174 2175 key.nr_color_regions = 1; 2176 2177 key.program_string_id = bfp->id; 2178 2179 uint32_t old_prog_offset = brw->wm.prog_offset; 2180 struct brw_wm_prog_data *old_prog_data = brw->wm.prog_data; 2181 2182 bool success = do_wm_prog(brw, prog, bfp, &key); 2183 2184 brw->wm.prog_offset = old_prog_offset; 2185 brw->wm.prog_data = old_prog_data; 2186 2187 return success; 2188} 2189