cpu-arm.cc revision 3e5fa29ddb82551500b118e9bf37af3966277b70 
1// Copyright 2006-2009 the V8 project authors. All rights reserved.
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27
28// CPU specific code for arm independent of OS goes here.
29#ifdef __arm__
30#include <sys/syscall.h>  // for cache flushing.
31#endif
32
33#include "v8.h"
34
35#if defined(V8_TARGET_ARCH_ARM)
36
37#include "cpu.h"
38#include "macro-assembler.h"
39#include "simulator.h"  // for cache flushing.
40
41namespace v8 {
42namespace internal {
43
44void CPU::Setup() {
45  CpuFeatures::Probe();
46}
47
48
49void CPU::FlushICache(void* start, size_t size) {
50#if defined (USE_SIMULATOR)
51  // Not generating ARM instructions for C-code. This means that we are
52  // building an ARM emulator based target.  We should notify the simulator
53  // that the Icache was flushed.
54  // None of this code ends up in the snapshot so there are no issues
55  // around whether or not to generate the code when building snapshots.
56  assembler::arm::Simulator::FlushICache(start, size);
57#else
58  // Ideally, we would call
59  //   syscall(__ARM_NR_cacheflush, start,
60  //           reinterpret_cast<intptr_t>(start) + size, 0);
61  // however, syscall(int, ...) is not supported on all platforms, especially
62  // not when using EABI, so we call the __ARM_NR_cacheflush syscall directly.
63
64  register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start);
65  register uint32_t end asm("a2") =
66      reinterpret_cast<uint32_t>(start) + size;
67  register uint32_t flg asm("a3") = 0;
68  #ifdef __ARM_EABI__
69    #if defined (__arm__) && !defined(__thumb__)
70      // __arm__ may be defined in thumb mode.
71      register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
72      asm volatile(
73          "svc 0x0"
74          : "=r" (beg)
75          : "0" (beg), "r" (end), "r" (flg), "r" (scno));
76    #else
77      // r7 is reserved by the EABI in thumb mode.
78      asm volatile(
79      "@   Enter ARM Mode  \n\t"
80          "adr r3, 1f      \n\t"
81          "bx  r3          \n\t"
82          ".ALIGN 4        \n\t"
83          ".ARM            \n"
84      "1:  push {r7}       \n\t"
85          "mov r7, %4      \n\t"
86          "svc 0x0         \n\t"
87          "pop {r7}        \n\t"
88      "@   Enter THUMB Mode\n\t"
89          "adr r3, 2f+1    \n\t"
90          "bx  r3          \n\t"
91          ".THUMB          \n"
92      "2:                  \n\t"
93          : "=r" (beg)
94          : "0" (beg), "r" (end), "r" (flg), "r" (__ARM_NR_cacheflush)
95          : "r3");
96    #endif
97  #else
98    #if defined (__arm__) && !defined(__thumb__)
99      // __arm__ may be defined in thumb mode.
100      asm volatile(
101          "svc %1"
102          : "=r" (beg)
103          : "i" (__ARM_NR_cacheflush), "0" (beg), "r" (end), "r" (flg));
104    #else
105      // Do not use the value of __ARM_NR_cacheflush in the inline assembly
106      // below, because the thumb mode value would be used, which would be
107      // wrong, since we switch to ARM mode before executing the svc instruction
108      asm volatile(
109      "@   Enter ARM Mode  \n\t"
110          "adr r3, 1f      \n\t"
111          "bx  r3          \n\t"
112          ".ALIGN 4        \n\t"
113          ".ARM            \n"
114      "1:  svc 0x9f0002    \n"
115      "@   Enter THUMB Mode\n\t"
116          "adr r3, 2f+1    \n\t"
117          "bx  r3          \n\t"
118          ".THUMB          \n"
119      "2:                  \n\t"
120          : "=r" (beg)
121          : "0" (beg), "r" (end), "r" (flg)
122          : "r3");
123    #endif
124  #endif
125#endif
126}
127
128
129void CPU::DebugBreak() {
130#if !defined (__arm__) || !defined(CAN_USE_ARMV5_INSTRUCTIONS)
131  UNIMPLEMENTED();  // when building ARM emulator target
132#else
133  asm volatile("bkpt 0");
134#endif
135}
136
137} }  // namespace v8::internal
138
139#endif  // V8_TARGET_ARCH_ARM
140