cpu-arm.cc revision 6ded16be15dd865a9b21ea304d5273c8be299c87 
1// Copyright 2006-2009 the V8 project authors. All rights reserved.
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27
28// CPU specific code for arm independent of OS goes here.
29#ifdef __arm__
30#include <sys/syscall.h>  // for cache flushing.
31#endif
32
33#include "v8.h"
34
35#include "cpu.h"
36#include "macro-assembler.h"
37
38#ifndef __arm__
39#include "simulator-arm.h"  // for cache flushing.
40#endif
41
42namespace v8 {
43namespace internal {
44
45void CPU::Setup() {
46  CpuFeatures::Probe();
47}
48
49
50void CPU::FlushICache(void* start, size_t size) {
51#if !defined (__arm__)
52  // Not generating ARM instructions for C-code. This means that we are
53  // building an ARM emulator based target.  We should notify the simulator
54  // that the Icache was flushed.
55  // None of this code ends up in the snapshot so there are no issues
56  // around whether or not to generate the code when building snapshots.
57  assembler::arm::Simulator::FlushICache(start, size);
58#else
59  // Ideally, we would call
60  //   syscall(__ARM_NR_cacheflush, start,
61  //           reinterpret_cast<intptr_t>(start) + size, 0);
62  // however, syscall(int, ...) is not supported on all platforms, especially
63  // not when using EABI, so we call the __ARM_NR_cacheflush syscall directly.
64
65  register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start);
66  register uint32_t end asm("a2") =
67      reinterpret_cast<uint32_t>(start) + size;
68  register uint32_t flg asm("a3") = 0;
69  #ifdef __ARM_EABI__
70    #if defined (__arm__) && !defined(__thumb__)
71      // __arm__ may be defined in thumb mode.
72      register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
73      asm volatile(
74          "swi 0x0"
75          : "=r" (beg)
76          : "0" (beg), "r" (end), "r" (flg), "r" (scno));
77    #else
78      // r7 is reserved by the EABI in thumb mode.
79      asm volatile(
80      "@   Enter ARM Mode  \n\t"
81          "adr r3, 1f      \n\t"
82          "bx  r3          \n\t"
83          ".ALIGN 4        \n\t"
84          ".ARM            \n"
85      "1:  push {r7}       \n\t"
86          "mov r7, %4      \n\t"
87          "swi 0x0         \n\t"
88          "pop {r7}        \n\t"
89      "@   Enter THUMB Mode\n\t"
90          "adr r3, 2f+1    \n\t"
91          "bx  r3          \n\t"
92          ".THUMB          \n"
93      "2:                  \n\t"
94          : "=r" (beg)
95          : "0" (beg), "r" (end), "r" (flg), "r" (__ARM_NR_cacheflush)
96          : "r3");
97    #endif
98  #else
99    #if defined (__arm__) && !defined(__thumb__)
100      // __arm__ may be defined in thumb mode.
101      asm volatile(
102          "swi %1"
103          : "=r" (beg)
104          : "i" (__ARM_NR_cacheflush), "0" (beg), "r" (end), "r" (flg));
105    #else
106      // Do not use the value of __ARM_NR_cacheflush in the inline assembly
107      // below, because the thumb mode value would be used, which would be
108      // wrong, since we switch to ARM mode before executing the swi instruction
109      asm volatile(
110      "@   Enter ARM Mode  \n\t"
111          "adr r3, 1f      \n\t"
112          "bx  r3          \n\t"
113          ".ALIGN 4        \n\t"
114          ".ARM            \n"
115      "1:  swi 0x9f0002    \n"
116      "@   Enter THUMB Mode\n\t"
117          "adr r3, 2f+1    \n\t"
118          "bx  r3          \n\t"
119          ".THUMB          \n"
120      "2:                  \n\t"
121          : "=r" (beg)
122          : "0" (beg), "r" (end), "r" (flg)
123          : "r3");
124    #endif
125  #endif
126#endif
127}
128
129
130void CPU::DebugBreak() {
131#if !defined (__arm__) || !defined(CAN_USE_ARMV5_INSTRUCTIONS)
132  UNIMPLEMENTED();  // when building ARM emulator target
133#else
134  asm volatile("bkpt 0");
135#endif
136}
137
138} }  // namespace v8::internal
139