cpu-arm.cc revision a7e24c173cf37484693b9abb38e494fa7bd7baeb 
1// Copyright 2006-2009 the V8 project authors. All rights reserved.
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3// modification, are permitted provided that the following conditions are
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5//
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27
28// CPU specific code for arm independent of OS goes here.
29#if defined(__arm__)
30#include <sys/syscall.h>  // for cache flushing.
31#endif
32
33#include "v8.h"
34
35#include "cpu.h"
36
37namespace v8 {
38namespace internal {
39
40void CPU::Setup() {
41  // Nothing to do.
42}
43
44
45void CPU::FlushICache(void* start, size_t size) {
46#if !defined (__arm__)
47  // Not generating ARM instructions for C-code. This means that we are
48  // building an ARM emulator based target. No I$ flushes are necessary.
49  // None of this code ends up in the snapshot so there are no issues
50  // around whether or not to generate the code when building snapshots.
51#else
52  // Ideally, we would call
53  //   syscall(__ARM_NR_cacheflush, start,
54  //           reinterpret_cast<intptr_t>(start) + size, 0);
55  // however, syscall(int, ...) is not supported on all platforms, especially
56  // not when using EABI, so we call the __ARM_NR_cacheflush syscall directly.
57
58  register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start);
59  register uint32_t end asm("a2") =
60      reinterpret_cast<uint32_t>(start) + size;
61  register uint32_t flg asm("a3") = 0;
62  #ifdef __ARM_EABI__
63    register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
64    #if defined (__arm__) && !defined(__thumb__)
65      // __arm__ may be defined in thumb mode.
66      asm volatile(
67          "swi 0x0"
68          : "=r" (beg)
69          : "0" (beg), "r" (end), "r" (flg), "r" (scno));
70    #else
71      asm volatile(
72      "@   Enter ARM Mode  \n\t"
73          "adr r3, 1f      \n\t"
74          "bx  r3          \n\t"
75          ".ALIGN 4        \n\t"
76          ".ARM            \n"
77      "1:  swi 0x0         \n\t"
78      "@   Enter THUMB Mode\n\t"
79          "adr r3, 2f+1    \n\t"
80          "bx  r3          \n\t"
81          ".THUMB          \n"
82      "2:                  \n\t"
83          : "=r" (beg)
84          : "0" (beg), "r" (end), "r" (flg), "r" (scno)
85          : "r3");
86    #endif
87  #else
88    #if defined (__arm__) && !defined(__thumb__)
89      // __arm__ may be defined in thumb mode.
90      asm volatile(
91          "swi %1"
92          : "=r" (beg)
93          : "i" (__ARM_NR_cacheflush), "0" (beg), "r" (end), "r" (flg));
94    #else
95      // Do not use the value of __ARM_NR_cacheflush in the inline assembly
96      // below, because the thumb mode value would be used, which would be
97      // wrong, since we switch to ARM mode before executing the swi instruction
98      asm volatile(
99      "@   Enter ARM Mode  \n\t"
100          "adr r3, 1f      \n\t"
101          "bx  r3          \n\t"
102          ".ALIGN 4        \n\t"
103          ".ARM            \n"
104      "1:  swi 0x9f0002    \n"
105      "@   Enter THUMB Mode\n\t"
106          "adr r3, 2f+1    \n\t"
107          "bx  r3          \n\t"
108          ".THUMB          \n"
109      "2:                  \n\t"
110          : "=r" (beg)
111          : "0" (beg), "r" (end), "r" (flg)
112          : "r3");
113    #endif
114  #endif
115#endif
116}
117
118
119void CPU::DebugBreak() {
120#if !defined (__arm__)
121  UNIMPLEMENTED();  // when building ARM emulator target
122#else
123  asm volatile("bkpt 0");
124#endif
125}
126
127} }  // namespace v8::internal
128