/dalvik/vm/alloc/ |
H A D | HeapBitmapInlines.h | 31 const size_t index = HB_OFFSET_TO_INDEX(offset); local 36 assert(index < hb->bitsLen / sizeof(*hb->bits)); 42 unsigned long *p = hb->bits + index; 47 hb->bits[index] |= mask; 50 hb->bits[index] &= ~mask;
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H A D | HeapSource.cpp | 231 * is false, don't count the heap at index 0. 897 size_t index = HB_OFFSET_TO_INDEX( local 900 char *src = (char *)(gHs->liveBits.bits + index); 901 char *dst = (char *)(gHs->markBits.bits + index);
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/dalvik/vm/compiler/codegen/arm/ |
H A D | Assemble.cpp | 1720 int index = gDvmJit.compilerICPatchIndex++; local 1723 gDvmJit.compilerICPatchQueue[index].cellAddr = cellAddr; 1724 gDvmJit.compilerICPatchQueue[index].cellContent = *newContent; 1725 gDvmJit.compilerICPatchQueue[index].classDescriptor = clazz->descriptor; 1726 gDvmJit.compilerICPatchQueue[index].classLoader = clazz->classLoader; 1728 gDvmJit.compilerICPatchQueue[index].serialNumber = clazz->serialNumber;
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H A D | CodegenDriver.cpp | 612 /* Resume here - must reload element & array, regPtr & index preserved */ 2159 // Returns the index of the lowest set bit in 'x'. 2792 int index; local 2820 index = testVal - firstKey; 2823 if (index < 0 || index >= size) { 2826 } else if (index >= MAX_CHAINED_SWITCH_CASES) { 2828 caseDPCOffset = entries[index]; 2831 jumpIndex = index; 3898 * of the index i [all...] |
/dalvik/vm/compiler/codegen/mips/ |
H A D | Assemble.cpp | 1055 int index = gDvmJit.compilerICPatchIndex++; local 1058 gDvmJit.compilerICPatchQueue[index].cellAddr = cellAddr; 1059 gDvmJit.compilerICPatchQueue[index].cellContent = *newContent; 1060 gDvmJit.compilerICPatchQueue[index].classDescriptor = clazz->descriptor; 1061 gDvmJit.compilerICPatchQueue[index].classLoader = clazz->classLoader; 1063 gDvmJit.compilerICPatchQueue[index].serialNumber = clazz->serialNumber;
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H A D | CodegenDriver.cpp | 673 /* Resume here - must reload element & array, regPtr & index preserved */ 2213 // Returns the index of the lowest set bit in 'x'. 2878 int index; local 2904 index = testVal - firstKey; 2907 if (index < 0 || index >= size) { 2910 } else if (index >= MAX_CHAINED_SWITCH_CASES) { 2913 caseDPCOffset = entries[index]; 2915 caseDPCOffset = (unsigned int)entries[index] >> 16 | entries[index] << 1 [all...] |
/dalvik/vm/compiler/codegen/x86/ |
H A D | AnalysisO1.cpp | 1224 ALOGI("insert from entry %d %d: index %d", currentBB->infoBasicBlock[indexToA].regNum, 1382 if reachingDefIndex >= 0, the def is currentInfo.reachingDefs[index] 1716 bool startBeforeRange = false, endBeforeRange = false; //before the index or in the range 2067 int index; local 2069 index = searchCompileTable(LowOpndRegType_virtual | LowOpndRegType_xmm, reg); 2070 if(index >= 0 && compileTable[index].physicalReg != PhysicalReg_Null) { 2075 dumpPartToMem(compileTable[index].physicalReg, reg, false); //dump high of xmm to memory 2076 compileTable[index].physicalReg = PhysicalReg_Null; 2078 index 2135 int index; local 2342 int index = getFreeReg(newType, reg, tIndex); local 2376 int index = searchCompileTable(newType, reg); local 2428 int index = searchVirtualInfoOfBB((LowOpndRegType)(type&MASK_FOR_TYPE), reg, currentBB); local [all...] |
H A D | BytecodeVisitor.cpp | 419 int index = searchCompileTable(LowOpndRegType_virtual | type, vA); local 420 if(index < 0) { 424 compileTable[index].refCount--; 430 int index = searchCompileTable(LowOpndRegType_virtual | type, vA); local 431 if(index < 0) { 435 compileTable[index].refCount--; 436 index = searchCompileTable(LowOpndRegType_virtual | type, vB); 437 if(index < 0) { 441 compileTable[index].refCount--; 3979 0/*index fo [all...] |
H A D | CodegenInterface.cpp | 374 int index = gDvmJit.compilerICPatchIndex++; local 377 gDvmJit.compilerICPatchQueue[index].cellAddr = cellAddr; 378 gDvmJit.compilerICPatchQueue[index].cellContent = *newContent; 379 gDvmJit.compilerICPatchQueue[index].classDescriptor = clazz->descriptor; 380 gDvmJit.compilerICPatchQueue[index].classLoader = clazz->classLoader; 382 gDvmJit.compilerICPatchQueue[index].serialNumber = clazz->serialNumber; 801 /* assign index in virtual register to P_GPR_2 */ 809 * of the index is "endCondition - 1". 840 /* assign index in virtual register to P_GPR_2 */ 957 /* check whether we can merge the block at index [all...] |
H A D | Lower.h | 276 int index; //enum PhysicalReg for "Reg" type member in struct:UseDefProducerEntry 282 int index; member in struct:UseDefUserEntry 296 int index; member in struct:LowOpndMem 864 int startLR/*logical register index*/, bool isPhysical, int tmp/*const pool index*/, 868 int startLR/*logical register index*/, bool startPhysical); 871 int startLR/*logical register index*/, bool startPhysical); 1141 void set_mem_opnd_scale(LowOpndMem* mem, int base, bool isPhysical, int disp, int index, bool indexPhysical, int scale);
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H A D | LowerHelper.cpp | 57 //the index to the table is the opcode 138 void set_mem_opnd_scale(LowOpndMem* mem, int base, bool isPhysical, int disp, int index, bool indexPhysical, int scale) { argument 149 mem->m_index.physicalReg = index; 151 mem->m_index.logicalReg = index; 590 donotSpillReg(baseAll); //make sure index will not use the same physical reg 2793 INPUT: const pool index in %eax 2821 INPUT: const pool index in argument "indexReg" (%eax) 2830 int startLR/*scratch register*/, bool isPhysical, int indexReg/*const pool index*/, 2836 //push index to stack first, to free indexReg 2853 INPUT: const pool index i [all...] |
/dalvik/vm/compiler/codegen/x86/libenc/ |
H A D | dec_base.cpp | 467 RegName index = RegName_Null; local 483 //base and index should be 32 bits!!! 491 if (sib.index != 4) { 492 index = getRegName(OpndKind_GPReg, OpndSize_32, EXTEND_REG(sib.index, x)); //Android x86: OpndDesc.size 494 // (sib.index == 4) => no index 495 //%esp can't be sib.index 537 opnd = EncoderBase::Operand(opndDesc.size, base, index, scale, disp);
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H A D | enc_base.cpp | 417 assert(original.index() == decoded.index()); 471 // we have index & scale (nb: having index w/o base and w/o scale 474 // the base is ESP (nb: cant have ESP as index) 478 if (base == RegName_Null && op.index() == RegName_Null) { 479 assert(op.scale() == 0); // 'scale!=0' has no meaning without index 488 sib.index = 4; // 100 - none 507 if (op.index() == RegName_Null && getHWRegIndex(op.base()) != getHWRegIndex(REG_STACK)) { 508 assert(op.scale() == 0); // 'scale!=0' has no meaning without index [all...] |
H A D | enc_base.h | 74 static char * getOpndLocation(int index); 375 Operand(OpndSize size, RegName base, RegName index, unsigned scale, 379 m_index = index; 462 * @brief Returns index of memory operand (RegName_Null if not memory). 464 RegName index(void) const { return is_mem() ? m_index : RegName_Null; } 651 * @brief Returns an 'processor's index' of the register - the index 654 * For the new EM64T registers the 'HW index' differs from the index
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H A D | enc_prvt.h | 265 * @brief Describes SIB (scale,index,base) byte. 269 unsigned char index:3; member in struct:SIB
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H A D | enc_wrapper.cpp | 98 getRegNameString(opnd.index()), opnd.scale()); 517 getRegNameString(opnd.index()), opnd.scale());
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H A D | encoder.h | 333 // Can also serve as a full memory operand with base,index, displacement and scale. 334 // Use n_reg to specify 'no register', say, for index. 357 inline const R_Opnd & index(void) const { return m_index; } function in class:M_Opnd 376 // a memory operand with base register, scaled index register 382 M_Index_Opnd(Reg_No base, Reg_No index, I_32 disp, unsigned scale): argument 383 M_Opnd(disp, base, index, scale) {}
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H A D | encoder.inl | 76 map_reg(m.base().reg_no()), map_reg(m.index().reg_no()), 87 // don't start with 0, so it is necessary to subtract xmm0_reg index from
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/dalvik/vm/compiler/template/ |
H A D | gen-template.py | 127 index = opcodes.index(tokens[1])
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/dalvik/vm/interp/ |
H A D | Interp.cpp | 166 * Returns the index of the breakpoint entry, or -1 if not found. 1024 int index = testVal - firstKey; local 1025 if (index < 0 || index >= size) { 1037 assert(index >= 0 && index < size); 1039 testVal, index, 1040 s4FromSwitchData(&entries[index])); 1041 return s4FromSwitchData(&entries[index]);
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/dalvik/vm/mterp/armv5te/ |
H A D | OP_AGET.S | 16 GET_VREG(r1, r3) @ r1<- vCC (requested index) 20 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width 21 cmp r1, r3 @ compare unsigned index, length 22 bcs common_errArrayIndex @ index >= length, bail
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H A D | OP_AGET_WIDE.S | 13 GET_VREG(r1, r3) @ r1<- vCC (requested index) 17 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 18 cmp r1, r3 @ compare unsigned index, length 20 b common_errArrayIndex @ index >= length, bail
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H A D | OP_APUT.S | 16 GET_VREG(r1, r3) @ r1<- vCC (requested index) 20 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width 21 cmp r1, r3 @ compare unsigned index, length 22 bcs common_errArrayIndex @ index >= length, bail
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H A D | OP_APUT_OBJECT.S | 11 GET_VREG(r1, r3) @ r1<- vCC (requested index) 16 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width 17 cmp r1, r3 @ compare unsigned index, length 19 b common_errArrayIndex @ index >= length, bail
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H A D | OP_APUT_WIDE.S | 13 GET_VREG(r1, r3) @ r1<- vCC (requested index) 17 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 18 cmp r1, r3 @ compare unsigned index, length 21 b common_errArrayIndex @ index >= length, bail
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