Searched refs:reg (Results 1 - 25 of 96) sorted by relevance

1234

/dalvik/libdex/
H A DDexDebugInfo.cpp120 static void emitLocalCbIfLive(void *cnxt, int reg, u4 endAddress, argument
123 if (localCb != NULL && localInReg[reg].live) {
124 localCb(cnxt, reg, localInReg[reg].startAddress, endAddress,
125 localInReg[reg].name,
126 localInReg[reg].descriptor,
127 localInReg[reg].signature == NULL
128 ? "" : localInReg[reg].signature );
182 int reg; local
190 reg
213 u2 reg; local
[all...]
H A DDexDebugInfo.h36 typedef void (*DexDebugNewLocalCb)(void *cnxt, u2 reg, u4 startAddress,
/dalvik/dexgen/src/com/android/dexgen/rop/code/
H A DRegisterSpec.java44 private final int reg; field in class:RegisterSpec
55 * @param reg {@code >= 0;} the register number
61 private static RegisterSpec intern(int reg, TypeBearer type, argument
63 theInterningItem.set(reg, type, local);
80 * @param reg {@code >= 0;} the register number
85 public static RegisterSpec make(int reg, TypeBearer type) { argument
86 return intern(reg, type, null);
94 * @param reg {@code >= 0;} the register number
100 public static RegisterSpec make(int reg, TypeBearer type, argument
106 return intern(reg, typ
121 makeLocalOptional( int reg, TypeBearer type, LocalItem local) argument
133 regString(int reg) argument
146 RegisterSpec(int reg, TypeBearer type, LocalItem local) argument
222 equals(int reg, TypeBearer type, LocalItem local) argument
273 hashCodeOf(int reg, TypeBearer type, LocalItem local) argument
596 private int reg; field in class:RegisterSpec.ForComparison
617 set(int reg, TypeBearer type, LocalItem local) argument
[all...]
H A DRegisterSpecSet.java33 * {@code null} or is an instance whose {@code reg}
163 * @param reg {@code >= 0;} the desired register number
167 public RegisterSpec get(int reg) { argument
169 return specs[reg];
172 throw new IllegalArgumentException("bogus reg");
201 for (int reg = 0; reg < length; reg++) {
202 RegisterSpec s = specs[reg];
226 for (int reg
[all...]
/dalvik/dx/src/com/android/dx/rop/code/
H A DRegisterSpec.java43 private final int reg; field in class:RegisterSpec
57 * @param reg {@code >= 0;} the register number
63 private static RegisterSpec intern(int reg, TypeBearer type, argument
66 theInterningItem.set(reg, type, local);
84 * @param reg {@code >= 0;} the register number
89 public static RegisterSpec make(int reg, TypeBearer type) { argument
90 return intern(reg, type, null);
98 * @param reg {@code >= 0;} the register number
104 public static RegisterSpec make(int reg, TypeBearer type, argument
110 return intern(reg, typ
125 makeLocalOptional( int reg, TypeBearer type, LocalItem local) argument
137 regString(int reg) argument
150 RegisterSpec(int reg, TypeBearer type, LocalItem local) argument
226 equals(int reg, TypeBearer type, LocalItem local) argument
277 hashCodeOf(int reg, TypeBearer type, LocalItem local) argument
602 private int reg; field in class:RegisterSpec.ForComparison
623 set(int reg, TypeBearer type, LocalItem local) argument
[all...]
H A DRegisterSpecSet.java32 * {@code null} or is an instance whose {@code reg}
162 * @param reg {@code >= 0;} the desired register number
166 public RegisterSpec get(int reg) { argument
168 return specs[reg];
171 throw new IllegalArgumentException("bogus reg");
200 for (int reg = 0; reg < length; reg++) {
201 RegisterSpec s = specs[reg];
225 for (int reg
[all...]
/dalvik/vm/compiler/codegen/x86/libenc/
H A Denc_base.h169 RegName reg;
317 Operand(RegName reg, OpndExt ext = OpndExt_None) : m_kind(getRegKind(reg)),
318 m_size(getRegSize(reg)),
319 m_ext(ext), m_reg(reg)
331 Operand(OpndSize sz, OpndKind kind, RegName reg, OpndExt ext = OpndExt_None) :
332 m_kind(kind), m_size(sz), m_ext(ext), m_reg(reg)
334 assert(m_size == getRegSize(reg));
335 assert(m_kind == getRegKind(reg));
477 RegName reg(voi
[all...]
H A Denc_wrapper.h183 int reg, bool isPhysical, LowOpndRegType type, char* stream);
185 int reg, bool isPhysical,
189 int reg, bool isPhysical, LowOpndRegType type, char* stream);
192 int reg, bool isPhysical, LowOpndRegType type, char* stream);
194 int reg, bool isPhysical,
199 int reg, bool isPhysical, LowOpndRegType type, char * stream);
202 int reg, bool isPhysical, LowOpndRegType type, char * stream);
204 int reg, bool isPhysical,
208 int reg, bool isPhysical,
211 int imm, int reg, boo
[all...]
/dalvik/vm/mterp/x86/
H A Dheader.S53 nick reg purpose
58 rINSTbh bh high byte of inst word, usually contains src/tgt reg names
111 #define SPILL(reg) movl reg##,reg##_SPILL(%ebp)
112 #define UNSPILL(reg) movl reg##_SPILL(%ebp),reg
113 #define SPILL_TMP1(reg) movl reg,TMP_SPILL
[all...]
/dalvik/vm/compiler/codegen/x86/
H A DNcgAot.h37 int reg, bool isPhysical);
40 int reg, bool isPhysical);
42 int reg, bool isPhysical);
H A DLower.h521 #define C_SCRATCH_3 scratchRegs[2] //scratch reg inside callee
563 int registerAlloc(int type, int reg, bool isPhysical, bool updateRef);
564 int registerAllocMove(int reg, int type, bool isPhysical, int srcReg);
565 int checkVirtualReg(int reg, LowOpndRegType type, int updateRef); //returns the physical register
566 int updateRefCount(int reg, LowOpndRegType type);
567 int updateRefCount2(int reg, int type, bool isPhysical);
570 int checkTempReg(int reg, int type, bool isPhysical, int vA);
571 bool checkTempReg2(int reg, int type, bool isPhysical, int physicalRegForVR);
574 int updateVirtualReg(int reg, LowOpndRegType type);
584 void updateGlue(int reg, boo
[all...]
H A DLowerHelper.cpp110 void set_reg_opnd(LowOpndReg* op_reg, int reg, bool isPhysical, LowOpndRegType type) { argument
114 op_reg->physicalReg = reg;
117 op_reg->logicalReg = reg;
291 //!update fields of LowOp and generate a x86 instruction that takes a single reg operand
295 int reg, LowOpndRegType type) {
296 stream = encoder_reg(m, size, reg, true, type, stream);
301 int reg, bool isPhysical, LowOpndRegType type) {
309 int regAll = registerAlloc(type, reg, isPhysical, true);
312 stream = encoder_reg(m, size, reg, isPhysical, type, stream);
317 int reg, boo
294 lower_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, LowOpndRegType type) argument
300 dump_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, LowOpndRegType type) argument
316 dump_reg_noalloc(Mnemonic m, OpndSize size, int reg, bool isPhysical, LowOpndRegType type) argument
321 lower_reg_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, int reg2, LowOpndRegType type) argument
336 dump_reg_reg_noalloc(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
350 dump_reg_reg_noalloc_dst(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
366 dump_reg_reg_noalloc_src(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
387 dump_reg_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
420 lower_mem_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int disp, int base_reg, MemoryAccessType mType, int mIndex, int reg, LowOpndRegType type, bool isMoves) argument
442 dump_mem_reg_noalloc(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical, LowOpndRegType type) argument
451 dump_mem_reg_noalloc_mem(Mnemonic m, AtomOpCode m2, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical, LowOpndRegType type) argument
467 dump_mem_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical, LowOpndRegType type) argument
493 dump_moves_mem_reg(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
513 dump_movez_mem_reg(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
534 dump_movez_reg_reg(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
566 lower_mem_scale_reg(Mnemonic m, OpndSize size, int base_reg, int disp, int index_reg, int scale, int reg, LowOpndRegType type) argument
583 dump_mem_scale_reg(Mnemonic m, OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical, LowOpndRegType type) argument
611 lower_reg_mem_scale(Mnemonic m, OpndSize size, int reg, int base_reg, int disp, int index_reg, int scale, LowOpndRegType type) argument
622 dump_reg_mem_scale(Mnemonic m, OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, LowOpndRegType type) argument
645 lower_reg_mem(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, int disp, int base_reg, MemoryAccessType mType, int mIndex, LowOpndRegType type) argument
652 dump_reg_mem_noalloc(Mnemonic m, OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, LowOpndRegType type) argument
661 dump_reg_mem(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, LowOpndRegType type) argument
681 lower_imm_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int imm, int reg, LowOpndRegType type, bool chaining) argument
687 dump_imm_reg_noalloc(Mnemonic m, OpndSize size, int imm, int reg, bool isPhysical, LowOpndRegType type) argument
694 dump_imm_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int imm, int reg, bool isPhysical, LowOpndRegType type, bool chaining) argument
746 lower_fp_mem(Mnemonic m, OpndSize size, int reg, int disp, int base_reg, MemoryAccessType mType, int mIndex) argument
752 dump_fp_mem(Mnemonic m, OpndSize size, int reg, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex) argument
767 lower_mem_fp(Mnemonic m, OpndSize size, int disp, int base_reg, MemoryAccessType mType, int mIndex, int reg) argument
773 dump_mem_fp(Mnemonic m, OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg) argument
796 load_effective_addr(int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
805 load_effective_addr_scale(int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
873 compare_reg_mem(LowOp* op, OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
881 compare_mem_reg(OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
890 compare_VR_reg_all(OpndSize size, int vA, int reg, bool isPhysical, Mnemonic m) argument
954 compare_VR_reg(OpndSize size, int vA, int reg, bool isPhysical) argument
960 compare_VR_ss_reg(int vA, int reg, bool isPhysical) argument
964 compare_VR_sd_reg(int vA, int reg, bool isPhysical) argument
1078 compare_imm_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1145 compare_ss_mem_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1162 compare_sd_mem_with_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1179 compare_fp_stack(bool pop, int reg, bool isDouble) argument
1200 test_imm_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1206 test_imm_mem(OpndSize size, int imm, int disp, int reg, bool isPhysical) argument
1212 alu_unary_reg(OpndSize size, ALU_Opcode opc, int reg, bool isPhysical) argument
1245 alu_binary_imm_reg(OpndSize size, ALU_Opcode opc, int imm, int reg, bool isPhysical) argument
1256 alu_binary_mem_reg(OpndSize size, ALU_Opcode opc, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1267 alu_sd_binary_VR_reg(ALU_Opcode opc, int vA, int reg, bool isPhysical, bool isSD) argument
1320 alu_binary_VR_reg(OpndSize size, ALU_Opcode opc, int vA, int reg, bool isPhysical) argument
1382 alu_binary_reg_mem(OpndSize size, ALU_Opcode opc, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1402 alu_ss_binary_reg_reg(ALU_Opcode opc, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1410 alu_sd_binary_reg_reg(ALU_Opcode opc, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1418 push_reg_to_stack(OpndSize size, int reg, bool isPhysical) argument
1430 move_reg_to_mem(OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1439 move_reg_to_mem_noalloc(OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex) argument
1449 move_mem_to_reg(OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1458 move_mem_to_reg_noalloc(OpndSize size, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical) argument
1468 move_ss_mem_to_reg_noalloc(int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex, int reg, bool isPhysical) argument
1476 move_ss_reg_to_mem_noalloc(int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical, MemoryAccessType mType, int mIndex) argument
1484 movez_mem_to_reg(OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1494 movez_reg_to_reg(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1501 movez_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1509 moves_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1521 moves_mem_to_reg(LowOp* op, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1530 move_reg_to_reg(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1539 move_reg_to_reg_noalloc(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1548 move_mem_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1555 move_mem_disp_scale_to_reg(OpndSize size, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale, int reg, bool isPhysical) argument
1565 move_reg_to_mem_scale(OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale) argument
1573 move_reg_to_mem_disp_scale(OpndSize size, int reg, bool isPhysical, int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale) argument
1638 move_chain_to_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1645 move_imm_to_reg(OpndSize size, int imm, int reg, bool isPhysical) argument
1654 move_imm_to_reg_noalloc(OpndSize size, int imm, int reg, bool isPhysical) argument
1663 conditional_move_reg_to_reg(OpndSize size, ConditionCode cc, int reg1, bool isPhysical1, int reg, bool isPhysical) argument
1670 move_ss_mem_to_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1678 move_ss_reg_to_mem(LowOp* op, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1685 move_sd_mem_to_reg(int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1692 move_sd_reg_to_mem(LowOp* op, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1701 get_virtual_reg_all(u2 vB, OpndSize size, int reg, bool isPhysical, Mnemonic m) argument
1788 get_virtual_reg(u2 vB, OpndSize size, int reg, bool isPhysical) argument
1792 get_virtual_reg_noalloc(u2 vB, OpndSize size, int reg, bool isPhysical) argument
1802 set_virtual_reg_all(u2 vA, OpndSize size, int reg, bool isPhysical, Mnemonic m) argument
1861 set_virtual_reg(u2 vA, OpndSize size, int reg, bool isPhysical) argument
1865 set_virtual_reg_noalloc(u2 vA, OpndSize size, int reg, bool isPhysical) argument
1870 get_VR_ss(int vB, int reg, bool isPhysical) argument
1873 set_VR_ss(int vA, int reg, bool isPhysical) argument
1876 get_VR_sd(int vB, int reg, bool isPhysical) argument
1879 set_VR_sd(int vA, int reg, bool isPhysical) argument
1886 get_currentpc(int reg, bool isPhysical) argument
1893 simpleNullCheck(int reg, bool isPhysical, int vr) argument
1934 nullCheck(int reg, bool isPhysical, int exceptionNum, int vr) argument
2009 get_self_pointer(int reg, bool isPhysical) argument
2016 get_res_strings(int reg, bool isPhysical) argument
2044 get_res_classes(int reg, bool isPhysical) argument
2069 get_res_fields(int reg, bool isPhysical) argument
2094 get_res_methods(int reg, bool isPhysical) argument
2119 get_glue_method_class(int reg, bool isPhysical) argument
2128 get_glue_method(int reg, bool isPhysical) argument
2136 set_glue_method(int reg, bool isPhysical) argument
2145 get_glue_dvmdex(int reg, bool isPhysical) argument
2170 set_glue_dvmdex(int reg, bool isPhysical) argument
2178 get_suspendCount(int reg, bool isPhysical) argument
2187 get_return_value(OpndSize size, int reg, bool isPhysical) argument
2195 set_return_value(OpndSize size, int reg, bool isPhysical) argument
2211 get_exception(int reg, bool isPhysical) argument
2219 set_exception(int reg, bool isPhysical) argument
2239 savearea_from_fp(int reg, bool isPhysical) argument
[all...]
/dalvik/vm/compiler/codegen/
H A DRallocUtil.cpp62 regs[i].reg = regNums[i];
77 p[i].reg, p[i].inUse, p[i].pair, p[i].partner, p[i].live,
83 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg) argument
89 if (p[i].reg == reg) {
96 if (p[i].reg == reg) {
100 ALOGE("Tried to get info on a non-existant temp: r%d",reg);
110 (info1->partner == info2->reg) &&
111 (info2->partner == info1->reg));
124 dvmCompilerFlushReg(CompilationUnit *cUnit, int reg) argument
136 clobberRegBody(CompilationUnit *cUnit, RegisterInfo *p, int numTemps, int reg) argument
165 dvmCompilerClobber(CompilationUnit *cUnit, int reg) argument
342 dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg) argument
367 dvmCompilerIsLive(CompilationUnit *cUnit, int reg) argument
387 dvmCompilerIsTemp(CompilationUnit *cUnit, int reg) argument
412 dvmCompilerLockTemp(CompilationUnit *cUnit, int reg) argument
437 dvmCompilerResetDef(CompilationUnit *cUnit, int reg) argument
606 regClassMatches(int regClass, int reg) argument
617 dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg) argument
641 dvmCompilerMarkClean(CompilationUnit *cUnit, int reg) argument
647 dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg) argument
653 dvmCompilerMarkInUse(CompilationUnit *cUnit, int reg) argument
[all...]
H A DRalloc.h82 extern void dvmCompilerClobber(CompilationUnit *cUnit, int reg);
94 extern void dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg);
96 extern void dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg);
101 extern void dvmCompilerMarkClean(CompilationUnit *cUnit, int reg);
103 extern void dvmCompilerResetDef(CompilationUnit *cUnit, int reg);
142 extern RegisterInfo *dvmCompilerIsTemp(CompilationUnit *cUnit, int reg);
144 extern void dvmCompilerMarkInUse(CompilationUnit *cUnit, int reg);
153 extern void dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg);
164 extern RegisterInfo *dvmCompilerIsLive(CompilationUnit *cUnit, int reg);
188 extern void dvmCompilerLockTemp(CompilationUnit *cUnit, int reg);
[all...]
/dalvik/vm/compiler/codegen/mips/
H A DRallocUtil.cpp64 regs[i].reg = regNums[i];
79 p[i].reg, p[i].inUse, p[i].pair, p[i].partner, p[i].live,
85 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg) argument
91 if (p[i].reg == reg) {
98 if (p[i].reg == reg) {
102 ALOGE("Tried to get info on a non-existant temp: r%d",reg);
112 (info1->partner == info2->reg) &&
113 (info2->partner == info1->reg));
126 flushReg(CompilationUnit *cUnit, int reg) argument
138 clobberRegBody(CompilationUnit *cUnit, RegisterInfo *p, int numTemps, int reg) argument
167 dvmCompilerClobber(CompilationUnit *cUnit, int reg) argument
343 dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg) argument
372 dvmCompilerIsLive(CompilationUnit *cUnit, int reg) argument
392 dvmCompilerIsTemp(CompilationUnit *cUnit, int reg) argument
417 dvmCompilerLockTemp(CompilationUnit *cUnit, int reg) argument
503 dvmCompilerResetDef(CompilationUnit *cUnit, int reg) argument
678 regClassMatches(int regClass, int reg) argument
689 dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg) argument
713 dvmCompilerMarkClean(CompilationUnit *cUnit, int reg) argument
719 dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg) argument
725 dvmCompilerMarkInUse(CompilationUnit *cUnit, int reg) argument
1022 dvmCompilerFlushRegForV5TEVFP(CompilationUnit *cUnit, int reg) argument
[all...]
H A DRalloc.h86 extern void dvmCompilerClobber(CompilationUnit *cUnit, int reg);
98 extern void dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg);
100 extern void dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg);
105 extern void dvmCompilerMarkClean(CompilationUnit *cUnit, int reg);
107 extern void dvmCompilerResetDef(CompilationUnit *cUnit, int reg);
146 extern RegisterInfo *dvmCompilerIsTemp(CompilationUnit *cUnit, int reg);
148 extern void dvmCompilerMarkInUse(CompilationUnit *cUnit, int reg);
157 extern void dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg);
168 extern RegisterInfo *dvmCompilerIsLive(CompilationUnit *cUnit, int reg);
192 extern void dvmCompilerLockTemp(CompilationUnit *cUnit, int reg);
[all...]
/dalvik/dx/src/com/android/dx/ssa/
H A DPhiTypeResolver.java69 for (int reg = 0; reg < regCount; reg++) {
70 SsaInsn definsn = ssaMeth.getDefinitionForRegister(reg);
74 worklist.set(reg);
78 int reg;
79 while ( 0 <= (reg = worklist.nextSetBit(0))) {
80 worklist.clear(reg);
86 PhiInsn definsn = (PhiInsn)ssaMeth.getDefinitionForRegister(reg);
94 List<SsaInsn> useList = ssaMeth.getUseListForRegister(reg);
[all...]
H A DSsaInsn.java112 * Returns whether or not the specified reg is the result reg.
114 * @param reg register to test
118 public boolean isResultReg(int reg) { argument
119 return result != null && result.getReg() == reg;
127 * @param reg new result register
129 public void changeResultReg(int reg) { argument
131 result = result.withReg(reg);
212 * @param reg the register in question
213 * @return true if the reg i
215 isRegASource(int reg) argument
[all...]
/dalvik/dexgen/src/com/android/dexgen/dex/code/form/
H A DForm31c.java77 RegisterSpec reg;
81 reg = regs.get(0);
89 reg = regs.get(0);
90 if (reg.getReg() != regs.get(1).getReg()) {
100 if (!unsignedFitsInByte(reg.getReg())) {
H A DForm21c.java77 RegisterSpec reg;
81 reg = regs.get(0);
89 reg = regs.get(0);
90 if (reg.getReg() != regs.get(1).getReg()) {
100 if (!unsignedFitsInByte(reg.getReg())) {
/dalvik/dexgen/src/com/android/dexgen/dex/file/
H A DDebugInfoDecoder.java56 /** indexed by register, the last local variable live in a reg */
153 public int reg; field in class:DebugInfoDecoder.LocalEntry
164 public LocalEntry(int address, boolean isStart, int reg, int nameIndex, argument
168 this.reg = reg;
176 address, isStart ? "start" : "end", reg,
294 int reg = readUnsignedLeb128(bs);
298 address, true, reg, nameIdx, typeIdx, 0);
301 lastEntryForReg[reg] = le;
306 int reg
[all...]
/dalvik/dx/src/com/android/dx/dex/file/
H A DDebugInfoDecoder.java67 /** indexed by register, the last local variable live in a reg */
164 public int reg; field in class:DebugInfoDecoder.LocalEntry
175 public LocalEntry(int address, boolean isStart, int reg, int nameIndex, argument
179 this.reg = reg;
187 address, isStart ? "start" : "end", reg,
298 int reg = Leb128.readUnsignedLeb128(bs);
302 address, true, reg, nameIdx, typeIdx, 0);
305 lastEntryForReg[reg] = le;
310 int reg
[all...]
/dalvik/dx/src/com/android/dx/ssa/back/
H A DRegisterAllocator.java76 * @param reg register
79 protected final int getCategoryForSsaReg(int reg) { argument
80 SsaInsn definition = ssaMeth.getDefinitionForRegister(reg);
83 // an undefined reg
93 * @param reg {@code >= 0;} SSA register
97 protected final RegisterSpec getDefinitionSpecForSsaReg(int reg) { argument
98 SsaInsn definition = ssaMeth.getDefinitionForRegister(reg);
107 * @param reg register in question
110 protected boolean isDefinitionMoveParam(int reg) { argument
111 SsaInsn defInsn = ssaMeth.getDefinitionForRegister(reg);
133 insertMoveBefore(SsaInsn insn, RegisterSpec reg) argument
[all...]
H A DInterferenceGraph.java79 * @param reg {@code >= 0;} register
83 public void mergeInterferenceSet(int reg, IntSet set) { argument
84 if (reg < interference.size()) {
85 set.merge(interference.get(reg));
/dalvik/dx/src/com/android/dx/dex/code/form/
H A DForm21c.java78 RegisterSpec reg;
82 reg = regs.get(0);
90 reg = regs.get(0);
91 if (reg.getReg() != regs.get(1).getReg()) {
101 if (!unsignedFitsInByte(reg.getReg())) {

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