1a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden%default {"preinstr":""} 2a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 5a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 6a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 8a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 9a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 11a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 12a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 13a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 14a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden $preinstr @ optional op; may set condition codes 15a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 16a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden $instr @ r0<- op, r0-r3 changed 17a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 18a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 19a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 20a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 21