hwc.cpp revision 54aa0d2841777939a8d4e7e6edcbda06f1e241c9
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include <errno.h> 17#include <fcntl.h> 18#include <poll.h> 19#include <pthread.h> 20#include <stdio.h> 21#include <stdlib.h> 22 23#include <sys/ioctl.h> 24#include <sys/mman.h> 25#include <sys/time.h> 26#include <sys/resource.h> 27 28#include <s3c-fb.h> 29 30#include <EGL/egl.h> 31 32#define HWC_REMOVE_DEPRECATED_VERSIONS 1 33 34#include <cutils/compiler.h> 35#include <cutils/log.h> 36#include <cutils/properties.h> 37#include <hardware/gralloc.h> 38#include <hardware/hardware.h> 39#include <hardware/hwcomposer.h> 40#include <hardware_legacy/uevent.h> 41#include <utils/String8.h> 42#include <utils/Vector.h> 43 44#include <sync/sync.h> 45 46#include "ion.h" 47#include "gralloc_priv.h" 48#include "exynos_gscaler.h" 49#include "exynos_format.h" 50#include "exynos_v4l2.h" 51#include "s5p_tvout_v4l2.h" 52 53const size_t NUM_HW_WINDOWS = 5; 54const size_t NO_FB_NEEDED = NUM_HW_WINDOWS + 1; 55const size_t MAX_PIXELS = 2560 * 1600 * 2; 56const size_t GSC_W_ALIGNMENT = 16; 57const size_t GSC_H_ALIGNMENT = 16; 58const int AVAILABLE_GSC_UNITS[] = { 0, 3 }; 59const size_t NUM_GSC_UNITS = sizeof(AVAILABLE_GSC_UNITS) / 60 sizeof(AVAILABLE_GSC_UNITS[0]); 61 62struct exynos5_hwc_composer_device_1_t; 63 64struct exynos5_gsc_map_t { 65 enum { 66 GSC_NONE = 0, 67 GSC_M2M, 68 // TODO: GSC_LOCAL_PATH 69 } mode; 70 int idx; 71}; 72 73struct exynos5_hwc_post_data_t { 74 int overlay_map[NUM_HW_WINDOWS]; 75 exynos5_gsc_map_t gsc_map[NUM_HW_WINDOWS]; 76 size_t fb_window; 77}; 78 79const size_t NUM_GSC_DST_BUFS = 3; 80struct exynos5_gsc_data_t { 81 void *gsc; 82 exynos_gsc_img src_cfg; 83 exynos_gsc_img dst_cfg; 84 buffer_handle_t dst_buf[NUM_GSC_DST_BUFS]; 85 size_t current_buf; 86}; 87 88struct exynos5_hwc_composer_device_1_t { 89 hwc_composer_device_1_t base; 90 91 int fd; 92 int vsync_fd; 93 exynos5_hwc_post_data_t bufs; 94 95 const private_module_t *gralloc_module; 96 alloc_device_t *alloc_device; 97 const hwc_procs_t *procs; 98 pthread_t vsync_thread; 99 int force_gpu; 100 101 int32_t xres; 102 int32_t yres; 103 int32_t xdpi; 104 int32_t ydpi; 105 int32_t vsync_period; 106 107 int hdmi_mixer0; 108 int hdmi_layer0; 109 int hdmi_layer1; 110 bool hdmi_hpd; 111 bool hdmi_enabled; 112 bool hdmi_blanked; 113 void *hdmi_gsc; 114 int hdmi_w; 115 int hdmi_h; 116 exynos_gsc_img hdmi_src; 117 exynos_gsc_img hdmi_dst; 118 119 exynos5_gsc_data_t gsc[NUM_GSC_UNITS]; 120 121 struct s3c_fb_win_config last_config[NUM_HW_WINDOWS]; 122 size_t last_fb_window; 123 const void *last_handles[NUM_HW_WINDOWS]; 124 exynos5_gsc_map_t last_gsc_map[NUM_HW_WINDOWS]; 125}; 126 127static void dump_handle(private_handle_t *h) 128{ 129 ALOGV("\t\tformat = %d, width = %u, height = %u, stride = %u, vstride = %u", 130 h->format, h->width, h->height, h->stride, h->vstride); 131} 132 133static void dump_layer(hwc_layer_1_t const *l) 134{ 135 ALOGV("\ttype=%d, flags=%08x, handle=%p, tr=%02x, blend=%04x, " 136 "{%d,%d,%d,%d}, {%d,%d,%d,%d}", 137 l->compositionType, l->flags, l->handle, l->transform, 138 l->blending, 139 l->sourceCrop.left, 140 l->sourceCrop.top, 141 l->sourceCrop.right, 142 l->sourceCrop.bottom, 143 l->displayFrame.left, 144 l->displayFrame.top, 145 l->displayFrame.right, 146 l->displayFrame.bottom); 147 148 if(l->handle && !(l->flags & HWC_SKIP_LAYER)) 149 dump_handle(private_handle_t::dynamicCast(l->handle)); 150} 151 152static void dump_config(s3c_fb_win_config &c) 153{ 154 ALOGV("\tstate = %u", c.state); 155 if (c.state == c.S3C_FB_WIN_STATE_BUFFER) { 156 ALOGV("\t\tfd = %d, offset = %u, stride = %u, " 157 "x = %d, y = %d, w = %u, h = %u, " 158 "format = %u, blending = %u", 159 c.fd, c.offset, c.stride, 160 c.x, c.y, c.w, c.h, 161 c.format, c.blending); 162 } 163 else if (c.state == c.S3C_FB_WIN_STATE_COLOR) { 164 ALOGV("\t\tcolor = %u", c.color); 165 } 166} 167 168static void dump_gsc_img(exynos_gsc_img &c) 169{ 170 ALOGV("\tx = %u, y = %u, w = %u, h = %u, fw = %u, fh = %u", 171 c.x, c.y, c.w, c.h, c.fw, c.fh); 172 ALOGV("\taddr = {%u, %u, %u}, rot = %u, cacheable = %u, drmMode = %u", 173 c.yaddr, c.uaddr, c.vaddr, c.rot, c.cacheable, c.drmMode); 174} 175 176inline int WIDTH(const hwc_rect &rect) { return rect.right - rect.left; } 177inline int HEIGHT(const hwc_rect &rect) { return rect.bottom - rect.top; } 178template<typename T> inline T max(T a, T b) { return (a > b) ? a : b; } 179template<typename T> inline T min(T a, T b) { return (a < b) ? a : b; } 180 181static bool is_transformed(const hwc_layer_1_t &layer) 182{ 183 return layer.transform != 0; 184} 185 186static bool is_rotated(const hwc_layer_1_t &layer) 187{ 188 return (layer.transform & HAL_TRANSFORM_ROT_90) || 189 (layer.transform & HAL_TRANSFORM_ROT_180); 190} 191 192static bool is_scaled(const hwc_layer_1_t &layer) 193{ 194 return WIDTH(layer.displayFrame) != WIDTH(layer.sourceCrop) || 195 HEIGHT(layer.displayFrame) != HEIGHT(layer.sourceCrop); 196} 197 198static inline bool gsc_dst_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 199{ 200 return c1.x != c2.x || 201 c1.y != c2.y || 202 c1.w != c2.w || 203 c1.h != c2.h || 204 c1.format != c2.format || 205 c1.rot != c2.rot || 206 c1.cacheable != c2.cacheable || 207 c1.drmMode != c2.drmMode; 208} 209 210static inline bool gsc_src_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 211{ 212 return gsc_dst_cfg_changed(c1, c2) || 213 c1.fw != c2.fw || 214 c1.fh != c2.fh; 215} 216 217static enum s3c_fb_pixel_format exynos5_format_to_s3c_format(int format) 218{ 219 switch (format) { 220 case HAL_PIXEL_FORMAT_RGBA_8888: 221 return S3C_FB_PIXEL_FORMAT_RGBA_8888; 222 case HAL_PIXEL_FORMAT_RGBX_8888: 223 return S3C_FB_PIXEL_FORMAT_RGBX_8888; 224 case HAL_PIXEL_FORMAT_RGBA_5551: 225 return S3C_FB_PIXEL_FORMAT_RGBA_5551; 226 227 default: 228 return S3C_FB_PIXEL_FORMAT_MAX; 229 } 230} 231 232static bool exynos5_format_is_supported(int format) 233{ 234 return exynos5_format_to_s3c_format(format) < S3C_FB_PIXEL_FORMAT_MAX; 235} 236 237static bool exynos5_format_is_rgb(int format) 238{ 239 switch (format) { 240 case HAL_PIXEL_FORMAT_RGBA_8888: 241 case HAL_PIXEL_FORMAT_RGBX_8888: 242 case HAL_PIXEL_FORMAT_RGB_888: 243 case HAL_PIXEL_FORMAT_RGB_565: 244 case HAL_PIXEL_FORMAT_BGRA_8888: 245 case HAL_PIXEL_FORMAT_RGBA_5551: 246 case HAL_PIXEL_FORMAT_RGBA_4444: 247 return true; 248 249 default: 250 return false; 251 } 252} 253 254static bool exynos5_format_is_supported_by_gscaler(int format) 255{ 256 switch (format) { 257 case HAL_PIXEL_FORMAT_RGBX_8888: 258 case HAL_PIXEL_FORMAT_RGB_565: 259 case HAL_PIXEL_FORMAT_EXYNOS_YV12: 260 case HAL_PIXEL_FORMAT_YCbCr_420_SP: 261 case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED: 262 return true; 263 264 default: 265 return false; 266 } 267} 268 269static bool exynos5_format_is_ycrcb(int format) 270{ 271 return format == HAL_PIXEL_FORMAT_EXYNOS_YV12; 272} 273 274static bool exynos5_format_requires_gscaler(int format) 275{ 276 return exynos5_format_is_supported_by_gscaler(format) && 277 format != HAL_PIXEL_FORMAT_RGBX_8888; 278} 279 280static uint8_t exynos5_format_to_bpp(int format) 281{ 282 switch (format) { 283 case HAL_PIXEL_FORMAT_RGBA_8888: 284 case HAL_PIXEL_FORMAT_RGBX_8888: 285 return 32; 286 287 case HAL_PIXEL_FORMAT_RGBA_5551: 288 case HAL_PIXEL_FORMAT_RGBA_4444: 289 return 16; 290 291 default: 292 ALOGW("unrecognized pixel format %u", format); 293 return 0; 294 } 295} 296 297static bool exynos5_supports_gscaler(hwc_layer_1_t &layer, int format, 298 bool local_path) 299{ 300 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 301 302 int max_w = is_rotated(layer) ? 2048 : 4800; 303 int max_h = is_rotated(layer) ? 2048 : 3344; 304 305 bool rot90or270 = !!(layer.transform & HAL_TRANSFORM_ROT_90); 306 // n.b.: HAL_TRANSFORM_ROT_270 = HAL_TRANSFORM_ROT_90 | 307 // HAL_TRANSFORM_ROT_180 308 309 int src_w = WIDTH(layer.sourceCrop), src_h = HEIGHT(layer.sourceCrop); 310 int dest_w, dest_h; 311 if (rot90or270) { 312 dest_w = HEIGHT(layer.displayFrame); 313 dest_h = WIDTH(layer.displayFrame); 314 } else { 315 dest_w = WIDTH(layer.displayFrame); 316 dest_h = HEIGHT(layer.displayFrame); 317 } 318 int max_downscale = local_path ? 4 : 16; 319 const int max_upscale = 8; 320 321 return exynos5_format_is_supported_by_gscaler(format) && 322 handle->stride <= max_w && 323 handle->stride % GSC_W_ALIGNMENT == 0 && 324 src_w <= dest_w * max_downscale && 325 dest_w <= src_w * max_upscale && 326 handle->vstride <= max_h && 327 handle->vstride % GSC_H_ALIGNMENT == 0 && 328 src_h <= dest_h * max_downscale && 329 dest_h <= src_h * max_upscale && 330 // per 46.2 331 (!rot90or270 || layer.sourceCrop.top % 2 == 0) && 332 (!rot90or270 || layer.sourceCrop.left % 2 == 0); 333 // per 46.3.1.6 334} 335 336int hdmi_get_config(struct exynos5_hwc_composer_device_1_t *dev) 337{ 338 struct v4l2_dv_preset preset; 339 struct v4l2_dv_enum_preset enum_preset; 340 int index = 0; 341 bool found = false; 342 int ret; 343 344 if (ioctl(dev->hdmi_layer0, VIDIOC_G_DV_PRESET, &preset) < 0) { 345 ALOGE("%s: g_dv_preset error, %d", __func__, errno); 346 return -1; 347 } 348 349 while (true) { 350 enum_preset.index = index++; 351 ret = ioctl(dev->hdmi_layer0, VIDIOC_ENUM_DV_PRESETS, &enum_preset); 352 353 if (ret < 0) { 354 if (errno == EINVAL) 355 break; 356 ALOGE("%s: enum_dv_presets error, %d", __func__, errno); 357 return -1; 358 } 359 360 ALOGV("%s: %d preset=%02d width=%d height=%d name=%s", 361 __func__, enum_preset.index, enum_preset.preset, 362 enum_preset.width, enum_preset.height, enum_preset.name); 363 364 if (preset.preset == enum_preset.preset) { 365 dev->hdmi_w = enum_preset.width; 366 dev->hdmi_h = enum_preset.height; 367 found = true; 368 } 369 } 370 371 return found ? 0 : -1; 372} 373 374static enum s3c_fb_blending exynos5_blending_to_s3c_blending(int32_t blending) 375{ 376 switch (blending) { 377 case HWC_BLENDING_NONE: 378 return S3C_FB_BLENDING_NONE; 379 case HWC_BLENDING_PREMULT: 380 return S3C_FB_BLENDING_PREMULT; 381 case HWC_BLENDING_COVERAGE: 382 return S3C_FB_BLENDING_COVERAGE; 383 384 default: 385 return S3C_FB_BLENDING_MAX; 386 } 387} 388 389static bool exynos5_blending_is_supported(int32_t blending) 390{ 391 return exynos5_blending_to_s3c_blending(blending) < S3C_FB_BLENDING_MAX; 392} 393 394static int hdmi_start_background(struct exynos5_hwc_composer_device_1_t *dev) 395{ 396 struct v4l2_requestbuffers reqbuf; 397 struct v4l2_subdev_format sd_fmt; 398 struct v4l2_subdev_crop sd_crop; 399 struct v4l2_format fmt; 400 struct v4l2_buffer buffer; 401 struct v4l2_plane planes[1]; 402 403 memset(&reqbuf, 0, sizeof(reqbuf)); 404 memset(&sd_fmt, 0, sizeof(sd_fmt)); 405 memset(&sd_crop, 0, sizeof(sd_crop)); 406 memset(&fmt, 0, sizeof(fmt)); 407 memset(&buffer, 0, sizeof(buffer)); 408 memset(planes, 0, sizeof(planes)); 409 410 sd_fmt.pad = MIXER_G1_SUBDEV_PAD_SINK; 411 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 412 sd_fmt.format.width = 1; 413 sd_fmt.format.height = 1; 414 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 415 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 416 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 417 return -1; 418 } 419 420 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SINK; 421 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 422 sd_crop.rect.left = 0; 423 sd_crop.rect.top = 0; 424 sd_crop.rect.width = 1; 425 sd_crop.rect.height = 1; 426 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 427 ALOGE("%s: set_crop failed pad=%d", __func__, sd_crop.pad); 428 return -1; 429 } 430 431 sd_fmt.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 432 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 433 sd_fmt.format.width = dev->hdmi_w; 434 sd_fmt.format.height = dev->hdmi_h; 435 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 436 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 437 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 438 return -1; 439 } 440 441 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 442 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 443 sd_crop.rect.left = 0; 444 sd_crop.rect.top = 0; 445 sd_crop.rect.width = 1; 446 sd_crop.rect.height = 1; 447 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 448 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 449 return -1; 450 } 451 452 fmt.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 453 fmt.fmt.pix_mp.width = 1; 454 fmt.fmt.pix_mp.height = 1; 455 fmt.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_BGR32; 456 fmt.fmt.pix_mp.field = V4L2_FIELD_ANY; 457 fmt.fmt.pix_mp.num_planes = 1; 458 if (exynos_v4l2_s_fmt(dev->hdmi_layer1, &fmt) < 0) { 459 ALOGE("%s::videodev set format failed", __func__); 460 return -1; 461 } 462 463 reqbuf.count = 1; 464 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 465 reqbuf.memory = V4L2_MEMORY_MMAP; 466 467 if (exynos_v4l2_reqbufs(dev->hdmi_layer1, &reqbuf) < 0) { 468 ALOGE("%s: exynos_v4l2_reqbufs failed %d", __func__, errno); 469 return -1; 470 } 471 472 if (reqbuf.count != 1) { 473 ALOGE("%s: didn't get buffer", __func__); 474 return -1; 475 } 476 477 memset(&buffer, 0, sizeof(buffer)); 478 buffer.type = reqbuf.type; 479 buffer.memory = V4L2_MEMORY_MMAP; 480 buffer.length = 1; 481 buffer.m.planes = planes; 482 if (exynos_v4l2_querybuf(dev->hdmi_layer1, &buffer) < 0) { 483 ALOGE("%s: exynos_v4l2_querybuf failed %d", __func__, errno); 484 return -1; 485 } 486 487 void *start = mmap(NULL, planes[0].length, PROT_READ | PROT_WRITE, 488 MAP_SHARED, dev->hdmi_layer1, planes[0].m.mem_offset); 489 if (start == MAP_FAILED) { 490 ALOGE("%s: mmap failed %d", __func__, errno); 491 return -1; 492 } 493 494 memset(start, 0, planes[0].length); 495 496 munmap(start, planes[0].length); 497 498 if (exynos_v4l2_qbuf(dev->hdmi_layer1, &buffer) < 0) { 499 ALOGE("%s: exynos_v4l2_qbuf failed %d", __func__, errno); 500 return -1; 501 } 502 503 if (exynos_v4l2_streamon(dev->hdmi_layer1, buffer.type) < 0) { 504 ALOGE("%s:stream on failed", __func__); 505 return -1; 506 } 507 508 if (exynos_v4l2_s_ctrl(dev->hdmi_layer1, V4L2_CID_TV_LAYER_PRIO, 0) < 0) { 509 ALOGE("%s: s_ctrl LAYER_PRIO failed", __func__); 510 return -1; 511 } 512 513 return 0; 514} 515 516static int hdmi_stop_background(struct exynos5_hwc_composer_device_1_t *dev) 517{ 518 struct v4l2_requestbuffers reqbuf; 519 520 if (exynos_v4l2_streamoff(dev->hdmi_layer1, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) < 0) { 521 ALOGE("%s:stream off failed", __func__); 522 return -1; 523 } 524 525 memset(&reqbuf, 0, sizeof(reqbuf)); 526 reqbuf.count = 0; 527 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 528 reqbuf.memory = V4L2_MEMORY_MMAP; 529 if (exynos_v4l2_reqbufs(dev->hdmi_layer1, &reqbuf) < 0) { 530 ALOGE("%s: exynos_v4l2_reqbufs failed %d", __func__, errno); 531 return -1; 532 } 533 534 return 0; 535} 536 537static int hdmi_enable(struct exynos5_hwc_composer_device_1_t *dev) 538{ 539 if (dev->hdmi_enabled) 540 return 0; 541 542 if (dev->hdmi_blanked) 543 return 0; 544 545 dev->hdmi_gsc = exynos_gsc_create_exclusive(3, GSC_OUTPUT_MODE, GSC_OUT_TV); 546 if (!dev->hdmi_gsc) { 547 ALOGE("%s: exynos_gsc_create_exclusive failed", __func__); 548 return -ENODEV; 549 } 550 551 memset(&dev->hdmi_src, 0, sizeof(dev->hdmi_src)); 552 553 if (hdmi_start_background(dev) < 0) { 554 ALOGE("%s: hdmi_start_background failed", __func__); 555 return -1; 556 } 557 558 dev->hdmi_enabled = true; 559 return 0; 560} 561 562static void hdmi_disable(struct exynos5_hwc_composer_device_1_t *dev) 563{ 564 if (!dev->hdmi_enabled) 565 return; 566 exynos_gsc_destroy(dev->hdmi_gsc); 567 hdmi_stop_background(dev); 568 dev->hdmi_gsc = NULL; 569 dev->hdmi_enabled = false; 570} 571 572static int hdmi_configure(struct exynos5_hwc_composer_device_1_t *dev, 573 exynos_gsc_img &src_cfg, 574 exynos_gsc_img &dst_cfg) 575{ 576 if (!gsc_src_cfg_changed(src_cfg, dev->hdmi_src) 577 && !gsc_dst_cfg_changed(dst_cfg, dev->hdmi_dst)) 578 return 0; 579 580 ALOGV("HDMI source config:"); 581 dump_gsc_img(src_cfg); 582 ALOGV("HDMI dest config:"); 583 dump_gsc_img(dst_cfg); 584 585 exynos_gsc_stop_exclusive(dev->hdmi_gsc); 586 587 int ret = exynos_gsc_config_exclusive(dev->hdmi_gsc, &src_cfg, &dst_cfg); 588 if (ret < 0) { 589 ALOGE("%s: exynos_gsc_config_exclusive failed %d", __func__, ret); 590 return ret; 591 } 592 593 dev->hdmi_src = src_cfg; 594 dev->hdmi_dst = dst_cfg; 595 return ret; 596} 597 598static int hdmi_configure_handle(struct exynos5_hwc_composer_device_1_t *dev, private_handle_t *h) 599{ 600 exynos_gsc_img src_cfg, dst_cfg; 601 memset(&src_cfg, 0, sizeof(src_cfg)); 602 memset(&dst_cfg, 0, sizeof(dst_cfg)); 603 604 src_cfg.w = src_cfg.fw = h->width; 605 src_cfg.h = src_cfg.fh = h->height; 606 src_cfg.format = HAL_PIXEL_FORMAT_BGRA_8888; 607 608 dst_cfg.w = dst_cfg.fw = dev->hdmi_w; 609 dst_cfg.h = dst_cfg.fh = dev->hdmi_h; 610 dst_cfg.format = HAL_PIXEL_FORMAT_EXYNOS_YV12; 611 612 return hdmi_configure(dev, src_cfg, dst_cfg); 613} 614 615static int hdmi_configure_layer(struct exynos5_hwc_composer_device_1_t *dev, hwc_layer_1_t &layer) 616{ 617 exynos_gsc_img src_cfg, dst_cfg; 618 memset(&src_cfg, 0, sizeof(src_cfg)); 619 memset(&dst_cfg, 0, sizeof(dst_cfg)); 620 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle); 621 622 src_cfg.x = layer.sourceCrop.left; 623 src_cfg.y = layer.sourceCrop.top; 624 src_cfg.w = WIDTH(layer.sourceCrop); 625 src_cfg.fw = src_handle->stride; 626 src_cfg.h = HEIGHT(layer.sourceCrop); 627 src_cfg.fh = src_handle->vstride; 628 src_cfg.format = src_handle->format; 629 630 if (dev->hdmi_w * src_cfg.h < dev->hdmi_h * src_cfg.w) { 631 dst_cfg.w = dev->hdmi_w; 632 dst_cfg.fw = dev->hdmi_w; 633 dst_cfg.fh = dev->hdmi_h; 634 dst_cfg.h = dev->hdmi_w * src_cfg.h / src_cfg.w; 635 dst_cfg.y = (dev->hdmi_h - dst_cfg.h) / 2; 636 } 637 else { 638 dst_cfg.w = dev->hdmi_h * src_cfg.w / src_cfg.h; 639 dst_cfg.fw = dev->hdmi_w; 640 dst_cfg.h = dev->hdmi_h; 641 dst_cfg.fh = dev->hdmi_h; 642 dst_cfg.x = (dev->hdmi_w - dst_cfg.w) / 2; 643 } 644 dst_cfg.format = HAL_PIXEL_FORMAT_EXYNOS_YV12; 645 dst_cfg.rot = layer.transform; 646 647 return hdmi_configure(dev, src_cfg, dst_cfg); 648} 649 650static int hdmi_output(struct exynos5_hwc_composer_device_1_t *dev, private_handle_t *h) 651{ 652 exynos_gsc_img src_info; 653 exynos_gsc_img dst_info; 654 655 memset(&src_info, 0, sizeof(src_info)); 656 memset(&dst_info, 0, sizeof(dst_info)); 657 658 src_info.yaddr = h->fd; 659 if (exynos5_format_is_ycrcb(h->format)) { 660 src_info.uaddr = h->fd2; 661 src_info.vaddr = h->fd1; 662 } else { 663 src_info.uaddr = h->fd1; 664 src_info.vaddr = h->fd2; 665 } 666 667 int ret = exynos_gsc_run_exclusive(dev->hdmi_gsc, &src_info, &dst_info); 668 if (ret < 0) { 669 ALOGE("%s: exynos_gsc_run_exclusive failed %d", __func__, ret); 670 return ret; 671 } 672 673 return 0; 674} 675 676bool exynos5_is_offscreen(hwc_layer_1_t &layer, 677 struct exynos5_hwc_composer_device_1_t *pdev) 678{ 679 return layer.sourceCrop.left > pdev->xres || 680 layer.sourceCrop.right < 0 || 681 layer.sourceCrop.top > pdev->yres || 682 layer.sourceCrop.bottom < 0; 683} 684 685bool exynos5_supports_overlay(hwc_layer_1_t &layer, size_t i, 686 struct exynos5_hwc_composer_device_1_t *pdev) 687{ 688 if (layer.flags & HWC_SKIP_LAYER) { 689 ALOGV("\tlayer %u: skipping", i); 690 return false; 691 } 692 693 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 694 695 if (!handle) { 696 ALOGV("\tlayer %u: handle is NULL", i); 697 return false; 698 } 699 if (!exynos5_format_is_rgb(handle->format) && 700 !exynos5_format_is_supported_by_gscaler(handle->format)) { 701 ALOGW("\tlayer %u: unexpected format %u", i, handle->format); 702 return false; 703 } 704 705 if (exynos5_format_requires_gscaler(handle->format)) { 706 if (!exynos5_supports_gscaler(layer, handle->format, false)) { 707 ALOGV("\tlayer %u: gscaler required but not supported", i); 708 return false; 709 } 710 } else { 711 if (!exynos5_format_is_supported(handle->format)) { 712 ALOGV("\tlayer %u: pixel format %u not supported", i, handle->format); 713 return false; 714 } 715 if (is_scaled(layer)) { 716 ALOGV("\tlayer %u: scaling not supported", i); 717 return false; 718 } 719 if (is_transformed(layer)) { 720 ALOGV("\tlayer %u: transformations not supported", i); 721 return false; 722 } 723 } 724 if (!exynos5_blending_is_supported(layer.blending)) { 725 ALOGV("\tlayer %u: blending %d not supported", i, layer.blending); 726 return false; 727 } 728 if (CC_UNLIKELY(exynos5_is_offscreen(layer, pdev))) { 729 ALOGW("\tlayer %u: off-screen", i); 730 return false; 731 } 732 733 return true; 734} 735 736inline bool intersect(const hwc_rect &r1, const hwc_rect &r2) 737{ 738 return !(r1.left > r2.right || 739 r1.right < r2.left || 740 r1.top > r2.bottom || 741 r1.bottom < r2.top); 742} 743 744inline hwc_rect intersection(const hwc_rect &r1, const hwc_rect &r2) 745{ 746 hwc_rect i; 747 i.top = max(r1.top, r2.top); 748 i.bottom = min(r1.bottom, r2.bottom); 749 i.left = max(r1.left, r2.left); 750 i.right = min(r1.right, r2.right); 751 return i; 752} 753 754static int exynos5_prepare_fimd(exynos5_hwc_composer_device_1_t *pdev, 755 hwc_display_contents_1_t* contents, bool force_fb) 756{ 757 ALOGV("preparing %u layers for FIMD", contents->numHwLayers); 758 759 memset(pdev->bufs.gsc_map, 0, sizeof(pdev->bufs.gsc_map)); 760 761 force_fb = force_fb || pdev->force_gpu; 762 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 763 pdev->bufs.overlay_map[i] = -1; 764 765 bool fb_needed = false; 766 size_t first_fb = 0, last_fb = 0; 767 768 // find unsupported overlays 769 for (size_t i = 0; i < contents->numHwLayers; i++) { 770 hwc_layer_1_t &layer = contents->hwLayers[i]; 771 772 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 773 ALOGV("\tlayer %u: framebuffer target", i); 774 continue; 775 } 776 777 if (layer.compositionType == HWC_BACKGROUND && !force_fb) { 778 ALOGV("\tlayer %u: background supported", i); 779 dump_layer(&contents->hwLayers[i]); 780 continue; 781 } 782 783 if (exynos5_supports_overlay(contents->hwLayers[i], i, pdev) && 784 !force_fb) { 785 ALOGV("\tlayer %u: overlay supported", i); 786 layer.compositionType = HWC_OVERLAY; 787 dump_layer(&contents->hwLayers[i]); 788 continue; 789 } 790 791 if (!fb_needed) { 792 first_fb = i; 793 fb_needed = true; 794 } 795 last_fb = i; 796 layer.compositionType = HWC_FRAMEBUFFER; 797 798 dump_layer(&contents->hwLayers[i]); 799 } 800 801 // can't composite overlays sandwiched between framebuffers 802 if (fb_needed) 803 for (size_t i = first_fb; i < last_fb; i++) 804 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 805 806 // Incrementally try to add our supported layers to hardware windows. 807 // If adding a layer would violate a hardware constraint, force it 808 // into the framebuffer and try again. (Revisiting the entire list is 809 // necessary because adding a layer to the framebuffer can cause other 810 // windows to retroactively violate constraints.) 811 bool changed; 812 do { 813 android::Vector<hwc_rect> rects; 814 android::Vector<hwc_rect> overlaps; 815 size_t pixels_left, windows_left, gsc_left = NUM_GSC_UNITS; 816 817 if (fb_needed) { 818 hwc_rect_t fb_rect; 819 fb_rect.top = fb_rect.left = 0; 820 fb_rect.right = pdev->xres - 1; 821 fb_rect.bottom = pdev->yres - 1; 822 pixels_left = MAX_PIXELS - pdev->xres * pdev->yres; 823 windows_left = NUM_HW_WINDOWS - 1; 824 rects.push_back(fb_rect); 825 } 826 else { 827 pixels_left = MAX_PIXELS; 828 windows_left = NUM_HW_WINDOWS; 829 } 830 if (pdev->hdmi_enabled) 831 gsc_left--; 832 833 changed = false; 834 835 for (size_t i = 0; i < contents->numHwLayers; i++) { 836 hwc_layer_1_t &layer = contents->hwLayers[i]; 837 if ((layer.flags & HWC_SKIP_LAYER) || 838 layer.compositionType == HWC_FRAMEBUFFER_TARGET) 839 continue; 840 841 private_handle_t *handle = private_handle_t::dynamicCast( 842 layer.handle); 843 844 // we've already accounted for the framebuffer above 845 if (layer.compositionType == HWC_FRAMEBUFFER) 846 continue; 847 848 // only layer 0 can be HWC_BACKGROUND, so we can 849 // unconditionally allow it without extra checks 850 if (layer.compositionType == HWC_BACKGROUND) { 851 windows_left--; 852 continue; 853 } 854 855 size_t pixels_needed = WIDTH(layer.displayFrame) * 856 HEIGHT(layer.displayFrame); 857 bool can_compose = windows_left && pixels_needed <= pixels_left; 858 bool gsc_required = exynos5_format_requires_gscaler(handle->format); 859 if (gsc_required) 860 can_compose = can_compose && gsc_left; 861 862 // hwc_rect_t right and bottom values are normally exclusive; 863 // the intersection logic is simpler if we make them inclusive 864 hwc_rect_t visible_rect = layer.displayFrame; 865 visible_rect.right--; visible_rect.bottom--; 866 867 // no more than 2 layers can overlap on a given pixel 868 for (size_t j = 0; can_compose && j < overlaps.size(); j++) { 869 if (intersect(visible_rect, overlaps.itemAt(j))) 870 can_compose = false; 871 } 872 873 if (!can_compose) { 874 layer.compositionType = HWC_FRAMEBUFFER; 875 if (!fb_needed) { 876 first_fb = last_fb = i; 877 fb_needed = true; 878 } 879 else { 880 first_fb = min(i, first_fb); 881 last_fb = max(i, last_fb); 882 } 883 changed = true; 884 break; 885 } 886 887 for (size_t j = 0; j < rects.size(); j++) { 888 const hwc_rect_t &other_rect = rects.itemAt(j); 889 if (intersect(visible_rect, other_rect)) 890 overlaps.push_back(intersection(visible_rect, other_rect)); 891 } 892 rects.push_back(visible_rect); 893 pixels_left -= pixels_needed; 894 windows_left--; 895 if (gsc_required) 896 gsc_left--; 897 } 898 899 if (changed) 900 for (size_t i = first_fb; i < last_fb; i++) 901 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 902 } while(changed); 903 904 unsigned int nextWindow = 0; 905 int nextGsc = 0; 906 907 for (size_t i = 0; i < contents->numHwLayers; i++) { 908 hwc_layer_1_t &layer = contents->hwLayers[i]; 909 910 if (fb_needed && i == first_fb) { 911 ALOGV("assigning framebuffer to window %u\n", 912 nextWindow); 913 nextWindow++; 914 continue; 915 } 916 917 if (layer.compositionType != HWC_FRAMEBUFFER && 918 layer.compositionType != HWC_FRAMEBUFFER_TARGET) { 919 ALOGV("assigning layer %u to window %u", i, nextWindow); 920 pdev->bufs.overlay_map[nextWindow] = i; 921 if (layer.compositionType == HWC_OVERLAY) { 922 private_handle_t *handle = 923 private_handle_t::dynamicCast(layer.handle); 924 if (exynos5_format_requires_gscaler(handle->format)) { 925 ALOGV("\tusing gscaler %u", AVAILABLE_GSC_UNITS[nextGsc]); 926 pdev->bufs.gsc_map[nextWindow].mode = 927 exynos5_gsc_map_t::GSC_M2M; 928 pdev->bufs.gsc_map[nextWindow].idx = nextGsc++; 929 } 930 } 931 nextWindow++; 932 } 933 } 934 935 for (size_t i = nextGsc; i < NUM_GSC_UNITS; i++) { 936 for (size_t j = 0; j < NUM_GSC_DST_BUFS; j++) 937 if (pdev->gsc[i].dst_buf[j]) 938 pdev->alloc_device->free(pdev->alloc_device, 939 pdev->gsc[i].dst_buf[j]); 940 memset(&pdev->gsc[i], 0, sizeof(pdev->gsc[i])); 941 } 942 943 if (fb_needed) 944 pdev->bufs.fb_window = first_fb; 945 else 946 pdev->bufs.fb_window = NO_FB_NEEDED; 947 948 return 0; 949} 950 951static int exynos5_prepare_hdmi(exynos5_hwc_composer_device_1_t *pdev, 952 hwc_display_contents_1_t* contents) 953{ 954 ALOGE("exynos5_prepare_hdmi() not implemented"); 955 return -EINVAL; 956} 957 958static int exynos5_prepare(hwc_composer_device_1_t *dev, 959 size_t numDisplays, hwc_display_contents_1_t** displays) 960{ 961 if (!numDisplays || !displays) 962 return 0; 963 964 exynos5_hwc_composer_device_1_t *pdev = 965 (exynos5_hwc_composer_device_1_t *)dev; 966 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 967 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 968 969 if (pdev->hdmi_hpd) { 970 hdmi_enable(pdev); 971 } else { 972 hdmi_disable(pdev); 973 } 974 975 if (fimd_contents) { 976 bool force_fb = pdev->hdmi_enabled && !hdmi_contents; 977 int err = exynos5_prepare_fimd(pdev, fimd_contents, force_fb); 978 if (err) 979 return err; 980 } 981 982 if (hdmi_contents) { 983 if (!pdev->hdmi_enabled) { 984 ALOGE("HDMI disabled; can't prepare contents of external display"); 985 return -EINVAL; 986 } 987 int err = exynos5_prepare_hdmi(pdev, hdmi_contents); 988 if (err) 989 return err; 990 } 991 992 return 0; 993} 994 995static int exynos5_config_gsc_m2m(hwc_layer_1_t &layer, 996 alloc_device_t* alloc_device, exynos5_gsc_data_t *gsc_data, 997 int gsc_idx) 998{ 999 ALOGV("configuring gscaler %u for memory-to-memory", gsc_idx); 1000 1001 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle); 1002 buffer_handle_t dst_buf; 1003 private_handle_t *dst_handle; 1004 int ret = 0; 1005 1006 exynos_gsc_img src_cfg, dst_cfg; 1007 memset(&src_cfg, 0, sizeof(src_cfg)); 1008 memset(&dst_cfg, 0, sizeof(dst_cfg)); 1009 1010 src_cfg.x = layer.sourceCrop.left; 1011 src_cfg.y = layer.sourceCrop.top; 1012 src_cfg.w = WIDTH(layer.sourceCrop); 1013 src_cfg.fw = src_handle->stride; 1014 src_cfg.h = HEIGHT(layer.sourceCrop); 1015 src_cfg.fh = src_handle->vstride; 1016 src_cfg.yaddr = src_handle->fd; 1017 if (exynos5_format_is_ycrcb(src_handle->format)) { 1018 src_cfg.uaddr = src_handle->fd2; 1019 src_cfg.vaddr = src_handle->fd1; 1020 } else { 1021 src_cfg.uaddr = src_handle->fd1; 1022 src_cfg.vaddr = src_handle->fd2; 1023 } 1024 src_cfg.format = src_handle->format; 1025 src_cfg.drmMode = !!(src_handle->flags & GRALLOC_USAGE_PROTECTED); 1026 1027 dst_cfg.x = 0; 1028 dst_cfg.y = 0; 1029 dst_cfg.w = WIDTH(layer.displayFrame); 1030 dst_cfg.h = HEIGHT(layer.displayFrame); 1031 dst_cfg.format = HAL_PIXEL_FORMAT_BGRA_8888; 1032 dst_cfg.rot = layer.transform; 1033 dst_cfg.drmMode = src_cfg.drmMode; 1034 1035 ALOGV("source configuration:"); 1036 dump_gsc_img(src_cfg); 1037 1038 if (gsc_src_cfg_changed(src_cfg, gsc_data->src_cfg) || 1039 gsc_dst_cfg_changed(dst_cfg, gsc_data->dst_cfg)) { 1040 int dst_stride; 1041 int usage = GRALLOC_USAGE_SW_READ_NEVER | 1042 GRALLOC_USAGE_SW_WRITE_NEVER | 1043 GRALLOC_USAGE_HW_COMPOSER; 1044 1045 if (src_handle->flags & GRALLOC_USAGE_PROTECTED) 1046 usage |= GRALLOC_USAGE_PROTECTED; 1047 1048 int w = ALIGN(WIDTH(layer.displayFrame), GSC_W_ALIGNMENT); 1049 int h = ALIGN(HEIGHT(layer.displayFrame), GSC_H_ALIGNMENT); 1050 1051 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1052 if (gsc_data->dst_buf[i]) { 1053 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1054 gsc_data->dst_buf[i] = NULL; 1055 } 1056 1057 int ret = alloc_device->alloc(alloc_device, w, h, 1058 HAL_PIXEL_FORMAT_RGBX_8888, usage, &gsc_data->dst_buf[i], 1059 &dst_stride); 1060 if (ret < 0) { 1061 ALOGE("failed to allocate destination buffer: %s", 1062 strerror(-ret)); 1063 goto err_alloc; 1064 } 1065 } 1066 1067 gsc_data->current_buf = 0; 1068 } 1069 1070 dst_buf = gsc_data->dst_buf[gsc_data->current_buf]; 1071 dst_handle = private_handle_t::dynamicCast(dst_buf); 1072 1073 dst_cfg.fw = dst_handle->stride; 1074 dst_cfg.fh = dst_handle->vstride; 1075 dst_cfg.yaddr = dst_handle->fd; 1076 1077 ALOGV("destination configuration:"); 1078 dump_gsc_img(dst_cfg); 1079 1080 gsc_data->gsc = exynos_gsc_create_exclusive(AVAILABLE_GSC_UNITS[gsc_idx], 1081 GSC_M2M_MODE, GSC_DUMMY); 1082 if (!gsc_data->gsc) { 1083 ALOGE("failed to create gscaler handle"); 1084 ret = -1; 1085 goto err_alloc; 1086 } 1087 1088 ret = exynos_gsc_config_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1089 if (ret < 0) { 1090 ALOGE("failed to configure gscaler %u", gsc_idx); 1091 goto err_gsc_config; 1092 } 1093 1094 ret = exynos_gsc_run_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1095 if (ret < 0) { 1096 ALOGE("failed to run gscaler %u", gsc_idx); 1097 goto err_gsc_config; 1098 } 1099 1100 gsc_data->src_cfg = src_cfg; 1101 gsc_data->dst_cfg = dst_cfg; 1102 1103 return 0; 1104 1105err_gsc_config: 1106 exynos_gsc_destroy(gsc_data->gsc); 1107 gsc_data->gsc = NULL; 1108err_alloc: 1109 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1110 if (gsc_data->dst_buf[i]) { 1111 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1112 gsc_data->dst_buf[i] = NULL; 1113 } 1114 } 1115 memset(&gsc_data->src_cfg, 0, sizeof(gsc_data->src_cfg)); 1116 memset(&gsc_data->dst_cfg, 0, sizeof(gsc_data->dst_cfg)); 1117 return ret; 1118} 1119 1120static void exynos5_config_handle(private_handle_t *handle, 1121 hwc_rect_t &sourceCrop, hwc_rect_t &displayFrame, 1122 int32_t blending, s3c_fb_win_config &cfg, 1123 exynos5_hwc_composer_device_1_t *pdev) 1124{ 1125 uint32_t x, y; 1126 uint32_t w = WIDTH(displayFrame); 1127 uint32_t h = HEIGHT(displayFrame); 1128 uint8_t bpp = exynos5_format_to_bpp(handle->format); 1129 uint32_t offset = (sourceCrop.top * handle->stride + sourceCrop.left) * bpp / 8; 1130 1131 if (displayFrame.left < 0) { 1132 unsigned int crop = -displayFrame.left; 1133 ALOGV("layer off left side of screen; cropping %u pixels from left edge", 1134 crop); 1135 x = 0; 1136 w -= crop; 1137 offset += crop * bpp / 8; 1138 } else { 1139 x = displayFrame.left; 1140 } 1141 1142 if (displayFrame.right > pdev->xres) { 1143 unsigned int crop = displayFrame.right - pdev->xres; 1144 ALOGV("layer off right side of screen; cropping %u pixels from right edge", 1145 crop); 1146 w -= crop; 1147 } 1148 1149 if (displayFrame.top < 0) { 1150 unsigned int crop = -displayFrame.top; 1151 ALOGV("layer off top side of screen; cropping %u pixels from top edge", 1152 crop); 1153 y = 0; 1154 h -= crop; 1155 offset += handle->stride * crop * bpp / 8; 1156 } else { 1157 y = displayFrame.top; 1158 } 1159 1160 if (displayFrame.bottom > pdev->yres) { 1161 int crop = displayFrame.bottom - pdev->yres; 1162 ALOGV("layer off bottom side of screen; cropping %u pixels from bottom edge", 1163 crop); 1164 h -= crop; 1165 } 1166 1167 cfg.state = cfg.S3C_FB_WIN_STATE_BUFFER; 1168 cfg.fd = handle->fd; 1169 cfg.x = x; 1170 cfg.y = y; 1171 cfg.w = w; 1172 cfg.h = h; 1173 cfg.format = exynos5_format_to_s3c_format(handle->format); 1174 cfg.offset = offset; 1175 cfg.stride = handle->stride * bpp / 8; 1176 cfg.blending = exynos5_blending_to_s3c_blending(blending); 1177} 1178 1179static void exynos5_config_overlay(hwc_layer_1_t *layer, s3c_fb_win_config &cfg, 1180 exynos5_hwc_composer_device_1_t *pdev) 1181{ 1182 if (layer->compositionType == HWC_BACKGROUND) { 1183 hwc_color_t color = layer->backgroundColor; 1184 cfg.state = cfg.S3C_FB_WIN_STATE_COLOR; 1185 cfg.color = (color.r << 16) | (color.g << 8) | color.b; 1186 cfg.x = 0; 1187 cfg.y = 0; 1188 cfg.w = pdev->xres; 1189 cfg.h = pdev->yres; 1190 return; 1191 } 1192 1193 private_handle_t *handle = private_handle_t::dynamicCast(layer->handle); 1194 exynos5_config_handle(handle, layer->sourceCrop, layer->displayFrame, 1195 layer->blending, cfg, pdev); 1196} 1197 1198static int exynos5_post_fimd(exynos5_hwc_composer_device_1_t *pdev, 1199 hwc_display_contents_1_t* contents, hwc_layer_1_t *fb_layer, 1200 bool hdmi_mirroring) 1201{ 1202 exynos5_hwc_post_data_t *pdata = &pdev->bufs; 1203 struct s3c_fb_win_config_data win_data; 1204 struct s3c_fb_win_config *config = win_data.config; 1205 memset(config, 0, sizeof(win_data.config)); 1206 1207 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1208 int layer_idx = pdata->overlay_map[i]; 1209 if (layer_idx != -1) { 1210 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1211 1212 if (layer.acquireFenceFd != -1) { 1213 int err = sync_wait(layer.acquireFenceFd, 100); 1214 if (err != 0) 1215 ALOGW("fence for layer %zu didn't signal in 100 ms: %s", 1216 i, strerror(errno)); 1217 close(layer.acquireFenceFd); 1218 } 1219 1220 if (pdata->gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) { 1221 int gsc_idx = pdata->gsc_map[i].idx; 1222 exynos5_config_gsc_m2m(layer, pdev->alloc_device, 1223 &pdev->gsc[gsc_idx], gsc_idx); 1224 } 1225 } 1226 } 1227 1228 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1229 int layer_idx = pdata->overlay_map[i]; 1230 if (layer_idx != -1) { 1231 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1232 private_handle_t *handle = 1233 private_handle_t::dynamicCast(layer.handle); 1234 1235 if (pdata->gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) { 1236 int gsc_idx = pdata->gsc_map[i].idx; 1237 exynos5_gsc_data_t &gsc = pdev->gsc[gsc_idx]; 1238 1239 if (!gsc.gsc) { 1240 ALOGE("failed to queue gscaler %u input for layer %u", 1241 gsc_idx, i); 1242 continue; 1243 } 1244 1245 int err = exynos_gsc_stop_exclusive(gsc.gsc); 1246 exynos_gsc_destroy(gsc.gsc); 1247 gsc.gsc = NULL; 1248 if (err < 0) { 1249 ALOGE("failed to dequeue gscaler output for layer %u", i); 1250 continue; 1251 } 1252 1253 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1254 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1255 private_handle_t *dst_handle = 1256 private_handle_t::dynamicCast(dst_buf); 1257 hwc_rect_t sourceCrop = { 0, 0, 1258 WIDTH(layer.displayFrame), HEIGHT(layer.displayFrame) }; 1259 exynos5_config_handle(dst_handle, sourceCrop, 1260 layer.displayFrame, layer.blending, config[i], pdev); 1261 } else { 1262 exynos5_config_overlay(&layer, config[i], pdev); 1263 } 1264 } 1265 if (i == 0 && config[i].blending != S3C_FB_BLENDING_NONE) { 1266 ALOGV("blending not supported on window 0; forcing BLENDING_NONE"); 1267 config[i].blending = S3C_FB_BLENDING_NONE; 1268 } 1269 1270 ALOGV("window %u configuration:", i); 1271 dump_config(config[i]); 1272 } 1273 1274 int ret = ioctl(pdev->fd, S3CFB_WIN_CONFIG, &win_data); 1275 if (ret < 0) { 1276 ALOGE("ioctl S3CFB_WIN_CONFIG failed: %s", strerror(errno)); 1277 return ret; 1278 } 1279 1280 memcpy(pdev->last_config, &win_data.config, sizeof(win_data.config)); 1281 memcpy(pdev->last_gsc_map, pdata->gsc_map, sizeof(pdata->gsc_map)); 1282 pdev->last_fb_window = pdata->fb_window; 1283 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1284 int layer_idx = pdata->overlay_map[i]; 1285 if (layer_idx != -1) { 1286 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1287 pdev->last_handles[i] = layer.handle; 1288 } 1289 } 1290 1291 if (hdmi_mirroring) { 1292 private_handle_t *fb = private_handle_t::dynamicCast(fb_layer->handle); 1293 hdmi_configure_handle(pdev, fb); 1294 hdmi_output(pdev, fb); 1295 } 1296 1297 return win_data.fence; 1298} 1299 1300static int exynos5_set_fimd(exynos5_hwc_composer_device_1_t *pdev, 1301 hwc_display_contents_1_t* contents, bool hdmi_mirroring) 1302{ 1303 if (!contents->dpy || !contents->sur) 1304 return 0; 1305 1306 hwc_layer_1_t *fb_layer = NULL; 1307 1308 if (pdev->bufs.fb_window != NO_FB_NEEDED) { 1309 for (size_t i = 0; i < contents->numHwLayers; i++) { 1310 if (contents->hwLayers[i].compositionType == 1311 HWC_FRAMEBUFFER_TARGET) { 1312 pdev->bufs.overlay_map[pdev->bufs.fb_window] = i; 1313 fb_layer = &contents->hwLayers[i]; 1314 break; 1315 } 1316 } 1317 1318 if (CC_UNLIKELY(!fb_layer)) { 1319 ALOGE("framebuffer target expected, but not provided"); 1320 return -EINVAL; 1321 } 1322 1323 ALOGV("framebuffer target buffer:"); 1324 dump_layer(fb_layer); 1325 } 1326 1327 int fence = exynos5_post_fimd(pdev, contents, fb_layer, hdmi_mirroring); 1328 if (fence < 0) 1329 return fence; 1330 1331 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1332 if (pdev->bufs.overlay_map[i] != -1) { 1333 hwc_layer_1_t &layer = 1334 contents->hwLayers[pdev->bufs.overlay_map[i]]; 1335 int dup_fd = dup(fence); 1336 if (dup_fd < 0) 1337 ALOGW("release fence dup failed: %s", strerror(errno)); 1338 layer.releaseFenceFd = dup_fd; 1339 } 1340 } 1341 close(fence); 1342 1343 return 0; 1344} 1345 1346static int exynos5_set_hdmi(exynos5_hwc_composer_device_1_t *pdev, 1347 hwc_display_contents_1_t* contents) 1348{ 1349 ALOGE("exynos5_set_hdmi() not implemented"); 1350 return -EINVAL; 1351} 1352 1353static int exynos5_set(struct hwc_composer_device_1 *dev, 1354 size_t numDisplays, hwc_display_contents_1_t** displays) 1355{ 1356 if (!numDisplays || !displays) 1357 return 0; 1358 1359 exynos5_hwc_composer_device_1_t *pdev = 1360 (exynos5_hwc_composer_device_1_t *)dev; 1361 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 1362 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 1363 1364 if (fimd_contents) { 1365 bool hdmi_mirroring = pdev->hdmi_enabled && !hdmi_contents; 1366 int err = exynos5_set_fimd(pdev, fimd_contents, hdmi_mirroring); 1367 if (err) 1368 return err; 1369 } 1370 1371 if (hdmi_contents) { 1372 if (!pdev->hdmi_enabled) { 1373 ALOGE("HDMI disabled; can't set contents of external display"); 1374 return -EINVAL; 1375 } 1376 int err = exynos5_set_hdmi(pdev, hdmi_contents); 1377 if (err) 1378 return err; 1379 } 1380 1381 return 0; 1382} 1383 1384static void exynos5_registerProcs(struct hwc_composer_device_1* dev, 1385 hwc_procs_t const* procs) 1386{ 1387 struct exynos5_hwc_composer_device_1_t* pdev = 1388 (struct exynos5_hwc_composer_device_1_t*)dev; 1389 pdev->procs = procs; 1390} 1391 1392static int exynos5_query(struct hwc_composer_device_1* dev, int what, int *value) 1393{ 1394 struct exynos5_hwc_composer_device_1_t *pdev = 1395 (struct exynos5_hwc_composer_device_1_t *)dev; 1396 1397 switch (what) { 1398 case HWC_BACKGROUND_LAYER_SUPPORTED: 1399 // we support the background layer 1400 value[0] = 1; 1401 break; 1402 case HWC_VSYNC_PERIOD: 1403 // vsync period in nanosecond 1404 value[0] = pdev->vsync_period; 1405 break; 1406 default: 1407 // unsupported query 1408 return -EINVAL; 1409 } 1410 return 0; 1411} 1412 1413static int exynos5_eventControl(struct hwc_composer_device_1 *dev, int dpy, 1414 int event, int enabled) 1415{ 1416 struct exynos5_hwc_composer_device_1_t *pdev = 1417 (struct exynos5_hwc_composer_device_1_t *)dev; 1418 1419 switch (event) { 1420 case HWC_EVENT_VSYNC: 1421 __u32 val = !!enabled; 1422 int err = ioctl(pdev->fd, S3CFB_SET_VSYNC_INT, &val); 1423 if (err < 0) { 1424 ALOGE("vsync ioctl failed"); 1425 return -errno; 1426 } 1427 1428 return 0; 1429 } 1430 1431 return -EINVAL; 1432} 1433 1434static void handle_hdmi_uevent(struct exynos5_hwc_composer_device_1_t *pdev, 1435 const char *buff, int len) 1436{ 1437 const char *s = buff; 1438 s += strlen(s) + 1; 1439 1440 while (*s) { 1441 if (!strncmp(s, "SWITCH_STATE=", strlen("SWITCH_STATE="))) 1442 pdev->hdmi_hpd = atoi(s + strlen("SWITCH_STATE=")) == 1; 1443 1444 s += strlen(s) + 1; 1445 if (s - buff >= len) 1446 break; 1447 } 1448 1449 if (pdev->hdmi_hpd) { 1450 if (hdmi_get_config(pdev)) { 1451 ALOGE("Error reading HDMI configuration"); 1452 pdev->hdmi_hpd = false; 1453 return; 1454 } 1455 } 1456 1457 ALOGV("HDMI HPD changed to %s", pdev->hdmi_hpd ? "enabled" : "disabled"); 1458 if (pdev->hdmi_hpd) 1459 ALOGI("HDMI Resolution changed to %dx%d", pdev->hdmi_h, pdev->hdmi_w); 1460 1461 /* hwc_dev->procs is set right after the device is opened, but there is 1462 * still a race condition where a hotplug event might occur after the open 1463 * but before the procs are registered. */ 1464 if (pdev->procs) 1465 pdev->procs->invalidate(pdev->procs); 1466} 1467 1468static void handle_vsync_event(struct exynos5_hwc_composer_device_1_t *pdev) 1469{ 1470 if (!pdev->procs) 1471 return; 1472 1473 int err = lseek(pdev->vsync_fd, 0, SEEK_SET); 1474 if (err < 0) { 1475 ALOGE("error seeking to vsync timestamp: %s", strerror(errno)); 1476 return; 1477 } 1478 1479 char buf[4096]; 1480 err = read(pdev->vsync_fd, buf, sizeof(buf)); 1481 if (err < 0) { 1482 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1483 return; 1484 } 1485 buf[sizeof(buf) - 1] = '\0'; 1486 1487 errno = 0; 1488 uint64_t timestamp = strtoull(buf, NULL, 0); 1489 if (!errno) 1490 pdev->procs->vsync(pdev->procs, 0, timestamp); 1491} 1492 1493static void *hwc_vsync_thread(void *data) 1494{ 1495 struct exynos5_hwc_composer_device_1_t *pdev = 1496 (struct exynos5_hwc_composer_device_1_t *)data; 1497 char uevent_desc[4096]; 1498 memset(uevent_desc, 0, sizeof(uevent_desc)); 1499 1500 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); 1501 1502 uevent_init(); 1503 1504 char temp[4096]; 1505 int err = read(pdev->vsync_fd, temp, sizeof(temp)); 1506 if (err < 0) { 1507 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1508 return NULL; 1509 } 1510 1511 struct pollfd fds[2]; 1512 fds[0].fd = pdev->vsync_fd; 1513 fds[0].events = POLLPRI; 1514 fds[1].fd = uevent_get_fd(); 1515 fds[1].events = POLLIN; 1516 1517 while (true) { 1518 int err = poll(fds, 2, -1); 1519 1520 if (err > 0) { 1521 if (fds[0].revents & POLLPRI) { 1522 handle_vsync_event(pdev); 1523 } 1524 else if (fds[1].revents & POLLIN) { 1525 int len = uevent_next_event(uevent_desc, 1526 sizeof(uevent_desc) - 2); 1527 1528 bool hdmi = !strcmp(uevent_desc, 1529 "change@/devices/virtual/switch/hdmi"); 1530 if (hdmi) 1531 handle_hdmi_uevent(pdev, uevent_desc, len); 1532 } 1533 } 1534 else if (err == -1) { 1535 if (errno == EINTR) 1536 break; 1537 ALOGE("error in vsync thread: %s", strerror(errno)); 1538 } 1539 } 1540 1541 return NULL; 1542} 1543 1544static int exynos5_blank(struct hwc_composer_device_1 *dev, int dpy, int blank) 1545{ 1546 struct exynos5_hwc_composer_device_1_t *pdev = 1547 (struct exynos5_hwc_composer_device_1_t *)dev; 1548 1549 int fb_blank = blank ? FB_BLANK_POWERDOWN : FB_BLANK_UNBLANK; 1550 int err = ioctl(pdev->fd, FBIOBLANK, fb_blank); 1551 if (err < 0) { 1552 ALOGE("%sblank ioctl failed", blank ? "" : "un"); 1553 return -errno; 1554 } 1555 1556 if (pdev->hdmi_hpd) { 1557 if (blank && !pdev->hdmi_blanked) 1558 hdmi_disable(pdev); 1559 pdev->hdmi_blanked = !!blank; 1560 } 1561 1562 return 0; 1563} 1564 1565static void exynos5_dump(hwc_composer_device_1* dev, char *buff, int buff_len) 1566{ 1567 if (buff_len <= 0) 1568 return; 1569 1570 struct exynos5_hwc_composer_device_1_t *pdev = 1571 (struct exynos5_hwc_composer_device_1_t *)dev; 1572 1573 android::String8 result; 1574 1575 result.appendFormat(" hdmi_enabled=%u\n", pdev->hdmi_enabled); 1576 if (pdev->hdmi_enabled) 1577 result.appendFormat(" w=%u, h=%u\n", pdev->hdmi_w, pdev->hdmi_h); 1578 result.append( 1579 " type | handle | color | blend | format | position | size | gsc \n" 1580 "----------+----------|----------+-------+--------+---------------+---------------------\n"); 1581 // 8_______ | 8_______ | 8_______ | 5____ | 6_____ | [5____,5____] | [5____,5____] | 3__ \n" 1582 1583 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1584 struct s3c_fb_win_config &config = pdev->last_config[i]; 1585 if (config.state == config.S3C_FB_WIN_STATE_DISABLED) { 1586 result.appendFormat(" %8s | %8s | %8s | %5s | %6s | %13s | %13s", 1587 "DISABLED", "-", "-", "-", "-", "-", "-"); 1588 } 1589 else { 1590 if (config.state == config.S3C_FB_WIN_STATE_COLOR) 1591 result.appendFormat(" %8s | %8s | %8x | %5s | %6s", "COLOR", 1592 "-", config.color, "-", "-"); 1593 else 1594 result.appendFormat(" %8s | %8x | %8s | %5x | %6x", 1595 pdev->last_fb_window == i ? "FB" : "OVERLAY", 1596 intptr_t(pdev->last_handles[i]), 1597 "-", config.blending, config.format); 1598 1599 result.appendFormat(" | [%5d,%5d] | [%5u,%5u]", config.x, config.y, 1600 config.w, config.h); 1601 } 1602 if (pdev->last_gsc_map[i].mode == exynos5_gsc_map_t::GSC_NONE) 1603 result.appendFormat(" | %3s", "-"); 1604 else 1605 result.appendFormat(" | %3d", 1606 AVAILABLE_GSC_UNITS[pdev->last_gsc_map[i].idx]); 1607 result.append("\n"); 1608 } 1609 1610 strlcpy(buff, result.string(), buff_len); 1611} 1612 1613static int exynos5_getDisplayConfigs(struct hwc_composer_device_1 *dev, 1614 int disp, uint32_t *configs, size_t *numConfigs) 1615{ 1616 struct exynos5_hwc_composer_device_1_t *pdev = 1617 (struct exynos5_hwc_composer_device_1_t *)dev; 1618 1619 if (*numConfigs == 0) 1620 return 0; 1621 1622 if (disp == HWC_DISPLAY_PRIMARY) { 1623 configs[0] = 0; 1624 *numConfigs = 1; 1625 return 0; 1626 } else if (disp == HWC_DISPLAY_EXTERNAL) { 1627 if (!pdev->hdmi_enabled) { 1628 return -EINVAL; 1629 } 1630 1631 int err = hdmi_get_config(pdev); 1632 if (err) { 1633 return -EINVAL; 1634 } 1635 1636 configs[0] = 0; 1637 *numConfigs = 1; 1638 return 0; 1639 } 1640 1641 return -EINVAL; 1642} 1643 1644static int32_t exynos5_fimd_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1645 const uint32_t attribute) 1646{ 1647 switch(attribute) { 1648 case HWC_DISPLAY_VSYNC_PERIOD: 1649 return pdev->vsync_period; 1650 1651 case HWC_DISPLAY_WIDTH: 1652 return pdev->xres; 1653 1654 case HWC_DISPLAY_HEIGHT: 1655 return pdev->yres; 1656 1657 case HWC_DISPLAY_DPI_X: 1658 return pdev->xdpi; 1659 1660 case HWC_DISPLAY_DPI_Y: 1661 return pdev->ydpi; 1662 1663 default: 1664 ALOGE("unknown display attribute %u", attribute); 1665 return -EINVAL; 1666 } 1667} 1668 1669static int32_t exynos5_hdmi_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1670 const uint32_t attribute) 1671{ 1672 switch(attribute) { 1673 case HWC_DISPLAY_VSYNC_PERIOD: 1674 return pdev->vsync_period; 1675 1676 case HWC_DISPLAY_WIDTH: 1677 return pdev->hdmi_w; 1678 1679 case HWC_DISPLAY_HEIGHT: 1680 return pdev->hdmi_h; 1681 1682 case HWC_DISPLAY_DPI_X: 1683 case HWC_DISPLAY_DPI_Y: 1684 return 0; // unknown 1685 1686 default: 1687 ALOGE("unknown display attribute %u", attribute); 1688 return -EINVAL; 1689 } 1690} 1691 1692static int exynos5_getDisplayAttributes(struct hwc_composer_device_1 *dev, 1693 int disp, uint32_t config, const uint32_t *attributes, int32_t *values) 1694{ 1695 struct exynos5_hwc_composer_device_1_t *pdev = 1696 (struct exynos5_hwc_composer_device_1_t *)dev; 1697 1698 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; i++) { 1699 if (disp == HWC_DISPLAY_PRIMARY) 1700 values[i] = exynos5_fimd_attribute(pdev, attributes[i]); 1701 else if (disp == HWC_DISPLAY_EXTERNAL) 1702 values[i] = exynos5_hdmi_attribute(pdev, attributes[i]); 1703 else { 1704 ALOGE("unknown display type %u", disp); 1705 return -EINVAL; 1706 } 1707 } 1708 1709 return 0; 1710} 1711 1712static int exynos5_close(hw_device_t* device); 1713 1714static int exynos5_open(const struct hw_module_t *module, const char *name, 1715 struct hw_device_t **device) 1716{ 1717 int ret; 1718 int refreshRate; 1719 int sw_fd; 1720 1721 if (strcmp(name, HWC_HARDWARE_COMPOSER)) { 1722 return -EINVAL; 1723 } 1724 1725 struct exynos5_hwc_composer_device_1_t *dev; 1726 dev = (struct exynos5_hwc_composer_device_1_t *)malloc(sizeof(*dev)); 1727 memset(dev, 0, sizeof(*dev)); 1728 1729 if (hw_get_module(GRALLOC_HARDWARE_MODULE_ID, 1730 (const struct hw_module_t **)&dev->gralloc_module)) { 1731 ALOGE("failed to get gralloc hw module"); 1732 ret = -EINVAL; 1733 goto err_get_module; 1734 } 1735 1736 if (gralloc_open((const hw_module_t *)dev->gralloc_module, 1737 &dev->alloc_device)) { 1738 ALOGE("failed to open gralloc"); 1739 ret = -EINVAL; 1740 goto err_get_module; 1741 } 1742 1743 dev->fd = open("/dev/graphics/fb0", O_RDWR); 1744 if (dev->fd < 0) { 1745 ALOGE("failed to open framebuffer"); 1746 ret = dev->fd; 1747 goto err_open_fb; 1748 } 1749 1750 struct fb_var_screeninfo info; 1751 if (ioctl(dev->fd, FBIOGET_VSCREENINFO, &info) == -1) { 1752 ALOGE("FBIOGET_VSCREENINFO ioctl failed: %s", strerror(errno)); 1753 ret = -errno; 1754 goto err_ioctl; 1755 } 1756 1757 refreshRate = 1000000000000LLU / 1758 ( 1759 uint64_t( info.upper_margin + info.lower_margin + info.yres ) 1760 * ( info.left_margin + info.right_margin + info.xres ) 1761 * info.pixclock 1762 ); 1763 1764 if (refreshRate == 0) { 1765 ALOGW("invalid refresh rate, assuming 60 Hz"); 1766 refreshRate = 60; 1767 } 1768 1769 dev->xres = 2560; 1770 dev->yres = 1600; 1771 dev->xdpi = 1000 * (info.xres * 25.4f) / info.width; 1772 dev->ydpi = 1000 * (info.yres * 25.4f) / info.height; 1773 dev->vsync_period = 1000000000 / refreshRate; 1774 1775 ALOGV("using\n" 1776 "xres = %d px\n" 1777 "yres = %d px\n" 1778 "width = %d mm (%f dpi)\n" 1779 "height = %d mm (%f dpi)\n" 1780 "refresh rate = %d Hz\n", 1781 dev->xres, dev->yres, info.width, dev->xdpi / 1000.0, 1782 info.height, dev->ydpi / 1000.0, refreshRate); 1783 1784 dev->hdmi_mixer0 = open("/dev/v4l-subdev7", O_RDWR); 1785 if (dev->hdmi_layer0 < 0) { 1786 ALOGE("failed to open hdmi mixer0 subdev"); 1787 ret = dev->hdmi_layer0; 1788 goto err_ioctl; 1789 } 1790 1791 dev->hdmi_layer0 = open("/dev/video16", O_RDWR); 1792 if (dev->hdmi_layer0 < 0) { 1793 ALOGE("failed to open hdmi layer0 device"); 1794 ret = dev->hdmi_layer0; 1795 goto err_mixer0; 1796 } 1797 1798 dev->hdmi_layer1 = open("/dev/video17", O_RDWR); 1799 if (dev->hdmi_layer1 < 0) { 1800 ALOGE("failed to open hdmi layer1 device"); 1801 ret = dev->hdmi_layer1; 1802 goto err_hdmi0; 1803 } 1804 1805 dev->vsync_fd = open("/sys/devices/platform/exynos5-fb.1/vsync", O_RDONLY); 1806 if (dev->vsync_fd < 0) { 1807 ALOGE("failed to open vsync attribute"); 1808 ret = dev->vsync_fd; 1809 goto err_hdmi1; 1810 } 1811 1812 sw_fd = open("/sys/class/switch/hdmi/state", O_RDONLY); 1813 if (sw_fd) { 1814 char val; 1815 if (read(sw_fd, &val, 1) == 1 && val == '1') { 1816 dev->hdmi_hpd = true; 1817 if (hdmi_get_config(dev)) { 1818 ALOGE("Error reading HDMI configuration"); 1819 dev->hdmi_hpd = false; 1820 } 1821 } 1822 } 1823 1824 dev->base.common.tag = HARDWARE_DEVICE_TAG; 1825 dev->base.common.version = HWC_DEVICE_API_VERSION_1_1; 1826 dev->base.common.module = const_cast<hw_module_t *>(module); 1827 dev->base.common.close = exynos5_close; 1828 1829 dev->base.prepare = exynos5_prepare; 1830 dev->base.set = exynos5_set; 1831 dev->base.eventControl = exynos5_eventControl; 1832 dev->base.blank = exynos5_blank; 1833 dev->base.query = exynos5_query; 1834 dev->base.registerProcs = exynos5_registerProcs; 1835 dev->base.dump = exynos5_dump; 1836 dev->base.getDisplayConfigs = exynos5_getDisplayConfigs; 1837 dev->base.getDisplayAttributes = exynos5_getDisplayAttributes; 1838 1839 *device = &dev->base.common; 1840 1841 ret = pthread_create(&dev->vsync_thread, NULL, hwc_vsync_thread, dev); 1842 if (ret) { 1843 ALOGE("failed to start vsync thread: %s", strerror(ret)); 1844 ret = -ret; 1845 goto err_vsync; 1846 } 1847 1848 char value[PROPERTY_VALUE_MAX]; 1849 property_get("debug.hwc.force_gpu", value, "0"); 1850 dev->force_gpu = atoi(value); 1851 1852 return 0; 1853 1854err_vsync: 1855 close(dev->vsync_fd); 1856err_mixer0: 1857 close(dev->hdmi_mixer0); 1858err_hdmi1: 1859 close(dev->hdmi_layer0); 1860err_hdmi0: 1861 close(dev->hdmi_layer1); 1862err_ioctl: 1863 close(dev->fd); 1864err_open_fb: 1865 gralloc_close(dev->alloc_device); 1866err_get_module: 1867 free(dev); 1868 return ret; 1869} 1870 1871static int exynos5_close(hw_device_t *device) 1872{ 1873 struct exynos5_hwc_composer_device_1_t *dev = 1874 (struct exynos5_hwc_composer_device_1_t *)device; 1875 pthread_kill(dev->vsync_thread, SIGTERM); 1876 pthread_join(dev->vsync_thread, NULL); 1877 for (size_t i = 0; i < NUM_GSC_UNITS; i++) { 1878 if (dev->gsc[i].gsc) 1879 exynos_gsc_destroy(dev->gsc[i].gsc); 1880 for (size_t j = 0; i < NUM_GSC_DST_BUFS; j++) 1881 if (dev->gsc[i].dst_buf[j]) 1882 dev->alloc_device->free(dev->alloc_device, dev->gsc[i].dst_buf[j]); 1883 } 1884 gralloc_close(dev->alloc_device); 1885 close(dev->vsync_fd); 1886 close(dev->hdmi_mixer0); 1887 close(dev->hdmi_layer0); 1888 close(dev->hdmi_layer1); 1889 close(dev->fd); 1890 return 0; 1891} 1892 1893static struct hw_module_methods_t exynos5_hwc_module_methods = { 1894 open: exynos5_open, 1895}; 1896 1897hwc_module_t HAL_MODULE_INFO_SYM = { 1898 common: { 1899 tag: HARDWARE_MODULE_TAG, 1900 module_api_version: HWC_MODULE_API_VERSION_0_1, 1901 hal_api_version: HARDWARE_HAL_API_VERSION, 1902 id: HWC_HARDWARE_MODULE_ID, 1903 name: "Samsung exynos5 hwcomposer module", 1904 author: "Google", 1905 methods: &exynos5_hwc_module_methods, 1906 } 1907}; 1908