hwc.cpp revision bb3bd9e63d6e35f7c2bcb069de6cfbd02b97776d
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include <errno.h> 17#include <fcntl.h> 18#include <poll.h> 19#include <pthread.h> 20#include <stdio.h> 21#include <stdlib.h> 22 23#include <sys/ioctl.h> 24#include <sys/mman.h> 25#include <sys/time.h> 26#include <sys/resource.h> 27 28#include <s3c-fb.h> 29 30#include <EGL/egl.h> 31 32#define HWC_REMOVE_DEPRECATED_VERSIONS 1 33 34#include <cutils/compiler.h> 35#include <cutils/log.h> 36#include <cutils/properties.h> 37#include <hardware/gralloc.h> 38#include <hardware/hardware.h> 39#include <hardware/hwcomposer.h> 40#include <hardware_legacy/uevent.h> 41#include <utils/String8.h> 42#include <utils/Vector.h> 43 44#include <sync/sync.h> 45 46#include "ion.h" 47#include "gralloc_priv.h" 48#include "exynos_gscaler.h" 49#include "exynos_format.h" 50#include "exynos_v4l2.h" 51#include "s5p_tvout_v4l2.h" 52 53const size_t NUM_HW_WINDOWS = 5; 54const size_t NO_FB_NEEDED = NUM_HW_WINDOWS + 1; 55const size_t MAX_PIXELS = 2560 * 1600 * 2; 56const size_t GSC_W_ALIGNMENT = 16; 57const size_t GSC_H_ALIGNMENT = 16; 58const int AVAILABLE_GSC_UNITS[] = { 0, 3 }; 59const size_t NUM_GSC_UNITS = sizeof(AVAILABLE_GSC_UNITS) / 60 sizeof(AVAILABLE_GSC_UNITS[0]); 61 62struct exynos5_hwc_composer_device_1_t; 63 64struct exynos5_gsc_map_t { 65 enum { 66 GSC_NONE = 0, 67 GSC_M2M, 68 // TODO: GSC_LOCAL_PATH 69 } mode; 70 int idx; 71}; 72 73struct exynos5_hwc_post_data_t { 74 int overlay_map[NUM_HW_WINDOWS]; 75 exynos5_gsc_map_t gsc_map[NUM_HW_WINDOWS]; 76 size_t fb_window; 77}; 78 79const size_t NUM_GSC_DST_BUFS = 3; 80struct exynos5_gsc_data_t { 81 void *gsc; 82 exynos_gsc_img src_cfg; 83 exynos_gsc_img dst_cfg; 84 buffer_handle_t dst_buf[NUM_GSC_DST_BUFS]; 85 size_t current_buf; 86}; 87 88struct exynos5_hwc_composer_device_1_t { 89 hwc_composer_device_1_t base; 90 91 int fd; 92 int vsync_fd; 93 exynos5_hwc_post_data_t bufs; 94 95 const private_module_t *gralloc_module; 96 alloc_device_t *alloc_device; 97 const hwc_procs_t *procs; 98 pthread_t vsync_thread; 99 int force_gpu; 100 101 int32_t xres; 102 int32_t yres; 103 int32_t xdpi; 104 int32_t ydpi; 105 int32_t vsync_period; 106 107 int hdmi_mixer0; 108 int hdmi_layer0; 109 int hdmi_layer1; 110 bool hdmi_hpd; 111 bool hdmi_enabled; 112 bool hdmi_blanked; 113 void *hdmi_gsc; 114 int hdmi_w; 115 int hdmi_h; 116 exynos_gsc_img hdmi_src; 117 exynos_gsc_img hdmi_dst; 118 119 exynos5_gsc_data_t gsc[NUM_GSC_UNITS]; 120 121 struct s3c_fb_win_config last_config[NUM_HW_WINDOWS]; 122 size_t last_fb_window; 123 const void *last_handles[NUM_HW_WINDOWS]; 124 exynos5_gsc_map_t last_gsc_map[NUM_HW_WINDOWS]; 125}; 126 127static void dump_handle(private_handle_t *h) 128{ 129 ALOGV("\t\tformat = %d, width = %u, height = %u, stride = %u, vstride = %u", 130 h->format, h->width, h->height, h->stride, h->vstride); 131} 132 133static void dump_layer(hwc_layer_1_t const *l) 134{ 135 ALOGV("\ttype=%d, flags=%08x, handle=%p, tr=%02x, blend=%04x, " 136 "{%d,%d,%d,%d}, {%d,%d,%d,%d}", 137 l->compositionType, l->flags, l->handle, l->transform, 138 l->blending, 139 l->sourceCrop.left, 140 l->sourceCrop.top, 141 l->sourceCrop.right, 142 l->sourceCrop.bottom, 143 l->displayFrame.left, 144 l->displayFrame.top, 145 l->displayFrame.right, 146 l->displayFrame.bottom); 147 148 if(l->handle && !(l->flags & HWC_SKIP_LAYER)) 149 dump_handle(private_handle_t::dynamicCast(l->handle)); 150} 151 152static void dump_config(s3c_fb_win_config &c) 153{ 154 ALOGV("\tstate = %u", c.state); 155 if (c.state == c.S3C_FB_WIN_STATE_BUFFER) { 156 ALOGV("\t\tfd = %d, offset = %u, stride = %u, " 157 "x = %d, y = %d, w = %u, h = %u, " 158 "format = %u, blending = %u", 159 c.fd, c.offset, c.stride, 160 c.x, c.y, c.w, c.h, 161 c.format, c.blending); 162 } 163 else if (c.state == c.S3C_FB_WIN_STATE_COLOR) { 164 ALOGV("\t\tcolor = %u", c.color); 165 } 166} 167 168static void dump_gsc_img(exynos_gsc_img &c) 169{ 170 ALOGV("\tx = %u, y = %u, w = %u, h = %u, fw = %u, fh = %u", 171 c.x, c.y, c.w, c.h, c.fw, c.fh); 172 ALOGV("\taddr = {%u, %u, %u}, rot = %u, cacheable = %u, drmMode = %u", 173 c.yaddr, c.uaddr, c.vaddr, c.rot, c.cacheable, c.drmMode); 174} 175 176inline int WIDTH(const hwc_rect &rect) { return rect.right - rect.left; } 177inline int HEIGHT(const hwc_rect &rect) { return rect.bottom - rect.top; } 178template<typename T> inline T max(T a, T b) { return (a > b) ? a : b; } 179template<typename T> inline T min(T a, T b) { return (a < b) ? a : b; } 180 181static bool is_transformed(const hwc_layer_1_t &layer) 182{ 183 return layer.transform != 0; 184} 185 186static bool is_rotated(const hwc_layer_1_t &layer) 187{ 188 return (layer.transform & HAL_TRANSFORM_ROT_90) || 189 (layer.transform & HAL_TRANSFORM_ROT_180); 190} 191 192static bool is_scaled(const hwc_layer_1_t &layer) 193{ 194 return WIDTH(layer.displayFrame) != WIDTH(layer.sourceCrop) || 195 HEIGHT(layer.displayFrame) != HEIGHT(layer.sourceCrop); 196} 197 198static inline bool gsc_dst_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 199{ 200 return c1.x != c2.x || 201 c1.y != c2.y || 202 c1.w != c2.w || 203 c1.h != c2.h || 204 c1.format != c2.format || 205 c1.rot != c2.rot || 206 c1.cacheable != c2.cacheable || 207 c1.drmMode != c2.drmMode; 208} 209 210static inline bool gsc_src_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 211{ 212 return gsc_dst_cfg_changed(c1, c2) || 213 c1.fw != c2.fw || 214 c1.fh != c2.fh; 215} 216 217static enum s3c_fb_pixel_format exynos5_format_to_s3c_format(int format) 218{ 219 switch (format) { 220 case HAL_PIXEL_FORMAT_RGBA_8888: 221 return S3C_FB_PIXEL_FORMAT_RGBA_8888; 222 case HAL_PIXEL_FORMAT_RGBX_8888: 223 return S3C_FB_PIXEL_FORMAT_RGBX_8888; 224 case HAL_PIXEL_FORMAT_RGBA_5551: 225 return S3C_FB_PIXEL_FORMAT_RGBA_5551; 226 227 default: 228 return S3C_FB_PIXEL_FORMAT_MAX; 229 } 230} 231 232static bool exynos5_format_is_supported(int format) 233{ 234 return exynos5_format_to_s3c_format(format) < S3C_FB_PIXEL_FORMAT_MAX; 235} 236 237static bool exynos5_format_is_rgb(int format) 238{ 239 switch (format) { 240 case HAL_PIXEL_FORMAT_RGBA_8888: 241 case HAL_PIXEL_FORMAT_RGBX_8888: 242 case HAL_PIXEL_FORMAT_RGB_888: 243 case HAL_PIXEL_FORMAT_RGB_565: 244 case HAL_PIXEL_FORMAT_BGRA_8888: 245 case HAL_PIXEL_FORMAT_RGBA_5551: 246 case HAL_PIXEL_FORMAT_RGBA_4444: 247 return true; 248 249 default: 250 return false; 251 } 252} 253 254static bool exynos5_format_is_supported_by_gscaler(int format) 255{ 256 switch (format) { 257 case HAL_PIXEL_FORMAT_RGBX_8888: 258 case HAL_PIXEL_FORMAT_RGB_565: 259 case HAL_PIXEL_FORMAT_EXYNOS_YV12: 260 case HAL_PIXEL_FORMAT_YCbCr_420_SP: 261 case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED: 262 return true; 263 264 default: 265 return false; 266 } 267} 268 269static bool exynos5_format_is_ycrcb(int format) 270{ 271 return format == HAL_PIXEL_FORMAT_EXYNOS_YV12; 272} 273 274static bool exynos5_format_requires_gscaler(int format) 275{ 276 return exynos5_format_is_supported_by_gscaler(format) && 277 format != HAL_PIXEL_FORMAT_RGBX_8888; 278} 279 280static uint8_t exynos5_format_to_bpp(int format) 281{ 282 switch (format) { 283 case HAL_PIXEL_FORMAT_RGBA_8888: 284 case HAL_PIXEL_FORMAT_RGBX_8888: 285 return 32; 286 287 case HAL_PIXEL_FORMAT_RGBA_5551: 288 case HAL_PIXEL_FORMAT_RGBA_4444: 289 return 16; 290 291 default: 292 ALOGW("unrecognized pixel format %u", format); 293 return 0; 294 } 295} 296 297static bool exynos5_supports_gscaler(hwc_layer_1_t &layer, int format, 298 bool local_path) 299{ 300 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 301 302 int max_w = is_rotated(layer) ? 2048 : 4800; 303 int max_h = is_rotated(layer) ? 2048 : 3344; 304 305 bool rot90or270 = !!(layer.transform & HAL_TRANSFORM_ROT_90); 306 // n.b.: HAL_TRANSFORM_ROT_270 = HAL_TRANSFORM_ROT_90 | 307 // HAL_TRANSFORM_ROT_180 308 309 int src_w = WIDTH(layer.sourceCrop), src_h = HEIGHT(layer.sourceCrop); 310 int dest_w, dest_h; 311 if (rot90or270) { 312 dest_w = HEIGHT(layer.displayFrame); 313 dest_h = WIDTH(layer.displayFrame); 314 } else { 315 dest_w = WIDTH(layer.displayFrame); 316 dest_h = HEIGHT(layer.displayFrame); 317 } 318 int max_downscale = local_path ? 4 : 16; 319 const int max_upscale = 8; 320 321 return exynos5_format_is_supported_by_gscaler(format) && 322 handle->stride <= max_w && 323 handle->stride % GSC_W_ALIGNMENT == 0 && 324 src_w <= dest_w * max_downscale && 325 dest_w <= src_w * max_upscale && 326 handle->vstride <= max_h && 327 handle->vstride % GSC_H_ALIGNMENT == 0 && 328 src_h <= dest_h * max_downscale && 329 dest_h <= src_h * max_upscale && 330 // per 46.2 331 (!rot90or270 || layer.sourceCrop.top % 2 == 0) && 332 (!rot90or270 || layer.sourceCrop.left % 2 == 0); 333 // per 46.3.1.6 334} 335 336int hdmi_get_config(struct exynos5_hwc_composer_device_1_t *dev) 337{ 338 struct v4l2_dv_preset preset; 339 struct v4l2_dv_enum_preset enum_preset; 340 int index = 0; 341 bool found = false; 342 int ret; 343 344 if (ioctl(dev->hdmi_layer0, VIDIOC_G_DV_PRESET, &preset) < 0) { 345 ALOGE("%s: g_dv_preset error, %d", __func__, errno); 346 return -1; 347 } 348 349 while (true) { 350 enum_preset.index = index++; 351 ret = ioctl(dev->hdmi_layer0, VIDIOC_ENUM_DV_PRESETS, &enum_preset); 352 353 if (ret < 0) { 354 if (errno == EINVAL) 355 break; 356 ALOGE("%s: enum_dv_presets error, %d", __func__, errno); 357 return -1; 358 } 359 360 ALOGV("%s: %d preset=%02d width=%d height=%d name=%s", 361 __func__, enum_preset.index, enum_preset.preset, 362 enum_preset.width, enum_preset.height, enum_preset.name); 363 364 if (preset.preset == enum_preset.preset) { 365 dev->hdmi_w = enum_preset.width; 366 dev->hdmi_h = enum_preset.height; 367 found = true; 368 } 369 } 370 371 return found ? 0 : -1; 372} 373 374static enum s3c_fb_blending exynos5_blending_to_s3c_blending(int32_t blending) 375{ 376 switch (blending) { 377 case HWC_BLENDING_NONE: 378 return S3C_FB_BLENDING_NONE; 379 case HWC_BLENDING_PREMULT: 380 return S3C_FB_BLENDING_PREMULT; 381 case HWC_BLENDING_COVERAGE: 382 return S3C_FB_BLENDING_COVERAGE; 383 384 default: 385 return S3C_FB_BLENDING_MAX; 386 } 387} 388 389static bool exynos5_blending_is_supported(int32_t blending) 390{ 391 return exynos5_blending_to_s3c_blending(blending) < S3C_FB_BLENDING_MAX; 392} 393 394static int hdmi_start_background(struct exynos5_hwc_composer_device_1_t *dev) 395{ 396 struct v4l2_requestbuffers reqbuf; 397 struct v4l2_subdev_format sd_fmt; 398 struct v4l2_subdev_crop sd_crop; 399 struct v4l2_format fmt; 400 struct v4l2_buffer buffer; 401 struct v4l2_plane planes[1]; 402 403 memset(&reqbuf, 0, sizeof(reqbuf)); 404 memset(&sd_fmt, 0, sizeof(sd_fmt)); 405 memset(&sd_crop, 0, sizeof(sd_crop)); 406 memset(&fmt, 0, sizeof(fmt)); 407 memset(&buffer, 0, sizeof(buffer)); 408 memset(planes, 0, sizeof(planes)); 409 410 sd_fmt.pad = MIXER_G1_SUBDEV_PAD_SINK; 411 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 412 sd_fmt.format.width = 1; 413 sd_fmt.format.height = 1; 414 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 415 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 416 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 417 return -1; 418 } 419 420 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SINK; 421 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 422 sd_crop.rect.left = 0; 423 sd_crop.rect.top = 0; 424 sd_crop.rect.width = 1; 425 sd_crop.rect.height = 1; 426 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 427 ALOGE("%s: set_crop failed pad=%d", __func__, sd_crop.pad); 428 return -1; 429 } 430 431 sd_fmt.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 432 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 433 sd_fmt.format.width = dev->hdmi_w; 434 sd_fmt.format.height = dev->hdmi_h; 435 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 436 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 437 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 438 return -1; 439 } 440 441 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 442 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 443 sd_crop.rect.left = 0; 444 sd_crop.rect.top = 0; 445 sd_crop.rect.width = 1; 446 sd_crop.rect.height = 1; 447 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 448 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 449 return -1; 450 } 451 452 fmt.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 453 fmt.fmt.pix_mp.width = 1; 454 fmt.fmt.pix_mp.height = 1; 455 fmt.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_BGR32; 456 fmt.fmt.pix_mp.field = V4L2_FIELD_ANY; 457 fmt.fmt.pix_mp.num_planes = 1; 458 if (exynos_v4l2_s_fmt(dev->hdmi_layer1, &fmt) < 0) { 459 ALOGE("%s::videodev set format failed", __func__); 460 return -1; 461 } 462 463 reqbuf.count = 1; 464 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 465 reqbuf.memory = V4L2_MEMORY_MMAP; 466 467 if (exynos_v4l2_reqbufs(dev->hdmi_layer1, &reqbuf) < 0) { 468 ALOGE("%s: exynos_v4l2_reqbufs failed %d", __func__, errno); 469 return -1; 470 } 471 472 if (reqbuf.count != 1) { 473 ALOGE("%s: didn't get buffer", __func__); 474 return -1; 475 } 476 477 memset(&buffer, 0, sizeof(buffer)); 478 buffer.type = reqbuf.type; 479 buffer.memory = V4L2_MEMORY_MMAP; 480 buffer.length = 1; 481 buffer.m.planes = planes; 482 if (exynos_v4l2_querybuf(dev->hdmi_layer1, &buffer) < 0) { 483 ALOGE("%s: exynos_v4l2_querybuf failed %d", __func__, errno); 484 return -1; 485 } 486 487 void *start = mmap(NULL, planes[0].length, PROT_READ | PROT_WRITE, 488 MAP_SHARED, dev->hdmi_layer1, planes[0].m.mem_offset); 489 if (start == MAP_FAILED) { 490 ALOGE("%s: mmap failed %d", __func__, errno); 491 return -1; 492 } 493 494 memset(start, 0, planes[0].length); 495 496 munmap(start, planes[0].length); 497 498 if (exynos_v4l2_qbuf(dev->hdmi_layer1, &buffer) < 0) { 499 ALOGE("%s: exynos_v4l2_qbuf failed %d", __func__, errno); 500 return -1; 501 } 502 503 if (exynos_v4l2_streamon(dev->hdmi_layer1, buffer.type) < 0) { 504 ALOGE("%s:stream on failed", __func__); 505 return -1; 506 } 507 508 if (exynos_v4l2_s_ctrl(dev->hdmi_layer1, V4L2_CID_TV_LAYER_PRIO, 0) < 0) { 509 ALOGE("%s: s_ctrl LAYER_PRIO failed", __func__); 510 return -1; 511 } 512 513 return 0; 514} 515 516static int hdmi_stop_background(struct exynos5_hwc_composer_device_1_t *dev) 517{ 518 struct v4l2_requestbuffers reqbuf; 519 520 if (exynos_v4l2_streamoff(dev->hdmi_layer1, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) < 0) { 521 ALOGE("%s:stream off failed", __func__); 522 return -1; 523 } 524 525 memset(&reqbuf, 0, sizeof(reqbuf)); 526 reqbuf.count = 0; 527 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 528 reqbuf.memory = V4L2_MEMORY_MMAP; 529 if (exynos_v4l2_reqbufs(dev->hdmi_layer1, &reqbuf) < 0) { 530 ALOGE("%s: exynos_v4l2_reqbufs failed %d", __func__, errno); 531 return -1; 532 } 533 534 return 0; 535} 536 537static int hdmi_enable(struct exynos5_hwc_composer_device_1_t *dev) 538{ 539 if (dev->hdmi_enabled) 540 return 0; 541 542 if (dev->hdmi_blanked) 543 return 0; 544 545 dev->hdmi_gsc = exynos_gsc_create_exclusive(3, GSC_OUTPUT_MODE, GSC_OUT_TV); 546 if (!dev->hdmi_gsc) { 547 ALOGE("%s: exynos_gsc_create_exclusive failed", __func__); 548 return -ENODEV; 549 } 550 551 memset(&dev->hdmi_src, 0, sizeof(dev->hdmi_src)); 552 553 if (hdmi_start_background(dev) < 0) { 554 ALOGE("%s: hdmi_start_background failed", __func__); 555 return -1; 556 } 557 558 dev->hdmi_enabled = true; 559 return 0; 560} 561 562static void hdmi_disable(struct exynos5_hwc_composer_device_1_t *dev) 563{ 564 if (!dev->hdmi_enabled) 565 return; 566 exynos_gsc_destroy(dev->hdmi_gsc); 567 hdmi_stop_background(dev); 568 dev->hdmi_gsc = NULL; 569 dev->hdmi_enabled = false; 570} 571 572static int hdmi_configure(struct exynos5_hwc_composer_device_1_t *dev, 573 exynos_gsc_img &src_cfg, 574 exynos_gsc_img &dst_cfg) 575{ 576 if (!gsc_src_cfg_changed(src_cfg, dev->hdmi_src) 577 && !gsc_dst_cfg_changed(dst_cfg, dev->hdmi_dst)) 578 return 0; 579 580 ALOGV("HDMI source config:"); 581 dump_gsc_img(src_cfg); 582 ALOGV("HDMI dest config:"); 583 dump_gsc_img(dst_cfg); 584 585 exynos_gsc_stop_exclusive(dev->hdmi_gsc); 586 587 int ret = exynos_gsc_config_exclusive(dev->hdmi_gsc, &src_cfg, &dst_cfg); 588 if (ret < 0) { 589 ALOGE("%s: exynos_gsc_config_exclusive failed %d", __func__, ret); 590 return ret; 591 } 592 593 dev->hdmi_src = src_cfg; 594 dev->hdmi_dst = dst_cfg; 595 return ret; 596} 597 598static int hdmi_configure_handle(struct exynos5_hwc_composer_device_1_t *dev, private_handle_t *h) 599{ 600 exynos_gsc_img src_cfg, dst_cfg; 601 memset(&src_cfg, 0, sizeof(src_cfg)); 602 memset(&dst_cfg, 0, sizeof(dst_cfg)); 603 604 src_cfg.w = src_cfg.fw = h->width; 605 src_cfg.h = src_cfg.fh = h->height; 606 src_cfg.format = HAL_PIXEL_FORMAT_BGRA_8888; 607 608 dst_cfg.w = dst_cfg.fw = dev->hdmi_w; 609 dst_cfg.h = dst_cfg.fh = dev->hdmi_h; 610 dst_cfg.format = HAL_PIXEL_FORMAT_EXYNOS_YV12; 611 612 return hdmi_configure(dev, src_cfg, dst_cfg); 613} 614 615static int hdmi_configure_layer(struct exynos5_hwc_composer_device_1_t *dev, hwc_layer_1_t &layer) 616{ 617 exynos_gsc_img src_cfg, dst_cfg; 618 memset(&src_cfg, 0, sizeof(src_cfg)); 619 memset(&dst_cfg, 0, sizeof(dst_cfg)); 620 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle); 621 622 src_cfg.x = layer.sourceCrop.left; 623 src_cfg.y = layer.sourceCrop.top; 624 src_cfg.w = WIDTH(layer.sourceCrop); 625 src_cfg.fw = src_handle->stride; 626 src_cfg.h = HEIGHT(layer.sourceCrop); 627 src_cfg.fh = src_handle->vstride; 628 src_cfg.format = src_handle->format; 629 630 if (dev->hdmi_w * src_cfg.h < dev->hdmi_h * src_cfg.w) { 631 dst_cfg.w = dev->hdmi_w; 632 dst_cfg.fw = dev->hdmi_w; 633 dst_cfg.fh = dev->hdmi_h; 634 dst_cfg.h = dev->hdmi_w * src_cfg.h / src_cfg.w; 635 dst_cfg.y = (dev->hdmi_h - dst_cfg.h) / 2; 636 } 637 else { 638 dst_cfg.w = dev->hdmi_h * src_cfg.w / src_cfg.h; 639 dst_cfg.fw = dev->hdmi_w; 640 dst_cfg.h = dev->hdmi_h; 641 dst_cfg.fh = dev->hdmi_h; 642 dst_cfg.x = (dev->hdmi_w - dst_cfg.w) / 2; 643 } 644 dst_cfg.format = HAL_PIXEL_FORMAT_EXYNOS_YV12; 645 dst_cfg.rot = layer.transform; 646 647 return hdmi_configure(dev, src_cfg, dst_cfg); 648} 649 650static int hdmi_output(struct exynos5_hwc_composer_device_1_t *dev, private_handle_t *h) 651{ 652 exynos_gsc_img src_info; 653 exynos_gsc_img dst_info; 654 655 memset(&src_info, 0, sizeof(src_info)); 656 memset(&dst_info, 0, sizeof(dst_info)); 657 658 src_info.yaddr = h->fd; 659 if (exynos5_format_is_ycrcb(h->format)) { 660 src_info.uaddr = h->fd2; 661 src_info.vaddr = h->fd1; 662 } else { 663 src_info.uaddr = h->fd1; 664 src_info.vaddr = h->fd2; 665 } 666 667 int ret = exynos_gsc_run_exclusive(dev->hdmi_gsc, &src_info, &dst_info); 668 if (ret < 0) { 669 ALOGE("%s: exynos_gsc_run_exclusive failed %d", __func__, ret); 670 return ret; 671 } 672 673 return 0; 674} 675 676bool exynos5_is_offscreen(hwc_layer_1_t &layer, 677 struct exynos5_hwc_composer_device_1_t *pdev) 678{ 679 return layer.sourceCrop.left > pdev->xres || 680 layer.sourceCrop.right < 0 || 681 layer.sourceCrop.top > pdev->yres || 682 layer.sourceCrop.bottom < 0; 683} 684 685bool exynos5_supports_overlay(hwc_layer_1_t &layer, size_t i, 686 struct exynos5_hwc_composer_device_1_t *pdev) 687{ 688 if (layer.flags & HWC_SKIP_LAYER) { 689 ALOGV("\tlayer %u: skipping", i); 690 return false; 691 } 692 693 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 694 695 if (!handle) { 696 ALOGV("\tlayer %u: handle is NULL", i); 697 return false; 698 } 699 if (!exynos5_format_is_rgb(handle->format) && 700 !exynos5_format_is_supported_by_gscaler(handle->format)) { 701 ALOGW("\tlayer %u: unexpected format %u", i, handle->format); 702 return false; 703 } 704 705 if (exynos5_format_requires_gscaler(handle->format)) { 706 if (!exynos5_supports_gscaler(layer, handle->format, false)) { 707 ALOGV("\tlayer %u: gscaler required but not supported", i); 708 return false; 709 } 710 } else { 711 if (!exynos5_format_is_supported(handle->format)) { 712 ALOGV("\tlayer %u: pixel format %u not supported", i, handle->format); 713 return false; 714 } 715 if (is_scaled(layer)) { 716 ALOGV("\tlayer %u: scaling not supported", i); 717 return false; 718 } 719 if (is_transformed(layer)) { 720 ALOGV("\tlayer %u: transformations not supported", i); 721 return false; 722 } 723 } 724 if (!exynos5_blending_is_supported(layer.blending)) { 725 ALOGV("\tlayer %u: blending %d not supported", i, layer.blending); 726 return false; 727 } 728 if (CC_UNLIKELY(exynos5_is_offscreen(layer, pdev))) { 729 ALOGW("\tlayer %u: off-screen", i); 730 return false; 731 } 732 733 return true; 734} 735 736inline bool intersect(const hwc_rect &r1, const hwc_rect &r2) 737{ 738 return !(r1.left > r2.right || 739 r1.right < r2.left || 740 r1.top > r2.bottom || 741 r1.bottom < r2.top); 742} 743 744inline hwc_rect intersection(const hwc_rect &r1, const hwc_rect &r2) 745{ 746 hwc_rect i; 747 i.top = max(r1.top, r2.top); 748 i.bottom = min(r1.bottom, r2.bottom); 749 i.left = max(r1.left, r2.left); 750 i.right = min(r1.right, r2.right); 751 return i; 752} 753 754static int exynos5_prepare_fimd(exynos5_hwc_composer_device_1_t *pdev, 755 hwc_display_contents_1_t* contents, bool force_fb) 756{ 757 ALOGV("preparing %u layers for FIMD", contents->numHwLayers); 758 759 memset(pdev->bufs.gsc_map, 0, sizeof(pdev->bufs.gsc_map)); 760 761 force_fb = force_fb || pdev->force_gpu; 762 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 763 pdev->bufs.overlay_map[i] = -1; 764 765 bool fb_needed = false; 766 size_t first_fb = 0, last_fb = 0; 767 768 // find unsupported overlays 769 for (size_t i = 0; i < contents->numHwLayers; i++) { 770 hwc_layer_1_t &layer = contents->hwLayers[i]; 771 772 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 773 ALOGV("\tlayer %u: framebuffer target", i); 774 continue; 775 } 776 777 if (layer.compositionType == HWC_BACKGROUND && !force_fb) { 778 ALOGV("\tlayer %u: background supported", i); 779 dump_layer(&contents->hwLayers[i]); 780 continue; 781 } 782 783 if (exynos5_supports_overlay(contents->hwLayers[i], i, pdev) && 784 !force_fb) { 785 ALOGV("\tlayer %u: overlay supported", i); 786 layer.compositionType = HWC_OVERLAY; 787 dump_layer(&contents->hwLayers[i]); 788 continue; 789 } 790 791 if (!fb_needed) { 792 first_fb = i; 793 fb_needed = true; 794 } 795 last_fb = i; 796 layer.compositionType = HWC_FRAMEBUFFER; 797 798 dump_layer(&contents->hwLayers[i]); 799 } 800 801 // can't composite overlays sandwiched between framebuffers 802 if (fb_needed) 803 for (size_t i = first_fb; i < last_fb; i++) 804 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 805 806 // Incrementally try to add our supported layers to hardware windows. 807 // If adding a layer would violate a hardware constraint, force it 808 // into the framebuffer and try again. (Revisiting the entire list is 809 // necessary because adding a layer to the framebuffer can cause other 810 // windows to retroactively violate constraints.) 811 bool changed; 812 do { 813 android::Vector<hwc_rect> rects; 814 android::Vector<hwc_rect> overlaps; 815 size_t pixels_left, windows_left, gsc_left = NUM_GSC_UNITS; 816 817 if (fb_needed) { 818 hwc_rect_t fb_rect; 819 fb_rect.top = fb_rect.left = 0; 820 fb_rect.right = pdev->xres - 1; 821 fb_rect.bottom = pdev->yres - 1; 822 pixels_left = MAX_PIXELS - pdev->xres * pdev->yres; 823 windows_left = NUM_HW_WINDOWS - 1; 824 rects.push_back(fb_rect); 825 } 826 else { 827 pixels_left = MAX_PIXELS; 828 windows_left = NUM_HW_WINDOWS; 829 } 830 if (pdev->hdmi_enabled) 831 gsc_left--; 832 833 changed = false; 834 835 for (size_t i = 0; i < contents->numHwLayers; i++) { 836 hwc_layer_1_t &layer = contents->hwLayers[i]; 837 if ((layer.flags & HWC_SKIP_LAYER) || 838 layer.compositionType == HWC_FRAMEBUFFER_TARGET) 839 continue; 840 841 private_handle_t *handle = private_handle_t::dynamicCast( 842 layer.handle); 843 844 // we've already accounted for the framebuffer above 845 if (layer.compositionType == HWC_FRAMEBUFFER) 846 continue; 847 848 // only layer 0 can be HWC_BACKGROUND, so we can 849 // unconditionally allow it without extra checks 850 if (layer.compositionType == HWC_BACKGROUND) { 851 windows_left--; 852 continue; 853 } 854 855 size_t pixels_needed = WIDTH(layer.displayFrame) * 856 HEIGHT(layer.displayFrame); 857 bool can_compose = windows_left && pixels_needed <= pixels_left; 858 bool gsc_required = exynos5_format_requires_gscaler(handle->format); 859 if (gsc_required) 860 can_compose = can_compose && gsc_left; 861 862 // hwc_rect_t right and bottom values are normally exclusive; 863 // the intersection logic is simpler if we make them inclusive 864 hwc_rect_t visible_rect = layer.displayFrame; 865 visible_rect.right--; visible_rect.bottom--; 866 867 // no more than 2 layers can overlap on a given pixel 868 for (size_t j = 0; can_compose && j < overlaps.size(); j++) { 869 if (intersect(visible_rect, overlaps.itemAt(j))) 870 can_compose = false; 871 } 872 873 if (!can_compose) { 874 layer.compositionType = HWC_FRAMEBUFFER; 875 if (!fb_needed) { 876 first_fb = last_fb = i; 877 fb_needed = true; 878 } 879 else { 880 first_fb = min(i, first_fb); 881 last_fb = max(i, last_fb); 882 } 883 changed = true; 884 break; 885 } 886 887 for (size_t j = 0; j < rects.size(); j++) { 888 const hwc_rect_t &other_rect = rects.itemAt(j); 889 if (intersect(visible_rect, other_rect)) 890 overlaps.push_back(intersection(visible_rect, other_rect)); 891 } 892 rects.push_back(visible_rect); 893 pixels_left -= pixels_needed; 894 windows_left--; 895 if (gsc_required) 896 gsc_left--; 897 } 898 899 if (changed) 900 for (size_t i = first_fb; i < last_fb; i++) 901 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 902 } while(changed); 903 904 unsigned int nextWindow = 0; 905 int nextGsc = 0; 906 907 for (size_t i = 0; i < contents->numHwLayers; i++) { 908 hwc_layer_1_t &layer = contents->hwLayers[i]; 909 910 if (fb_needed && i == first_fb) { 911 ALOGV("assigning framebuffer to window %u\n", 912 nextWindow); 913 nextWindow++; 914 continue; 915 } 916 917 if (layer.compositionType != HWC_FRAMEBUFFER && 918 layer.compositionType != HWC_FRAMEBUFFER_TARGET) { 919 ALOGV("assigning layer %u to window %u", i, nextWindow); 920 pdev->bufs.overlay_map[nextWindow] = i; 921 if (layer.compositionType == HWC_OVERLAY) { 922 private_handle_t *handle = 923 private_handle_t::dynamicCast(layer.handle); 924 if (exynos5_format_requires_gscaler(handle->format)) { 925 ALOGV("\tusing gscaler %u", AVAILABLE_GSC_UNITS[nextGsc]); 926 pdev->bufs.gsc_map[nextWindow].mode = 927 exynos5_gsc_map_t::GSC_M2M; 928 pdev->bufs.gsc_map[nextWindow].idx = nextGsc++; 929 } 930 } 931 nextWindow++; 932 } 933 } 934 935 for (size_t i = nextGsc; i < NUM_GSC_UNITS; i++) { 936 for (size_t j = 0; j < NUM_GSC_DST_BUFS; j++) 937 if (pdev->gsc[i].dst_buf[j]) 938 pdev->alloc_device->free(pdev->alloc_device, 939 pdev->gsc[i].dst_buf[j]); 940 memset(&pdev->gsc[i], 0, sizeof(pdev->gsc[i])); 941 } 942 943 if (fb_needed) 944 pdev->bufs.fb_window = first_fb; 945 else 946 pdev->bufs.fb_window = NO_FB_NEEDED; 947 948 return 0; 949} 950 951static int exynos5_prepare_hdmi(exynos5_hwc_composer_device_1_t *pdev, 952 hwc_display_contents_1_t* contents) 953{ 954 ALOGE("exynos5_prepare_hdmi() not implemented"); 955 return -EINVAL; 956} 957 958static int exynos5_prepare(hwc_composer_device_1_t *dev, 959 size_t numDisplays, hwc_display_contents_1_t** displays) 960{ 961 if (!numDisplays || !displays) 962 return 0; 963 964 exynos5_hwc_composer_device_1_t *pdev = 965 (exynos5_hwc_composer_device_1_t *)dev; 966 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 967 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 968 969 if (pdev->hdmi_hpd) { 970 hdmi_enable(pdev); 971 } else { 972 hdmi_disable(pdev); 973 } 974 975 if (fimd_contents) { 976 bool force_fb = pdev->hdmi_enabled && !hdmi_contents; 977 int err = exynos5_prepare_fimd(pdev, fimd_contents, force_fb); 978 if (err) 979 return err; 980 } 981 982 if (hdmi_contents) { 983 if (!pdev->hdmi_enabled) { 984 ALOGE("HDMI disabled; can't prepare contents of external display"); 985 return -EINVAL; 986 } 987 int err = exynos5_prepare_hdmi(pdev, hdmi_contents); 988 if (err) 989 return err; 990 } 991 992 return 0; 993} 994 995static int exynos5_config_gsc_m2m(hwc_layer_1_t &layer, 996 alloc_device_t* alloc_device, exynos5_gsc_data_t *gsc_data, 997 int gsc_idx) 998{ 999 ALOGV("configuring gscaler %u for memory-to-memory", gsc_idx); 1000 1001 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle); 1002 buffer_handle_t dst_buf; 1003 private_handle_t *dst_handle; 1004 int ret = 0; 1005 1006 exynos_gsc_img src_cfg, dst_cfg; 1007 memset(&src_cfg, 0, sizeof(src_cfg)); 1008 memset(&dst_cfg, 0, sizeof(dst_cfg)); 1009 1010 src_cfg.x = layer.sourceCrop.left; 1011 src_cfg.y = layer.sourceCrop.top; 1012 src_cfg.w = WIDTH(layer.sourceCrop); 1013 src_cfg.fw = src_handle->stride; 1014 src_cfg.h = HEIGHT(layer.sourceCrop); 1015 src_cfg.fh = src_handle->vstride; 1016 src_cfg.yaddr = src_handle->fd; 1017 if (exynos5_format_is_ycrcb(src_handle->format)) { 1018 src_cfg.uaddr = src_handle->fd2; 1019 src_cfg.vaddr = src_handle->fd1; 1020 } else { 1021 src_cfg.uaddr = src_handle->fd1; 1022 src_cfg.vaddr = src_handle->fd2; 1023 } 1024 src_cfg.format = src_handle->format; 1025 src_cfg.drmMode = !!(src_handle->flags & GRALLOC_USAGE_PROTECTED); 1026 1027 dst_cfg.x = 0; 1028 dst_cfg.y = 0; 1029 dst_cfg.w = WIDTH(layer.displayFrame); 1030 dst_cfg.h = HEIGHT(layer.displayFrame); 1031 dst_cfg.format = HAL_PIXEL_FORMAT_BGRA_8888; 1032 dst_cfg.rot = layer.transform; 1033 dst_cfg.drmMode = src_cfg.drmMode; 1034 1035 ALOGV("source configuration:"); 1036 dump_gsc_img(src_cfg); 1037 1038 if (gsc_src_cfg_changed(src_cfg, gsc_data->src_cfg) || 1039 gsc_dst_cfg_changed(dst_cfg, gsc_data->dst_cfg)) { 1040 int dst_stride; 1041 int usage = GRALLOC_USAGE_SW_READ_NEVER | 1042 GRALLOC_USAGE_SW_WRITE_NEVER | 1043 GRALLOC_USAGE_HW_COMPOSER; 1044 1045 if (src_handle->flags & GRALLOC_USAGE_PROTECTED) 1046 usage |= GRALLOC_USAGE_PROTECTED; 1047 1048 int w = ALIGN(WIDTH(layer.displayFrame), GSC_W_ALIGNMENT); 1049 int h = ALIGN(HEIGHT(layer.displayFrame), GSC_H_ALIGNMENT); 1050 1051 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1052 if (gsc_data->dst_buf[i]) { 1053 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1054 gsc_data->dst_buf[i] = NULL; 1055 } 1056 1057 int ret = alloc_device->alloc(alloc_device, w, h, 1058 HAL_PIXEL_FORMAT_RGBX_8888, usage, &gsc_data->dst_buf[i], 1059 &dst_stride); 1060 if (ret < 0) { 1061 ALOGE("failed to allocate destination buffer: %s", 1062 strerror(-ret)); 1063 goto err_alloc; 1064 } 1065 } 1066 1067 gsc_data->current_buf = 0; 1068 } 1069 1070 dst_buf = gsc_data->dst_buf[gsc_data->current_buf]; 1071 dst_handle = private_handle_t::dynamicCast(dst_buf); 1072 1073 dst_cfg.fw = dst_handle->stride; 1074 dst_cfg.fh = dst_handle->vstride; 1075 dst_cfg.yaddr = dst_handle->fd; 1076 1077 ALOGV("destination configuration:"); 1078 dump_gsc_img(dst_cfg); 1079 1080 gsc_data->gsc = exynos_gsc_create_exclusive(AVAILABLE_GSC_UNITS[gsc_idx], 1081 GSC_M2M_MODE, GSC_DUMMY); 1082 if (!gsc_data->gsc) { 1083 ALOGE("failed to create gscaler handle"); 1084 ret = -1; 1085 goto err_alloc; 1086 } 1087 1088 ret = exynos_gsc_config_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1089 if (ret < 0) { 1090 ALOGE("failed to configure gscaler %u", gsc_idx); 1091 goto err_gsc_config; 1092 } 1093 1094 ret = exynos_gsc_run_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1095 if (ret < 0) { 1096 ALOGE("failed to run gscaler %u", gsc_idx); 1097 goto err_gsc_config; 1098 } 1099 1100 gsc_data->src_cfg = src_cfg; 1101 gsc_data->dst_cfg = dst_cfg; 1102 1103 return 0; 1104 1105err_gsc_config: 1106 exynos_gsc_destroy(gsc_data->gsc); 1107 gsc_data->gsc = NULL; 1108err_alloc: 1109 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1110 if (gsc_data->dst_buf[i]) { 1111 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1112 gsc_data->dst_buf[i] = NULL; 1113 } 1114 } 1115 memset(&gsc_data->src_cfg, 0, sizeof(gsc_data->src_cfg)); 1116 memset(&gsc_data->dst_cfg, 0, sizeof(gsc_data->dst_cfg)); 1117 return ret; 1118} 1119 1120static void exynos5_config_handle(private_handle_t *handle, 1121 hwc_rect_t &sourceCrop, hwc_rect_t &displayFrame, 1122 int32_t blending, int fence_fd, s3c_fb_win_config &cfg, 1123 exynos5_hwc_composer_device_1_t *pdev) 1124{ 1125 uint32_t x, y; 1126 uint32_t w = WIDTH(displayFrame); 1127 uint32_t h = HEIGHT(displayFrame); 1128 uint8_t bpp = exynos5_format_to_bpp(handle->format); 1129 uint32_t offset = (sourceCrop.top * handle->stride + sourceCrop.left) * bpp / 8; 1130 1131 if (displayFrame.left < 0) { 1132 unsigned int crop = -displayFrame.left; 1133 ALOGV("layer off left side of screen; cropping %u pixels from left edge", 1134 crop); 1135 x = 0; 1136 w -= crop; 1137 offset += crop * bpp / 8; 1138 } else { 1139 x = displayFrame.left; 1140 } 1141 1142 if (displayFrame.right > pdev->xres) { 1143 unsigned int crop = displayFrame.right - pdev->xres; 1144 ALOGV("layer off right side of screen; cropping %u pixels from right edge", 1145 crop); 1146 w -= crop; 1147 } 1148 1149 if (displayFrame.top < 0) { 1150 unsigned int crop = -displayFrame.top; 1151 ALOGV("layer off top side of screen; cropping %u pixels from top edge", 1152 crop); 1153 y = 0; 1154 h -= crop; 1155 offset += handle->stride * crop * bpp / 8; 1156 } else { 1157 y = displayFrame.top; 1158 } 1159 1160 if (displayFrame.bottom > pdev->yres) { 1161 int crop = displayFrame.bottom - pdev->yres; 1162 ALOGV("layer off bottom side of screen; cropping %u pixels from bottom edge", 1163 crop); 1164 h -= crop; 1165 } 1166 1167 cfg.state = cfg.S3C_FB_WIN_STATE_BUFFER; 1168 cfg.fd = handle->fd; 1169 cfg.x = x; 1170 cfg.y = y; 1171 cfg.w = w; 1172 cfg.h = h; 1173 cfg.format = exynos5_format_to_s3c_format(handle->format); 1174 cfg.offset = offset; 1175 cfg.stride = handle->stride * bpp / 8; 1176 cfg.blending = exynos5_blending_to_s3c_blending(blending); 1177 cfg.fence_fd = fence_fd; 1178} 1179 1180static void exynos5_config_overlay(hwc_layer_1_t *layer, s3c_fb_win_config &cfg, 1181 exynos5_hwc_composer_device_1_t *pdev) 1182{ 1183 if (layer->compositionType == HWC_BACKGROUND) { 1184 hwc_color_t color = layer->backgroundColor; 1185 cfg.state = cfg.S3C_FB_WIN_STATE_COLOR; 1186 cfg.color = (color.r << 16) | (color.g << 8) | color.b; 1187 cfg.x = 0; 1188 cfg.y = 0; 1189 cfg.w = pdev->xres; 1190 cfg.h = pdev->yres; 1191 return; 1192 } 1193 1194 private_handle_t *handle = private_handle_t::dynamicCast(layer->handle); 1195 exynos5_config_handle(handle, layer->sourceCrop, layer->displayFrame, 1196 layer->blending, layer->acquireFenceFd, cfg, pdev); 1197} 1198 1199static int exynos5_post_fimd(exynos5_hwc_composer_device_1_t *pdev, 1200 hwc_display_contents_1_t* contents, hwc_layer_1_t *fb_layer, 1201 bool hdmi_mirroring) 1202{ 1203 exynos5_hwc_post_data_t *pdata = &pdev->bufs; 1204 struct s3c_fb_win_config_data win_data; 1205 struct s3c_fb_win_config *config = win_data.config; 1206 1207 memset(config, 0, sizeof(win_data.config)); 1208 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1209 config[i].fence_fd = -1; 1210 1211 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1212 int layer_idx = pdata->overlay_map[i]; 1213 if (layer_idx != -1) { 1214 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1215 private_handle_t *handle = 1216 private_handle_t::dynamicCast(layer.handle); 1217 1218 if (pdata->gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) { 1219 int gsc_idx = pdata->gsc_map[i].idx; 1220 exynos5_gsc_data_t &gsc = pdev->gsc[gsc_idx]; 1221 1222 if (layer.acquireFenceFd != -1) { 1223 int err = sync_wait(layer.acquireFenceFd, 100); 1224 if (err != 0) 1225 ALOGW("fence for layer %zu didn't signal in 100 ms: %s", 1226 i, strerror(errno)); 1227 close(layer.acquireFenceFd); 1228 } 1229 1230 int err = exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc, 1231 gsc_idx); 1232 if (err < 0) { 1233 ALOGE("failed to queue gscaler %u input for layer %u", 1234 gsc_idx, i); 1235 continue; 1236 } 1237 1238 err = exynos_gsc_stop_exclusive(gsc.gsc); 1239 exynos_gsc_destroy(gsc.gsc); 1240 gsc.gsc = NULL; 1241 if (err < 0) { 1242 ALOGE("failed to dequeue gscaler output for layer %u", i); 1243 continue; 1244 } 1245 1246 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1247 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1248 private_handle_t *dst_handle = 1249 private_handle_t::dynamicCast(dst_buf); 1250 hwc_rect_t sourceCrop = { 0, 0, 1251 WIDTH(layer.displayFrame), HEIGHT(layer.displayFrame) }; 1252 exynos5_config_handle(dst_handle, sourceCrop, 1253 layer.displayFrame, layer.blending, -1, config[i], 1254 pdev); 1255 } else { 1256 exynos5_config_overlay(&layer, config[i], pdev); 1257 } 1258 } 1259 if (i == 0 && config[i].blending != S3C_FB_BLENDING_NONE) { 1260 ALOGV("blending not supported on window 0; forcing BLENDING_NONE"); 1261 config[i].blending = S3C_FB_BLENDING_NONE; 1262 } 1263 1264 ALOGV("window %u configuration:", i); 1265 dump_config(config[i]); 1266 } 1267 1268 int ret = ioctl(pdev->fd, S3CFB_WIN_CONFIG, &win_data); 1269 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1270 if (config[i].fence_fd != -1) 1271 close(config[i].fence_fd); 1272 if (ret < 0) { 1273 ALOGE("ioctl S3CFB_WIN_CONFIG failed: %s", strerror(errno)); 1274 return ret; 1275 } 1276 1277 memcpy(pdev->last_config, &win_data.config, sizeof(win_data.config)); 1278 memcpy(pdev->last_gsc_map, pdata->gsc_map, sizeof(pdata->gsc_map)); 1279 pdev->last_fb_window = pdata->fb_window; 1280 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1281 int layer_idx = pdata->overlay_map[i]; 1282 if (layer_idx != -1) { 1283 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1284 pdev->last_handles[i] = layer.handle; 1285 } 1286 } 1287 1288 if (hdmi_mirroring) { 1289 private_handle_t *fb = private_handle_t::dynamicCast(fb_layer->handle); 1290 hdmi_configure_handle(pdev, fb); 1291 hdmi_output(pdev, fb); 1292 } 1293 1294 return win_data.fence; 1295} 1296 1297static int exynos5_set_fimd(exynos5_hwc_composer_device_1_t *pdev, 1298 hwc_display_contents_1_t* contents, bool hdmi_mirroring) 1299{ 1300 if (!contents->dpy || !contents->sur) 1301 return 0; 1302 1303 hwc_layer_1_t *fb_layer = NULL; 1304 1305 if (pdev->bufs.fb_window != NO_FB_NEEDED) { 1306 for (size_t i = 0; i < contents->numHwLayers; i++) { 1307 if (contents->hwLayers[i].compositionType == 1308 HWC_FRAMEBUFFER_TARGET) { 1309 pdev->bufs.overlay_map[pdev->bufs.fb_window] = i; 1310 fb_layer = &contents->hwLayers[i]; 1311 break; 1312 } 1313 } 1314 1315 if (CC_UNLIKELY(!fb_layer)) { 1316 ALOGE("framebuffer target expected, but not provided"); 1317 return -EINVAL; 1318 } 1319 1320 ALOGV("framebuffer target buffer:"); 1321 dump_layer(fb_layer); 1322 } 1323 1324 int fence = exynos5_post_fimd(pdev, contents, fb_layer, hdmi_mirroring); 1325 if (fence < 0) 1326 return fence; 1327 1328 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1329 if (pdev->bufs.overlay_map[i] != -1) { 1330 hwc_layer_1_t &layer = 1331 contents->hwLayers[pdev->bufs.overlay_map[i]]; 1332 int dup_fd = dup(fence); 1333 if (dup_fd < 0) 1334 ALOGW("release fence dup failed: %s", strerror(errno)); 1335 layer.releaseFenceFd = dup_fd; 1336 } 1337 } 1338 close(fence); 1339 1340 return 0; 1341} 1342 1343static int exynos5_set_hdmi(exynos5_hwc_composer_device_1_t *pdev, 1344 hwc_display_contents_1_t* contents) 1345{ 1346 ALOGE("exynos5_set_hdmi() not implemented"); 1347 return -EINVAL; 1348} 1349 1350static int exynos5_set(struct hwc_composer_device_1 *dev, 1351 size_t numDisplays, hwc_display_contents_1_t** displays) 1352{ 1353 if (!numDisplays || !displays) 1354 return 0; 1355 1356 exynos5_hwc_composer_device_1_t *pdev = 1357 (exynos5_hwc_composer_device_1_t *)dev; 1358 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 1359 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 1360 1361 if (fimd_contents) { 1362 bool hdmi_mirroring = pdev->hdmi_enabled && !hdmi_contents; 1363 int err = exynos5_set_fimd(pdev, fimd_contents, hdmi_mirroring); 1364 if (err) 1365 return err; 1366 } 1367 1368 if (hdmi_contents) { 1369 if (!pdev->hdmi_enabled) { 1370 ALOGE("HDMI disabled; can't set contents of external display"); 1371 return -EINVAL; 1372 } 1373 int err = exynos5_set_hdmi(pdev, hdmi_contents); 1374 if (err) 1375 return err; 1376 } 1377 1378 return 0; 1379} 1380 1381static void exynos5_registerProcs(struct hwc_composer_device_1* dev, 1382 hwc_procs_t const* procs) 1383{ 1384 struct exynos5_hwc_composer_device_1_t* pdev = 1385 (struct exynos5_hwc_composer_device_1_t*)dev; 1386 pdev->procs = procs; 1387} 1388 1389static int exynos5_query(struct hwc_composer_device_1* dev, int what, int *value) 1390{ 1391 struct exynos5_hwc_composer_device_1_t *pdev = 1392 (struct exynos5_hwc_composer_device_1_t *)dev; 1393 1394 switch (what) { 1395 case HWC_BACKGROUND_LAYER_SUPPORTED: 1396 // we support the background layer 1397 value[0] = 1; 1398 break; 1399 case HWC_VSYNC_PERIOD: 1400 // vsync period in nanosecond 1401 value[0] = pdev->vsync_period; 1402 break; 1403 default: 1404 // unsupported query 1405 return -EINVAL; 1406 } 1407 return 0; 1408} 1409 1410static int exynos5_eventControl(struct hwc_composer_device_1 *dev, int dpy, 1411 int event, int enabled) 1412{ 1413 struct exynos5_hwc_composer_device_1_t *pdev = 1414 (struct exynos5_hwc_composer_device_1_t *)dev; 1415 1416 switch (event) { 1417 case HWC_EVENT_VSYNC: 1418 __u32 val = !!enabled; 1419 int err = ioctl(pdev->fd, S3CFB_SET_VSYNC_INT, &val); 1420 if (err < 0) { 1421 ALOGE("vsync ioctl failed"); 1422 return -errno; 1423 } 1424 1425 return 0; 1426 } 1427 1428 return -EINVAL; 1429} 1430 1431static void handle_hdmi_uevent(struct exynos5_hwc_composer_device_1_t *pdev, 1432 const char *buff, int len) 1433{ 1434 const char *s = buff; 1435 s += strlen(s) + 1; 1436 1437 while (*s) { 1438 if (!strncmp(s, "SWITCH_STATE=", strlen("SWITCH_STATE="))) 1439 pdev->hdmi_hpd = atoi(s + strlen("SWITCH_STATE=")) == 1; 1440 1441 s += strlen(s) + 1; 1442 if (s - buff >= len) 1443 break; 1444 } 1445 1446 if (pdev->hdmi_hpd) { 1447 if (hdmi_get_config(pdev)) { 1448 ALOGE("Error reading HDMI configuration"); 1449 pdev->hdmi_hpd = false; 1450 return; 1451 } 1452 } 1453 1454 ALOGV("HDMI HPD changed to %s", pdev->hdmi_hpd ? "enabled" : "disabled"); 1455 if (pdev->hdmi_hpd) 1456 ALOGI("HDMI Resolution changed to %dx%d", pdev->hdmi_h, pdev->hdmi_w); 1457 1458 /* hwc_dev->procs is set right after the device is opened, but there is 1459 * still a race condition where a hotplug event might occur after the open 1460 * but before the procs are registered. */ 1461 if (pdev->procs) 1462 pdev->procs->invalidate(pdev->procs); 1463} 1464 1465static void handle_vsync_event(struct exynos5_hwc_composer_device_1_t *pdev) 1466{ 1467 if (!pdev->procs) 1468 return; 1469 1470 int err = lseek(pdev->vsync_fd, 0, SEEK_SET); 1471 if (err < 0) { 1472 ALOGE("error seeking to vsync timestamp: %s", strerror(errno)); 1473 return; 1474 } 1475 1476 char buf[4096]; 1477 err = read(pdev->vsync_fd, buf, sizeof(buf)); 1478 if (err < 0) { 1479 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1480 return; 1481 } 1482 buf[sizeof(buf) - 1] = '\0'; 1483 1484 errno = 0; 1485 uint64_t timestamp = strtoull(buf, NULL, 0); 1486 if (!errno) 1487 pdev->procs->vsync(pdev->procs, 0, timestamp); 1488} 1489 1490static void *hwc_vsync_thread(void *data) 1491{ 1492 struct exynos5_hwc_composer_device_1_t *pdev = 1493 (struct exynos5_hwc_composer_device_1_t *)data; 1494 char uevent_desc[4096]; 1495 memset(uevent_desc, 0, sizeof(uevent_desc)); 1496 1497 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); 1498 1499 uevent_init(); 1500 1501 char temp[4096]; 1502 int err = read(pdev->vsync_fd, temp, sizeof(temp)); 1503 if (err < 0) { 1504 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1505 return NULL; 1506 } 1507 1508 struct pollfd fds[2]; 1509 fds[0].fd = pdev->vsync_fd; 1510 fds[0].events = POLLPRI; 1511 fds[1].fd = uevent_get_fd(); 1512 fds[1].events = POLLIN; 1513 1514 while (true) { 1515 int err = poll(fds, 2, -1); 1516 1517 if (err > 0) { 1518 if (fds[0].revents & POLLPRI) { 1519 handle_vsync_event(pdev); 1520 } 1521 else if (fds[1].revents & POLLIN) { 1522 int len = uevent_next_event(uevent_desc, 1523 sizeof(uevent_desc) - 2); 1524 1525 bool hdmi = !strcmp(uevent_desc, 1526 "change@/devices/virtual/switch/hdmi"); 1527 if (hdmi) 1528 handle_hdmi_uevent(pdev, uevent_desc, len); 1529 } 1530 } 1531 else if (err == -1) { 1532 if (errno == EINTR) 1533 break; 1534 ALOGE("error in vsync thread: %s", strerror(errno)); 1535 } 1536 } 1537 1538 return NULL; 1539} 1540 1541static int exynos5_blank(struct hwc_composer_device_1 *dev, int dpy, int blank) 1542{ 1543 struct exynos5_hwc_composer_device_1_t *pdev = 1544 (struct exynos5_hwc_composer_device_1_t *)dev; 1545 1546 int fb_blank = blank ? FB_BLANK_POWERDOWN : FB_BLANK_UNBLANK; 1547 int err = ioctl(pdev->fd, FBIOBLANK, fb_blank); 1548 if (err < 0) { 1549 ALOGE("%sblank ioctl failed", blank ? "" : "un"); 1550 return -errno; 1551 } 1552 1553 if (pdev->hdmi_hpd) { 1554 if (blank && !pdev->hdmi_blanked) 1555 hdmi_disable(pdev); 1556 pdev->hdmi_blanked = !!blank; 1557 } 1558 1559 return 0; 1560} 1561 1562static void exynos5_dump(hwc_composer_device_1* dev, char *buff, int buff_len) 1563{ 1564 if (buff_len <= 0) 1565 return; 1566 1567 struct exynos5_hwc_composer_device_1_t *pdev = 1568 (struct exynos5_hwc_composer_device_1_t *)dev; 1569 1570 android::String8 result; 1571 1572 result.appendFormat(" hdmi_enabled=%u\n", pdev->hdmi_enabled); 1573 if (pdev->hdmi_enabled) 1574 result.appendFormat(" w=%u, h=%u\n", pdev->hdmi_w, pdev->hdmi_h); 1575 result.append( 1576 " type | handle | color | blend | format | position | size | gsc \n" 1577 "----------+----------|----------+-------+--------+---------------+---------------------\n"); 1578 // 8_______ | 8_______ | 8_______ | 5____ | 6_____ | [5____,5____] | [5____,5____] | 3__ \n" 1579 1580 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1581 struct s3c_fb_win_config &config = pdev->last_config[i]; 1582 if (config.state == config.S3C_FB_WIN_STATE_DISABLED) { 1583 result.appendFormat(" %8s | %8s | %8s | %5s | %6s | %13s | %13s", 1584 "DISABLED", "-", "-", "-", "-", "-", "-"); 1585 } 1586 else { 1587 if (config.state == config.S3C_FB_WIN_STATE_COLOR) 1588 result.appendFormat(" %8s | %8s | %8x | %5s | %6s", "COLOR", 1589 "-", config.color, "-", "-"); 1590 else 1591 result.appendFormat(" %8s | %8x | %8s | %5x | %6x", 1592 pdev->last_fb_window == i ? "FB" : "OVERLAY", 1593 intptr_t(pdev->last_handles[i]), 1594 "-", config.blending, config.format); 1595 1596 result.appendFormat(" | [%5d,%5d] | [%5u,%5u]", config.x, config.y, 1597 config.w, config.h); 1598 } 1599 if (pdev->last_gsc_map[i].mode == exynos5_gsc_map_t::GSC_NONE) 1600 result.appendFormat(" | %3s", "-"); 1601 else 1602 result.appendFormat(" | %3d", 1603 AVAILABLE_GSC_UNITS[pdev->last_gsc_map[i].idx]); 1604 result.append("\n"); 1605 } 1606 1607 strlcpy(buff, result.string(), buff_len); 1608} 1609 1610static int exynos5_getDisplayConfigs(struct hwc_composer_device_1 *dev, 1611 int disp, uint32_t *configs, size_t *numConfigs) 1612{ 1613 struct exynos5_hwc_composer_device_1_t *pdev = 1614 (struct exynos5_hwc_composer_device_1_t *)dev; 1615 1616 if (*numConfigs == 0) 1617 return 0; 1618 1619 if (disp == HWC_DISPLAY_PRIMARY) { 1620 configs[0] = 0; 1621 *numConfigs = 1; 1622 return 0; 1623 } else if (disp == HWC_DISPLAY_EXTERNAL) { 1624 if (!pdev->hdmi_enabled) { 1625 return -EINVAL; 1626 } 1627 1628 int err = hdmi_get_config(pdev); 1629 if (err) { 1630 return -EINVAL; 1631 } 1632 1633 configs[0] = 0; 1634 *numConfigs = 1; 1635 return 0; 1636 } 1637 1638 return -EINVAL; 1639} 1640 1641static int32_t exynos5_fimd_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1642 const uint32_t attribute) 1643{ 1644 switch(attribute) { 1645 case HWC_DISPLAY_VSYNC_PERIOD: 1646 return pdev->vsync_period; 1647 1648 case HWC_DISPLAY_WIDTH: 1649 return pdev->xres; 1650 1651 case HWC_DISPLAY_HEIGHT: 1652 return pdev->yres; 1653 1654 case HWC_DISPLAY_DPI_X: 1655 return pdev->xdpi; 1656 1657 case HWC_DISPLAY_DPI_Y: 1658 return pdev->ydpi; 1659 1660 default: 1661 ALOGE("unknown display attribute %u", attribute); 1662 return -EINVAL; 1663 } 1664} 1665 1666static int32_t exynos5_hdmi_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1667 const uint32_t attribute) 1668{ 1669 switch(attribute) { 1670 case HWC_DISPLAY_VSYNC_PERIOD: 1671 return pdev->vsync_period; 1672 1673 case HWC_DISPLAY_WIDTH: 1674 return pdev->hdmi_w; 1675 1676 case HWC_DISPLAY_HEIGHT: 1677 return pdev->hdmi_h; 1678 1679 case HWC_DISPLAY_DPI_X: 1680 case HWC_DISPLAY_DPI_Y: 1681 return 0; // unknown 1682 1683 default: 1684 ALOGE("unknown display attribute %u", attribute); 1685 return -EINVAL; 1686 } 1687} 1688 1689static int exynos5_getDisplayAttributes(struct hwc_composer_device_1 *dev, 1690 int disp, uint32_t config, const uint32_t *attributes, int32_t *values) 1691{ 1692 struct exynos5_hwc_composer_device_1_t *pdev = 1693 (struct exynos5_hwc_composer_device_1_t *)dev; 1694 1695 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; i++) { 1696 if (disp == HWC_DISPLAY_PRIMARY) 1697 values[i] = exynos5_fimd_attribute(pdev, attributes[i]); 1698 else if (disp == HWC_DISPLAY_EXTERNAL) 1699 values[i] = exynos5_hdmi_attribute(pdev, attributes[i]); 1700 else { 1701 ALOGE("unknown display type %u", disp); 1702 return -EINVAL; 1703 } 1704 } 1705 1706 return 0; 1707} 1708 1709static int exynos5_close(hw_device_t* device); 1710 1711static int exynos5_open(const struct hw_module_t *module, const char *name, 1712 struct hw_device_t **device) 1713{ 1714 int ret; 1715 int refreshRate; 1716 int sw_fd; 1717 1718 if (strcmp(name, HWC_HARDWARE_COMPOSER)) { 1719 return -EINVAL; 1720 } 1721 1722 struct exynos5_hwc_composer_device_1_t *dev; 1723 dev = (struct exynos5_hwc_composer_device_1_t *)malloc(sizeof(*dev)); 1724 memset(dev, 0, sizeof(*dev)); 1725 1726 if (hw_get_module(GRALLOC_HARDWARE_MODULE_ID, 1727 (const struct hw_module_t **)&dev->gralloc_module)) { 1728 ALOGE("failed to get gralloc hw module"); 1729 ret = -EINVAL; 1730 goto err_get_module; 1731 } 1732 1733 if (gralloc_open((const hw_module_t *)dev->gralloc_module, 1734 &dev->alloc_device)) { 1735 ALOGE("failed to open gralloc"); 1736 ret = -EINVAL; 1737 goto err_get_module; 1738 } 1739 1740 dev->fd = open("/dev/graphics/fb0", O_RDWR); 1741 if (dev->fd < 0) { 1742 ALOGE("failed to open framebuffer"); 1743 ret = dev->fd; 1744 goto err_open_fb; 1745 } 1746 1747 struct fb_var_screeninfo info; 1748 if (ioctl(dev->fd, FBIOGET_VSCREENINFO, &info) == -1) { 1749 ALOGE("FBIOGET_VSCREENINFO ioctl failed: %s", strerror(errno)); 1750 ret = -errno; 1751 goto err_ioctl; 1752 } 1753 1754 refreshRate = 1000000000000LLU / 1755 ( 1756 uint64_t( info.upper_margin + info.lower_margin + info.yres ) 1757 * ( info.left_margin + info.right_margin + info.xres ) 1758 * info.pixclock 1759 ); 1760 1761 if (refreshRate == 0) { 1762 ALOGW("invalid refresh rate, assuming 60 Hz"); 1763 refreshRate = 60; 1764 } 1765 1766 dev->xres = 2560; 1767 dev->yres = 1600; 1768 dev->xdpi = 1000 * (info.xres * 25.4f) / info.width; 1769 dev->ydpi = 1000 * (info.yres * 25.4f) / info.height; 1770 dev->vsync_period = 1000000000 / refreshRate; 1771 1772 ALOGV("using\n" 1773 "xres = %d px\n" 1774 "yres = %d px\n" 1775 "width = %d mm (%f dpi)\n" 1776 "height = %d mm (%f dpi)\n" 1777 "refresh rate = %d Hz\n", 1778 dev->xres, dev->yres, info.width, dev->xdpi / 1000.0, 1779 info.height, dev->ydpi / 1000.0, refreshRate); 1780 1781 dev->hdmi_mixer0 = open("/dev/v4l-subdev7", O_RDWR); 1782 if (dev->hdmi_layer0 < 0) { 1783 ALOGE("failed to open hdmi mixer0 subdev"); 1784 ret = dev->hdmi_layer0; 1785 goto err_ioctl; 1786 } 1787 1788 dev->hdmi_layer0 = open("/dev/video16", O_RDWR); 1789 if (dev->hdmi_layer0 < 0) { 1790 ALOGE("failed to open hdmi layer0 device"); 1791 ret = dev->hdmi_layer0; 1792 goto err_mixer0; 1793 } 1794 1795 dev->hdmi_layer1 = open("/dev/video17", O_RDWR); 1796 if (dev->hdmi_layer1 < 0) { 1797 ALOGE("failed to open hdmi layer1 device"); 1798 ret = dev->hdmi_layer1; 1799 goto err_hdmi0; 1800 } 1801 1802 dev->vsync_fd = open("/sys/devices/platform/exynos5-fb.1/vsync", O_RDONLY); 1803 if (dev->vsync_fd < 0) { 1804 ALOGE("failed to open vsync attribute"); 1805 ret = dev->vsync_fd; 1806 goto err_hdmi1; 1807 } 1808 1809 sw_fd = open("/sys/class/switch/hdmi/state", O_RDONLY); 1810 if (sw_fd) { 1811 char val; 1812 if (read(sw_fd, &val, 1) == 1 && val == '1') { 1813 dev->hdmi_hpd = true; 1814 if (hdmi_get_config(dev)) { 1815 ALOGE("Error reading HDMI configuration"); 1816 dev->hdmi_hpd = false; 1817 } 1818 } 1819 } 1820 1821 dev->base.common.tag = HARDWARE_DEVICE_TAG; 1822 dev->base.common.version = HWC_DEVICE_API_VERSION_1_1; 1823 dev->base.common.module = const_cast<hw_module_t *>(module); 1824 dev->base.common.close = exynos5_close; 1825 1826 dev->base.prepare = exynos5_prepare; 1827 dev->base.set = exynos5_set; 1828 dev->base.eventControl = exynos5_eventControl; 1829 dev->base.blank = exynos5_blank; 1830 dev->base.query = exynos5_query; 1831 dev->base.registerProcs = exynos5_registerProcs; 1832 dev->base.dump = exynos5_dump; 1833 dev->base.getDisplayConfigs = exynos5_getDisplayConfigs; 1834 dev->base.getDisplayAttributes = exynos5_getDisplayAttributes; 1835 1836 *device = &dev->base.common; 1837 1838 ret = pthread_create(&dev->vsync_thread, NULL, hwc_vsync_thread, dev); 1839 if (ret) { 1840 ALOGE("failed to start vsync thread: %s", strerror(ret)); 1841 ret = -ret; 1842 goto err_vsync; 1843 } 1844 1845 char value[PROPERTY_VALUE_MAX]; 1846 property_get("debug.hwc.force_gpu", value, "0"); 1847 dev->force_gpu = atoi(value); 1848 1849 return 0; 1850 1851err_vsync: 1852 close(dev->vsync_fd); 1853err_mixer0: 1854 close(dev->hdmi_mixer0); 1855err_hdmi1: 1856 close(dev->hdmi_layer0); 1857err_hdmi0: 1858 close(dev->hdmi_layer1); 1859err_ioctl: 1860 close(dev->fd); 1861err_open_fb: 1862 gralloc_close(dev->alloc_device); 1863err_get_module: 1864 free(dev); 1865 return ret; 1866} 1867 1868static int exynos5_close(hw_device_t *device) 1869{ 1870 struct exynos5_hwc_composer_device_1_t *dev = 1871 (struct exynos5_hwc_composer_device_1_t *)device; 1872 pthread_kill(dev->vsync_thread, SIGTERM); 1873 pthread_join(dev->vsync_thread, NULL); 1874 for (size_t i = 0; i < NUM_GSC_UNITS; i++) { 1875 if (dev->gsc[i].gsc) 1876 exynos_gsc_destroy(dev->gsc[i].gsc); 1877 for (size_t j = 0; i < NUM_GSC_DST_BUFS; j++) 1878 if (dev->gsc[i].dst_buf[j]) 1879 dev->alloc_device->free(dev->alloc_device, dev->gsc[i].dst_buf[j]); 1880 } 1881 gralloc_close(dev->alloc_device); 1882 close(dev->vsync_fd); 1883 close(dev->hdmi_mixer0); 1884 close(dev->hdmi_layer0); 1885 close(dev->hdmi_layer1); 1886 close(dev->fd); 1887 return 0; 1888} 1889 1890static struct hw_module_methods_t exynos5_hwc_module_methods = { 1891 open: exynos5_open, 1892}; 1893 1894hwc_module_t HAL_MODULE_INFO_SYM = { 1895 common: { 1896 tag: HARDWARE_MODULE_TAG, 1897 module_api_version: HWC_MODULE_API_VERSION_0_1, 1898 hal_api_version: HARDWARE_HAL_API_VERSION, 1899 id: HWC_HARDWARE_MODULE_ID, 1900 name: "Samsung exynos5 hwcomposer module", 1901 author: "Google", 1902 methods: &exynos5_hwc_module_methods, 1903 } 1904}; 1905