History log of /external/mesa3d/src/mesa/drivers/dri/i915/intel_span.c
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67e9ae856355be532455c1cf1211d59b3a4c5992 27-Aug-2012 Eric Anholt <eric@anholt.net> i965: Disable the swrast context setup on GL 3.1 core.

I've reviewed the code, and the swrast callsites remaining are all in
drawpixels/copypixels/bitmap/accum, or _swrast_BlitFramebuffer that shouldn't
be hit. A piglit run with the context setup disabled on legacy GL and GLES2
showed regressions only in the copypixels and drawpixels tests.

If the context type is forced, this reduces the shader_runner maximum heap
size for glsl-algebraic-add-add-1.shader_test from 15,137,496b to 4,165,376b.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
bfae8650ec25d9f03ed1f58435325fd9b62b8da8 26-Aug-2012 Eric Anholt <eric@anholt.net> i965: Move depth resolve for span fallbacks to a simpler place.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
707f242c4be9bd6ea9140b9a7a7673ae5e4e191d 26-Aug-2012 Eric Anholt <eric@anholt.net> i965: Drop manual hiz resolves in span rendering.

swrast uses MapRenderbuffer, which leads to intel_miptree_map, which does the
depth resolve.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
f172eae8b23d0612865895c52af745021ae20a4c 02-Mar-2012 Daniel Vetter <daniel.vetter@ffwll.ch> i965: fixup W-tile offset computation to take swizzling into account

There's even a comment in the code containing the right swizzling
computations!

Previously this has not been noticed because we need to manually
enabled swizzling on snb/ivb (kernel 3.4 will do that) and we
don't use the separate stencil on ilk (where the bios enables
swizzling). This fixes

piglit ./bin/fbo-stencil readpixels GL_DEPTH32F_STENCIL8 -auto

on recent drm-intel-next kernels.

Also remove the comment about ivb, it's stale now.

Swizzling detection is done by allocating a temporary x-tiled
buffer object. Unfortunately kernels before v3.2 lie on snb/ivb
because they claim that swizzling is enable, but it isn't. The
kernel commit that fixes this for backport to pre-v3.2 is

commit acc83eb5a1e0ae7dbbf89ca2a1a943ade224bb84
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Mon Sep 12 20:49:16 2011 +0200

drm/i915: fix swizzling on gen6+

But if the kernel doesn't lie, this now works on swizzling and
not swizzling machines.

NOTE: This is a candidate for the 8.0 branch.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
89bb19adb08caaefc01e613e9bbfbdd1f366ddab 19-Jan-2012 Brian Paul <brianp@vmware.com> intel: use swrast code to map/unmap renderbuffers for swrast rendering
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
1839a7fc9faae81d32ffc0cdc908b933f4524e28 16-Jan-2012 Brian Paul <brianp@vmware.com> intel: remove intel_span_supports_format()

It always returned True.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
9f8ed9d66298e2dc5dff508e3ea723469fe06d93 16-Jan-2012 Brian Paul <brianp@vmware.com> intel: derive intel_renderbuffer from swrast_renderbuffer

Drivers that rely on swrast need to do this, as with swrast_texture_image.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
1e1b5cb01a10e39d01923e3c7e989c44210950cd 16-Jan-2012 Brian Paul <brianp@vmware.com> mesa: remove gl_renderbuffer:RowStride field
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
41869c49421141807ab71cabca4c8a07611f6a64 16-Jan-2012 Brian Paul <brianp@vmware.com> intel: remove most of the span Get/PutRow code
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
7d1ddec92168e9b6ead0da80b18364a75f9a85e6 16-Jan-2012 Brian Paul <brianp@vmware.com> mesa: use gl_renderbuffer::Map for all depth/stencil accesses

Instead of using the obsolete gl_renderbuffer::Data field.
Color buffer are still accessed through GetRow/PutRow().
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
14da67d9b9b9e30740ef1687c3952a0b5e8b0a54 16-Jan-2012 Brian Paul <brianp@vmware.com> intel: make intel_renderbuffer_map/unmap() static
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
d0dc75c000d5af92648c7de901756400672b8447 06-Dec-2011 Brian Paul <brianp@vmware.com> mesa/drivers: use new swrast renderbuffer functions

Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
0a3c895f341ae458b09dcdc9cbd674600366a925 01-Dec-2011 Brian Paul <brianp@vmware.com> mesa: rename MESA_FORMAT_RG88 to MESA_FORMAT_GR88

To better reflect the component ordering and be consistent with other
format names.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
622bae07a5da91bc966d173fd6df92a640e4f574 16-Nov-2011 Chad Versace <chad.versace@linux.intel.com> intel: Resolve buffers in intelSpanRenderStart

Resolve all buffers that will be mapped by intelSpanRenderStart. This
comprises resolving the depth buffer of each enabled texture and of the
read and draw buffers.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
1eede4aa8771c058bc560123d4b7c5625e23c8b6 16-Nov-2011 Chad Versace <chad.versace@linux.intel.com> intel: Refactor intelSpanRenderStart

Factor the mapping loops from intelSpanRenderStart() into
intel_span_map_buffers(). This in preparation for the next commit,
which resolves the buffers before mapping.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
da2816a45e6e3a33246a341fee72e6f893f315d9 16-Nov-2011 Chad Versace <chad.versace@linux.intel.com> intel: Replace intel_renderbuffer::region with a miptree [v3]

Essentially, this patch just globally substitutes `irb->region` with
`irb->mt->region` and then does some minor cleanups to avoid segfaults
and other problems.

This is in preparation for
1. Fixing scatter/gather for mipmapped separate stencil textures.
2. Supporting HiZ for mipmapped depth textures.

As a nice benefit, this lays down some preliminary groundwork for easily
texturing from any renderbuffer, even those of the window system.

A future commit will replace intel_mipmap_tree::hiz_region with a miptree.

v2:
- Return early in intel_process_dri2_buffer_*() if region allocation
fails.
- Fix double semicolon.
- Fix miptree reference leaks in the following functions:
intel_process_dri2_buffer_with_separate_stencil()
intel_image_target_renderbuffer_storage()

v3:
- [anholt] Fix check for hiz allocation failure. Replace
``if (!irb->mt)` with ``if(!irb->mt->hiz_region)``.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
af35a3523df7f555427de4835ae092d1836c3c95 14-Nov-2011 Chad Versace <chad.versace@linux.intel.com> intel: Fix swrast_render_start() for depthstencil buffers with separate stencil

1. Don't map the depthstencil buffer twice

Place a guard in intel_renderbuffer_map() to prevent a renderbuffer
from being mapped twice. This happened if a single buffer was attached to
the framebuffer's depth and stencil attachment points. (Interestingly,
because intel_map_renderbuffer_gtt() is idempotent, the double mapping did
not cause bugs for depthstencil buffers *without* separate stencil).

2. Stop overriding gl_framebuffer::_DepthBuffer,_StencilBuffer

Normally, if a depthstencil buffer is attached to the framebuffer's
depth attachment point, then _mesa_update_framebuffer() installs
a wrapper depth renderbuffer at gl_framebuffer::_DepthBuffer. Ditto for
the stencil attachment point and gl_framebuffer::_StencilBuffer

A depthstencil intel_renderbuffer with separate stencil contains hidden
depth and stencil renderbuffers, which are the *real* renderbuffers. In
order to force swrast to work, we were installing, in
brw_update_draw_buffer(), the hidden renderbuffers at
gl_framebuffer::_DepthBuffer and _StencilBuffer, thus overriding the
behavior of _mesa_update_framebuffer(). However, now that
intel_renderbuffer_map() is implemented with MapRenderbuffer(),
overriding _mesa_update_framebuffer's introduces bugs. This patch
removes the override code.

Fixes several Piglit tests on gen7.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
3d2235e6c76a8a6aef2a14ca57c68403cf056921 17-Nov-2011 Chad Versace <chad.versace@linux.intel.com> intel: Don't use special stencil span accessors

The special stencil span accessors, as set by intel_span_init_funcs.
perform software W detiling. Since intel_renderbuffer_map() now uses
MapRenderbuffer, rb->Data points to an *untiled* stencil buffer.

Fixes several Piglit tests on gen7.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
dc4c3a31c64aae2c3d76ccbd5bf54d04a1d5d041 15-Nov-2011 Chad Versace <chad.versace@linux.intel.com> intel: Simplify stencil detiling arithmetic

When calculating the y offset needed for detiling window system stencil
buffers, replace the term
region->height * 2 + region->height % 2 - 1
with
rb->Height - 1 .

The two terms are incidentally equivalent due to some out-of-date,
incorrect code in the Intel DRI2 glue for DDX. (See
intel_process_dri2_buffer_with_separate_stencil(), line ``buffer_height /=
2;``).

Note: This is a candidate for the 7.11 branch (only the intel_span.c hunk).
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
5365ba19db8e9d714604bb63f037800ba2ff2f4d 11-Nov-2011 Chad Versace <chad.versace@linux.intel.com> intel: Fix software detiling of system stencil buffers

If a window system stencil buffer had a region with odd height, then the
calculated y offset needed for software detiling was off by one. The bug
existed in intel_{map,unmap}_renderbuffer_s8() and in the intel_span.c
accessors.

Fixes the following Piglit tests on gen7:
general/depthstencil-default_fb-readpixels-24_8
general/depthstencil-default_fb-readpixels-FLOAT-and-USHORT

Fixes SIGABRT in the following Piglit tests on gen7:
general/depthstencil-default_fb-blit
general/depthstencil-default_fb-copypixels
general/depthstencil-default_fb-drawpixels-24_8
general/depthstencil-default_fb-drawpixels-FLOAT-and-USHORT

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
42c5552b0eef9c06898d29bb3f5c985f31316250 02-Nov-2011 Eric Anholt <eric@anholt.net> i965: Claim to support rendering to integer FBOs.

We're missing support for the software paths still, but basic
rendering is working.

v2: Override RGB_INT32/UINT32 to not be renderable, since the hardware
can't do it but we do allow texturing from it now. Drop the
DataType override, since the _mesa_problem() isn't in that path
any more.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
b5444a6ebd48a2bf4c258be98aac831636164e10 08-Nov-2011 Eric Anholt <eric@anholt.net> intel: Don't _mesa_problem when asked for an RB of a texturing-only type.

We want to be able to support some formats for texturing that we can't
render to, which means that some choices for RenderbufferStorage end
up being incomplete (for example, L8 currently). For these, where we
don't render to them, we don't want to have to make up an rb->DataType
that's only used for GetRow()/PutRow().
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
bae10c0d2e518f06c3686e04c778f0da73525b4d 11-Oct-2011 Eric Anholt <eric@anholt.net> intel: Use MapRenderbuffer in spans setup.

Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
92054cd94e2188c9f4d56ddf9377c5aeb8a4e64e 11-Oct-2011 Eric Anholt <eric@anholt.net> intel: Add an implementation of MapRenderbuffer.

v2: Add separate stencil S8 W-tile swizzling/deswizzling. Tested for
the swizzling case with env INTEL_SEPARATE_STENCIL=1 INTEL_HIZ=1
./bin/hiz-depth-stencil-test-fbo-d24-s8
v3: Apply Chad's fix for S8 window system buffers.

Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
f8377b411dfe3c879eaab11bb86f509178796bd1 22-Sep-2011 Chad Versace <chad@chad-versace.us> intel: Add 'mode' param to intel_region_map

The 'mode' param is a bitset of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT.

A future commit will perform buffer resolves in intel_region_map(). So,
even though the access mode is irrelevant to the GTT, the extra
information allows us to intelligently avoid unneccessary buffer resolves.

Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
8004a1cb95b8a195f3f4bbaa8d39d2f3297167de 22-Sep-2011 Eric Anholt <eric@anholt.net> intel: Rename region->buffer to region->bo, and remove accessor function.

We call all the other drm_intel_bo pointers in intel/*.h "bo", so this
one was rather out of place.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
f7dbcba280e4397cadb14f230aa925b4143cdde4 18-Jul-2011 Chad Versace <chad@chad-versace.us> intel: Fix stencil buffer to be W tiled

Until now, the stencil buffer was allocated as a Y tiled buffer, because
in several locations the PRM states that it is. However, it is actually
W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
4.5.2.1 W-Major Format:
W-Major Tile Format is used for separate stencil.

The GTT is incapable of W fencing, so we allocate the stencil buffer with
I915_TILING_NONE and decode the tile's layout in software.

This fix touches the following portions of code:
- In intel_allocate_renderbuffer_storage(), allocate the stencil
buffer with I915_TILING_NONE.
- In intel_verify_dri2_has_hiz(), verify that the stencil buffer is
not tiled.
- In the stencil buffer's span functions, the tile's layout must be
decoded in software.

This commit mutually depends on the xf86-video-intel commit
dri: Do not tile stencil buffer
Author: Chad Versace <chad@chad-versace.us>
Date: Mon Jul 18 00:38:00 2011 -0700

On Gen6 with separate stencil enabled, fixes the following Piglit tests:
bugs/fdo23670-drawpix_stencil
general/stencil-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-readpixels
spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-copypixels
spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-readpixels
spec/EXT_packed_depth_stencil/readpixels-24_8

Note: This is a candidate for the 7.11 branch.

Signed-off-by: Chad Versace <chad@chad-versace.us>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
39d0e3632a4ccb10f2ce6578151e854ba52d3c0e 16-Jun-2011 Chad Versace <chad@chad-versace.us> intel: Add fields to intel_renderbuffer for unwrapping packed depth/stencil buffers

Add the following fields:
intel_renderbuffer.wrapped_depth;
intel_renderbuffer.wrapped_stencil

If the intel_context is using separate stencil and the renderbuffer has
a packed depth/stencil format, then wrapped_depth and wrapped_stencil are
the real renderbuffers.

Alter the following functions to accomodate the wrapped buffers:
intel_delete_renderbuffer
intel_draw_buffer
intel_get_renderbuffer
intel_renderbuffer_map
intel_renderbuffer_unmap

Subsequent commits allocate renderbuffer storage for wrapped_depth and
wrapped_stencil.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
8875dd58719b978283e89acf04422a4eaf9b021d 14-Jun-2011 Chad Versace <chad@chad-versace.us> intel: Fix typo in intel_offset_S8 comments

Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
ef0d548838c3da476596ee4dc983cc02b4f67b7b 01-Jun-2011 Eric Anholt <eric@anholt.net> intel: Do the drawable x/y offset in intel_renderbuffer_map() for spans.

We were mapping the renderbuffer once, then walking over all the
buffers to map just the texture ones using the other texture mapping
function that handled the x/y offset to the image in the region. But
then we would go and overwrite *those* mappings with the original
mappings for depth/stencil, which was wrong.

Instead, just walk over the attachments once and map the attachments.
Wasn't that easy?
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
fb60e2061b1f2f58a65e908e864704c234b300b0 01-Jun-2011 Eric Anholt <eric@anholt.net> intel: Use rb->Data and rb->RowStride to handle spans Y flipping.

This is already pointing at 0 or Height - 1 and with an appropriate
pitch, so no need to recompute those values per customization of the
spans code. Cuts 3 out of 21kb of the compiled size.

Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
ff99103c0a8a1b9e76fff80f9753d2124da27da2 01-Jun-2011 Chad Versace <chad@chad-versace.us> intel: Define span functions for S8 renderbuffers

Since the stencil buffer is interleaved, the generic Mesa renderbuffer
accessors do not suffice. Custom span functions are necessary.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
f29bc77572eb68c6e93371a5c7a9c4e4d1f9ee35 19-May-2011 Ian Romanick <ian.d.romanick@intel.com> intel: Remove unused NO_TILE macro

Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
87478cd6e3e6349abc2688b390f8845d1e21af3d 15-Apr-2011 Eric Anholt <eric@anholt.net> intel: Add support for ARB_texture_float.

For 1 and 2-channel formats the hardware only supports rendering to R
and RG. To do I and L render targets we just call them R and
everything works out. For A, we would need to rewrite the CC to do
the alpha channel's blending on color instead, and send the fragment
alpha down the red channel. For LA, there doesn't seem to be any
hope, because we can't do independent color/alpha blending while
treating the LA surface as RG.

Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
73f07004811a2522b45179c74cd9a6d6d2e5c578 16-Apr-2011 Eric Anholt <eric@anholt.net> intel: Use mesa core's R8, RG88, R16, RG1616 RB accessors.

Fixes:
ARB_texture_rg/fbo-alphatest-formats

Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
0778fdb002b000e241b042ad65b6da6dd8480454 15-Apr-2011 Eric Anholt <eric@anholt.net> intel: Use Mesa core's renderbuffer accessors for depth.

Since we're using GTT mappings now (no manual detiling), there's
really nothing special to accessing these buffers, other than needing
the new RowStride field of gl_renderbuffer to accomodate padding.

Reduces the driver size by 2.7kb, and improves glean depthStencil
performance 3-10x (!)

Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
e339b669a14f37698b842c0c51c1f5e4001ef12f 10-Dec-2010 Eric Anholt <eric@anholt.net> intel: Add a couple of helper functions to reduce rb code duplication.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
28bab24e1698843e27d27204a1117066e7ffeabb 10-Dec-2010 Eric Anholt <eric@anholt.net> intel: Add spans code for the ARB_texture_rg support.

This starts spantmp2.h down the path of using MESA_FORMAT_* for
specifying the format instead of the crazy GL format/type combo.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
f9995b30756140724f41daf963fa06167912be7f 12-Oct-2010 Kristian Høgsberg <krh@bitplanet.net> Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
1946b81e700fbb266294b8c1cb0d29ced84bf647 25-Sep-2010 Eric Anholt <eric@anholt.net> i965: Add support for rendering to SARGB8 FBOs.

Tested with fbo-generatemipmap-formats GL_EXT_texture_srgb. The test
still fails on SLA8, though.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
6dd6830e6f87044b9ede10d324574cfe1f66a751 15-Jun-2010 Eric Anholt <eric@anholt.net> intel: Finalize the miptree before mapping it for fallbacks.

Fixes segfault in mipmap_view.c demo. Bug #27212.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
638342858894293246400d95a90d153c7f66719a 25-May-2010 Eric Anholt <eric@anholt.net> i965: Add support for GL_ALPHA framebuffer objects.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
c4775a27e3aaa2006b98f225387499b79bc609ef 10-May-2010 Kristian Høgsberg <krh@bitplanet.net> intel: Drop intelFlush()

Now that intel_flush() deosn't use the needs_mi_flush argument, we can
finally drop one of the two flush functions.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
c479a20fced2f4162092e96491da3d310fed8648 16-Mar-2010 Eric Anholt <eric@anholt.net> intel: Rename the z24_x8 depth spans to z24_s8 since they do stencil too.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
5782b2a968bb979b651e49bb5fc4162faa842050 16-Mar-2010 Eric Anholt <eric@anholt.net> i965: Fix readpixels from ReadBuffer != DrawBuffer.

Fixes piglit fbo-readdrawpix.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
bb35000b4b6dfe60048b2f5d60bc102c4a7fd791 05-Mar-2010 Eric Anholt <eric@anholt.net> intel: Remove non-kernel-exec-fencing support.

Shaves 60k off the driver from removing the broken spans code. This
means we now require 2.6.29, which seems fair given that it's a year
old and we've removed support for non-KMS already in the last release
of 2D.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
7cbc4c07ee85782d5da3e2db3c4e072ca498ff07 05-Mar-2010 Eric Anholt <eric@anholt.net> intel: Remove the unused s8 spans code. Not hit during no_rast piglit.

Shaves 5.5k off of the driver.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
32f2fd1c5d6088692551c80352b7d6fa35b0cd09 19-Feb-2010 Kristian Høgsberg <krh@bitplanet.net> Replace _mesa_malloc, _mesa_calloc and _mesa_free with plain libc versions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
d449627829e1a4a3250a1a723af2f4e3cd5fd194 18-Feb-2010 Kristian Høgsberg <krh@bitplanet.net> intel: Implement the DRI2 invalidate function properly

This uses a stamp mechanisms to mark the DRI drawable as invalid.
Instead of immediately updating the buffers we just bump the drawable
stamp and call out to DRI2GetBuffers "later".

"Later" used to be at LOCK_HARDWARE time, and this patch brings back
callouts at the points where we used to call LOCK_HARDWARE. A new function,
intel_prepare_render(), is called where we used to call LOCK_HARDWARE,
and if the buffers are invalid, we call out to DRI2GetBuffers there.

This lets us invalidate buffers only when notified instead of on
every glViewport() call. If the loader calls the DRI invalidate
entrypoint, we disable viewport triggered buffer invalidation.

Additionally, we can clean up the old viewport mechanism a bit,
since we can just invalidate the buffers and not worry about
reentrancy and whatnot.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
ee454f0ba422e37157c7ac774884474bcc6c9d34 27-Jan-2010 Eric Anholt <eric@anholt.net> intel: Remove DRI1 junk from spans code.

This reduces the driver size by over 1%.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
01dc463e5d5513e059eea601710cd4babe02610d 02-Jan-2010 Kristian Høgsberg <krh@bitplanet.net> intel: Drop LOCK/UNLOCK_HARDWARE()
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
a087eb590d780cb82b49464e05ffc85123adce7e 11-Dec-2009 Brian Paul <brianp@vmware.com> Merge branch 'mesa_7_7_branch'

Conflicts:
src/gallium/state_trackers/xorg/xorg_xv.c
src/mesa/drivers/dri/intel/intel_span.c
e624b77eb2d594cde053c73a530836e05227126a 09-Dec-2009 Ian Romanick <ian.d.romanick@intel.com> intel: Remove ARGB internal_format == GL_RGB hacks

Now that XRGB is supported, we don't need to hack around cases of an RGBA
format buffer with an internal format of GL_RGB.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
4f2b2032f46939b6056f837a086e73f0417183fc 09-Dec-2009 Ian Romanick <ian.d.romanick@intel.com> intel: Use spantmp2 GL_BGR / GL_UNSIGNED_INT_8_8_8_8_REV for XRGB8888
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
3078bd136d6ee1d9ad16b4c834cad23b005304a4 08-Dec-2009 Ian Romanick <ian.d.romanick@intel.com> intel: Axe intel_renderbuffer::texformat

Since the texformat branch merge, the value of intel_renderbuffer::texformat
is just a copy of gl_renderbuffer::Format.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8 18-Nov-2009 Eric Anholt <eric@anholt.net> intel: Remove non-GEM support.

This really isn't supported at this point. GEM's been in the kernel for
a year, and the fake bufmgr never really worked.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
bb2dd50be00000b66218bc6a9e6be8de70b31493 04-Nov-2009 Eric Anholt <eric@anholt.net> intel: Remove obsolete comment about GEM in the spans code.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
bcbfda71b03303d3f008a6f3cf8cb7d9667bf8d2 02-Nov-2009 Brian Paul <brianp@vmware.com> intel: avoid unnecessary front buffer flushing/updating

Before, if we just called glXMakeCurrent() and didn't render anything we'd
still trigger a flushFrontBuffer() call.

Now only set the intel->front_buffer_dirty field at state validation time
just before we draw something.

NOTE: additional calls to intel_check_front_buffer_rendering() might be
needed if I missed some rendering paths.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
7c8bed62e0165a0be3363f7abf81bf9e30341e00 30-Oct-2009 Eric Anholt <eric@anholt.net> intel: Use GTT mapping when available for swrast.

This improves piglit quick.tests runtime from 19:33 minutes to 6:06 on
my GM45. It should also hide most of the A17 swizzling issues, though
they'll still exist when swapping occurs (which is the kernel's problem
either way).
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
21a3a79371c34b20fb3de2af0f031856468bdfed 30-Oct-2009 Eric Anholt <eric@anholt.net> intel: Fix up z24_x8 depth spans since the texformat merge.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
409469fb70682cd819ab405e0f92a4659381cfbe 30-Oct-2009 Brian Paul <brianp@vmware.com> intel: fix up some XRGB breakage

We weren't choosing the right XRGB span functions for reading the
framebuffer. XRGB formats still aren't turned on yet though.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
4a253431abf43a0638afb43605b44a8742b72a60 30-Oct-2009 Brian Paul <brianp@vmware.com> intel: update intel_create_renderbuffer(format), add XRGB support

Pass a gl_format to intel_create_renderbuffer() instead of GLenum.
Add cases for MESA_FORMAT_XRGB8888 textures and renderbuffers.
However, we don't yet create any renderbuffers or textures with that
format. It seems the default alpha value is zero instead of one.
Need to investigate that first.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
1f196b786d6bd0c6a5dbdc638574ff716cc3d4de 29-Oct-2009 Brian Paul <brianp@vmware.com> Merge branch 'texformat-rework'

Conflicts:
src/mesa/drivers/dri/radeon/radeon_fbo.c
src/mesa/drivers/dri/s3v/s3v_tex.c
src/mesa/drivers/dri/s3v/s3v_xmesa.c
src/mesa/drivers/dri/trident/trident_context.c
src/mesa/main/debug.c
src/mesa/main/mipmap.c
src/mesa/main/texformat.c
src/mesa/main/texgetimage.c
7d56caabe45e91a67096804c7e341d04d01db7aa 28-Oct-2009 Brian Paul <brianp@vmware.com> Merge branch 'mesa_7_6_branch'

Conflicts:

src/mesa/shader/lex.yy.c
src/mesa/shader/program_lexer.l
b7eea8c616092f5473a323fba585b04c47ae2010 28-Oct-2009 Brian Paul <brianp@vmware.com> intel: added region draw_x/y offsets in x/y_tile_swizzle() funcs

This fixes the second part of bug 23552.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
68d94a608a6d46156a567b8f0e011ac58054975e 22-Oct-2009 Brian Paul <brianp@vmware.com> intel: use MESA_FORMAT_S8_Z24 format and avoid z24s8/s8z24 conversions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
45e76d2665b38ba3787548310efc59e969124c01 09-Oct-2009 Brian Paul <brianp@vmware.com> mesa: remove a bunch of gl_renderbuffer fields

_ActualFormat is replaced by Format (MESA_FORMAT_x).
ColorEncoding, ComponentType, RedBits, GreenBits, BlueBits, etc. are
all replaced by MESA_FORMAT_x queries.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
3e34a2a2b97e7c93955deedb7c12b73bccd6662d 06-Oct-2009 Brian Paul <brianp@vmware.com> drivers: don't include texformat.h

And remove other unneeded #includes while we're at it.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
7d4b7460b0e565d0574c00d1d40c426cfebc290d 29-Jul-2009 Eric Anholt <eric@anholt.net> i915: Enable ARB_vertex_shader for both i915 and i830.

Since the TNL is all done in software anyway, it should be the same to
the user who's probably using ARB_vertex_program otherwise, but gives them
a nicer programming environment.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
1f7c914ad0beea8a29c1a171c7cd1a12f2efe0fa 01-Oct-2009 Brian Paul <brianp@vmware.com> mesa: replace gl_texture_format with gl_format

Now gl_texture_image::TexFormat is a simple MESA_FORMAT_x enum.
ctx->Driver.ChooseTexture format also returns a MESA_FORMAT_x.
gl_texture_format will go away next.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
aa522e6cc434fbe37203152de2d5d513ab640c67 14-Sep-2009 Brian Paul <brianp@vmware.com> intel: minor code clean-ups
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
8ec456c68cc69349c2506ce64047d06c7113780c 14-Sep-2009 Brian Paul <brianp@vmware.com> intel: fix renderbuffer map/unmap regression

Commit 36dd53a3cded9d003ec418732b7fc93c1476aa9b caused a few regressions
because the glReadBuffer() buffer wasn't getting mapped when GL_READ_BUFFER
!= GL_DRAW_BUFFER.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
36dd53a3cded9d003ec418732b7fc93c1476aa9b 10-Sep-2009 Eric Anholt <eric@anholt.net> intel: Don't forget to map the depth read buffer in spans.

This broke BlitFramebufferEXT(GL_DEPTH_BUFFER_BIT).
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
4d24feddfff7787dd9271839951326a3710b268f 05-Aug-2009 Brian Paul <brianp@vmware.com> intel: fix typo: s/softare/software/
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
2c30fd84dfa052949a117c78d932b58c1f88b446 10-Apr-2009 Eric Anholt <eric@anholt.net> intel: Add support for argb1555, argb4444 FBOs and fix rgb565 fbo readpixels.

Also enable them all regardless of screen bpp, as 32 bpp what I've been
testing against, and haven't been able to detect any screen bpp-specific
troubles with them.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
2b34275a784501225f605f11db801b5f2d7cdc64 26-Feb-2009 Eric Anholt <eric@anholt.net> intel: Add span code for z24 without stencil.

It seems that in this case the Mesa code is handing us x8z24 values instead
of z24s8 values, so we need to not do the rotation. Fixes half of OGLconform
depthrange.c.

Bug #19447.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
43a45439465eff483486e7f86620e1d09978497f 26-Feb-2009 Eric Anholt <eric@anholt.net> intel: make template wrappers for the spans templates.

This is insanity, but so is copying the same blocks containing the actual
interesting code in the file three times each for the different tile formats.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
ba3aadf354e197ab56adddc99c3b3335d7e6863e 29-Jan-2009 Brian Paul <brianp@vmware.com> intel: fix check for Y orientation in span functions.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
65d39a9eed9ae60944dd3c5db392a382c5946cbc 27-Jan-2009 Eric Anholt <eric@anholt.net> intel: clean up more pf mess.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
03188b09e071ace9d9e21ccc56c01e90c0fa8639 14-Jan-2009 Ian Romanick <ian.d.romanick@intel.com> intel: SW fallback maps texture images, not texture coordinates
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
0cade4de4f74f6b0e86fb6622e2fc370c73fd840 20-Oct-2008 Eric Anholt <eric@anholt.net> intel: Don't keep intel->pClipRects, and instead just calculate it when needed.

This avoids issues with dereferencing stale cliprects around intel_draw_buffer
time. Additionally, take advantage of cliprects staying constant for FBOs and
DRI2, and emit cliprects in the batchbuffer instead of having to flush batch
each time they change.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
ecadb51bbcb972a79f3ed79e65a7986b9396e757 18-Sep-2008 Brian Paul <brian.paul@tungstengraphics.com> mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
35fd72756a05463568d94862f4fcd234903e1204 08-Sep-2008 Eric Anholt <eric@anholt.net> intel: track move of bo_exec from drivers to bufmgr.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
f75843a517bd188639e6866db2a7b04de3524e16 24-Aug-2008 Dave Airlie <airlied@linux.ie> Revert "Revert "Merge branch 'drm-gem'""

This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a 24-Aug-2008 Dave Airlie <airlied@linux.ie> Revert "Merge branch 'drm-gem'"

This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.

Conflicts:

src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
53675e5c05c0598b7ea206d5c27dbcae786a2c03 09-Aug-2008 Eric Anholt <eric@anholt.net> Merge branch 'drm-gem'

Conflicts:

src/mesa/drivers/dri/intel/intel_span.c
src/mesa/main/fbobject.c

This converts the i915 driver to use the GEM interfaces for object management.
8e8019b49ab137403ba92aef3e286f4e27049ad5 05-Aug-2008 Xiang, Haihao <haihao.xiang@intel.com> dri: Fix write/read depth buffer issue under 16bpp mode. See bug #16646
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
902e401a384a8213d1239aae42bc2b7071ad6bd8 27-Jul-2008 Eric Anholt <eric@anholt.net> intel: Don't return a renderbuffer with alpha when just GL_RGB is requested.

Fixes oglconform rbGetterFuncs testcase. The span code for this mode hasn't
actually been tested.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
2e3714380027252ba17a11f23eae851d3f77ab02 23-Jul-2008 Eric Anholt <eric@anholt.net> intel: Add a little span cache to spead up readpixels by cutting syscalls.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
d2d5abfaeb46fc7b4d4267a6c9e92420fc9b5334 23-Jul-2008 Eric Anholt <eric@anholt.net> intel-gem: Use pread/pwrite for span access.

This will avoid clflushing entire buffers for small acesses, such as those
commonly used by regression tests.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
bdaa06ad639821368ac8d1af7b7561fd7e83fb13 15-Jul-2008 Eric Anholt <eric@anholt.net> intel: move renderbuffer mapping to separate functions.

This lets us avoid duplicated code for doing so, including the depthstencil
paths that aren't covered by SpanRenderStart/Finish. Those paths were
missing the span funcs setup, leading to a null dereference in the fbotexture
demo.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
a5f02368d2a9ab1f814eba2c997729c6c655fc5e 15-Jul-2008 Eric Anholt <eric@anholt.net> intel-gem: Disable spantmp sse/mmx functions when tile swizzling.

Those functions rely on being able to treat the GET_PTR returned value as an
array indexed by x, but that's not the case for our tiling.

Bug #16387
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
2e841880cfc1006a2818d4a8bfefd21136dc39a9 11-Jul-2008 Eric Anholt <eric@anholt.net> drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
def6e4f420feed4a07402a8da84e7822f6ddba99 02-Jul-2008 Eric Anholt <eric@anholt.net> intel: span rendering requires just a flush before starting, not finish.

The dri_bo_map()s that follow will take care of idling the hardware as needed.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
4b3ed4d2d16811a624857519e95303017f4160b5 02-Jul-2008 Eric Anholt <eric@anholt.net> intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.

Apparently in Y mode we get bit 6 ^ bit 9. The reflect demo in 'd' mode now
displays correctly.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
19f585a3cf65887e249d630fe43e83e7e7618dfa 02-Jul-2008 Eric Anholt <eric@anholt.net> intel-gem: Fix Y-tiling span setup.

The boolean that the server gives us for whether the region is tiled was
getting used as the enum for what tiling mode. Instead, guess the correct
tiling in screen setup.

Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is
32 scanlines, not 8.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
e74f54793e45dd2e36474f6fc527456647f32efd 02-Jul-2008 Eric Anholt <eric@anholt.net> intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.

It turns out that it's not just deviceID dependent, and there's some additional
undefined factor that determines the bit 6 swizzling. It's now controllable
with swizzle_mode=[012] until we get a response on how to automatically detect.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
e2baf564d1b9716611d194cf117b329a92ad603d 17-Jun-2008 Eric Anholt <eric@anholt.net> [intel-gem] Bug #16326: Fix X tile unswizzling on 965.

Apparently a bit gets flipped in the addressing for some rows of each tile.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
537bbe6dec780f6f85838fe7e6036579c509f8a6 06-May-2008 Keith Packard <keithp@keithp.com> [intel-GEM] Add tiling support to swrast.

Accessing tiled surfaces without using the fence registers requires that
software deal with the address swizzling itself.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
c30392f187dc45412e579283989992ed4dd2fed8 10-Jan-2008 Xiang, Haihao <haihao.xiang@intel.com> i965: fix segfault caused by commit e131c46b20241737ceba4856dbe01dcca6dd2c03.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
ff73c783cc47361ff0dd819c82d067b4b85870dd 06-Jan-2008 Brian <brian.paul@tungstengraphics.com> Simplify ctx->_NumColorDrawBuffers, _ColorDrawBuffers and fix bug 13835.

These fields are no longer indexed by shader output. Now, we just have
a simple array of renderbuffer pointers.

If the shader writes to gl_FragData[i], send those colors to the N
_ColorDrawBuffers. Otherwise, replicate the single gl_FragColor (or
the fixed-function color) to the N _ColorDrawBuffers.

A few more changes and simplifications can follow from this...
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
7c71ef3a3d0cf2620525f468960cdc76a0fb0d33 12-Dec-2007 Eric Anholt <eric@anholt.net> [intel] Move bufmgr back to context instead of screen, fixing glthreads.

Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes. It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965). The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c
77a5bcaff43df8d54e0e0ef833726e4b41d7eb36 07-Nov-2007 Eric Anholt <eric@anholt.net> [intel] Move over files that will be shared with 965-fbo work.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.c