Cross Reference: /external/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp

Lines Matching refs:DestReg
93                                   unsigned DestReg, unsigned SrcReg,
97   if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
113       BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
119     if (Mips::CCRRegClass.contains(DestReg))
121     else if (Mips::FGR32RegClass.contains(DestReg))
123     else if (Mips::HIRegsRegClass.contains(DestReg))
124       Opc = Mips::MTHI, DestReg = 0;
125     else if (Mips::LORegsRegClass.contains(DestReg))
126       Opc = Mips::MTLO, DestReg = 0;
127     else if (Mips::HIRegsDSPRegClass.contains(DestReg))
129     else if (Mips::LORegsDSPRegClass.contains(DestReg))
131     else if (Mips::DSPCCRegClass.contains(DestReg)) {
134         .addReg(DestReg, RegState::ImplicitDefine);
138   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
140   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
142   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
144   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
155     if (Mips::HIRegs64RegClass.contains(DestReg))
156       Opc = Mips::MTHI64, DestReg = 0;
157     else if (Mips::LORegs64RegClass.contains(DestReg))
158       Opc = Mips::MTLO64, DestReg = 0;
159     else if (Mips::FGR64RegClass.contains(DestReg))
167   if (DestReg)
168     MIB.addReg(DestReg, RegState::Define);
214                  unsigned DestReg, int FI, const TargetRegisterClass *RC,
241   BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)