/external/chromium_org/third_party/icu/source/test/intltest/ |
H A D | tscoll.h | 26 struct Order struct in class:IntlTestCollator 51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
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/external/icu4c/test/intltest/ |
H A D | tscoll.h | 26 struct Order struct in class:IntlTestCollator 51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
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/external/aac/libAACdec/src/ |
H A D | aacdec_tns.h | 113 UCHAR Order; member in struct:__anon24
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/external/chromium_org/skia/ext/ |
H A D | recursive_gaussian_convolution.h | 21 enum Order { enum in class:skia::RecursiveFilter 29 SK_API RecursiveFilter(float sigma, Order order); 31 Order order() const { return order_; } 35 Order order_;
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/external/chromium_org/third_party/opus/src/silk/float/ |
H A D | corrMatrix_FLP.c | 43 const opus_int Order, /* I Max lag for correlation */ 50 ptr1 = &x[ Order - 1 ]; /* Points to first sample of column 0 of X: X[:,0] */ 51 for( lag = 0; lag < Order; lag++ ) { 62 const opus_int Order, /* I Max lag for correlation */ 70 ptr1 = &x[ Order - 1 ]; /* First sample of column 0 of X */ 72 matrix_ptr( XX, 0, 0, Order ) = ( silk_float )energy; 73 for( j = 1; j < Order; j++ ) { 76 matrix_ptr( XX, j, j, Order ) = ( silk_float )energy; 79 ptr2 = &x[ Order - 2 ]; /* First sample of column 1 of X */ 80 for( lag = 1; lag < Order; la 39 silk_corrVector_FLP( const silk_float *x, const silk_float *t, const opus_int L, const opus_int Order, silk_float *Xt ) argument 59 silk_corrMatrix_FLP( const silk_float *x, const opus_int L, const opus_int Order, silk_float *XX ) argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | AllocationOrder.h | 1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===// 30 ArrayRef<MCPhysReg> Order; member in class:llvm::AllocationOrder 43 ArrayRef<MCPhysReg> getOrder() const { return Order; } 51 while (Pos < int(Order.size())) { 52 unsigned Reg = Order[Pos++]; 67 return Order[Pos++];
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H A D | CriticalAntiDepBreaker.cpp | 366 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); local 367 for (unsigned i = 0; i != Order.size(); ++i) { 368 unsigned NewReg = Order[i];
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H A D | TargetRegisterInfo.cpp | 125 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); local 126 for (unsigned i = 0; i != Order.size(); ++i) 127 R.set(Order[i]); 257 ArrayRef<MCPhysReg> Order, 282 if (std::find(Order.begin(), Order.end(), Phys) == Order.end()) 256 getRegAllocationHints(unsigned VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM) const argument
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H A D | RegAllocGreedy.cpp | 457 AllocationOrder &Order, 459 Order.rewind(); 461 while ((PhysReg = Order.next())) 464 if (!PhysReg || Order.isHint()) 472 if (Order.isHint(Hint)) { 490 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); 500 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); 502 while ((PhysReg = Order.next())) { 679 /// @param Order Physregs to try. 682 AllocationOrder &Order, 456 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<LiveInterval*> &NewVRegs) argument 681 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<LiveInterval*> &NewVRegs, unsigned CostPerUseLimit) argument [all...] |
/external/chromium_org/third_party/libjingle/source/talk/base/ |
H A D | bytebuffer.h | 60 ByteOrder Order() const { return byte_order_; } function in class:talk_base::ByteBuffer
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/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 34 OwningArrayPtr<MCPhysReg> Order; member in struct:llvm::RegisterClassInfo::RCInfo 41 return makeArrayRef(Order.get(), NumRegs);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SDNodeDbgValue.h | 50 unsigned Order; member in class:llvm::SDDbgValue 55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O), 65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) { 72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) { 103 unsigned getOrder() { return Order; }
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H A D | SelectionDAGDumper.cpp | 489 if (unsigned Order = getIROrder()) 490 OS << " [ORD=" << Order << ']'; local
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/external/llvm/lib/Support/ |
H A D | Dwarf.cpp | 621 const char *llvm::dwarf::ArrayOrderString(unsigned Order) { argument 622 switch (Order) {
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/external/lzma/CPP/7zip/UI/Common/ |
H A D | ZipRegistry.h | 31 UInt32 Order;
member in struct:NCompression::CFormatOptions 42 BlockLogSize = NumThreads = Level = Dictionary = Order = UInt32(-1);
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/external/lzma/CS/7zip/ |
H A D | ICoder.cs | 95 Order,
enumerator in enum:SevenZip.CoderPropID
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/external/chromium_org/third_party/mesa/src/src/egl/main/ |
H A D | eglmode.c | 208 EGLint Order; /* SMALLER or LARGER */ member in struct:sort_info 242 else if (SortInfo[i].Order == SMALLER) { 245 else if (SortInfo[i].Order == LARGER) {
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/external/eigen/unsupported/Eigen/src/Splines/ |
H A D | Spline.h | 263 enum { Order = SplineTraits<Spline>::OrderAtCompileTime }; enumerator in enum:Eigen::__anon18358 270 const Block<const ControlPointVectorType,Dimension,Order> ctrl_pts(ctrls(),0,span-p,Dimension,p+1); 280 enum { Order = SplineTraits<SplineType>::OrderAtCompileTime }; enumerator in enum:Eigen::__anon18360 305 const Block<const ControlPointVectorType,Dimension,Order> ctrl_pts(spline.ctrls(),0,span-p,Dimension,p+1); 341 enum { Order = SplineTraits<SplineType>::OrderAtCompileTime }; enumerator in enum:Eigen::__anon18362 360 Matrix<Scalar,Order,Order> ndu(p+1,p+1);
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/external/mesa3d/src/egl/main/ |
H A D | eglmode.c | 208 EGLint Order; /* SMALLER or LARGER */ member in struct:sort_info 242 else if (SortInfo[i].Order == SMALLER) { 245 else if (SortInfo[i].Order == LARGER) {
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/external/chromium_org/third_party/WebKit/Source/devtools/front_end/ |
H A D | DataGrid.js | 142 /** @typedef {!{id: ?string, editable: boolean, longText: ?boolean, sort: !WebInspector.DataGrid.Order, sortable: boolean, align: !WebInspector.DataGrid.Align}} */ 153 WebInspector.DataGrid.Order = { 437 return WebInspector.DataGrid.Order.Ascending; 439 return WebInspector.DataGrid.Order.Descending; 927 var sortOrder = WebInspector.DataGrid.Order.Ascending; 929 sortOrder = WebInspector.DataGrid.Order.Descending; 942 * @param {!WebInspector.DataGrid.Order} sortOrder
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/external/chromium_org/third_party/leveldatabase/src/doc/bench/ |
H A D | db_bench_tree_db.cc | 282 enum Order { enum 424 void Write(bool sync, Order order, DBState state,
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H A D | db_bench_sqlite3.cc | 306 enum Order { enum 478 void Write(bool write_sync, Order order, DBState state, 581 void Read(Order order, int entries_per_batch) {
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 197 ArrayRef<MCPhysReg> Order, 213 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 229 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 233 for (unsigned I = 0, E = Order.size(); I != E; ++I) { 234 unsigned Reg = Order[I]; 196 getRegAllocationHints(unsigned VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM) const argument
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/external/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 259 PSets.push_back(RegBank.getRegPressureSet(*PSetI).Order); 854 ArrayRef<Record*> Order = RC.getOrder(); local 863 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 864 Record *Reg = Order[i]; 873 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 874 Record *Reg = Order[i]; 1033 ArrayRef<Record*> Order = RC.getOrder(); local 1036 AllocatableRegs.insert(Order.begin(), Order.end()); 1160 << " const ArrayRef<MCPhysReg> Order[] [all...] |
/external/clang/lib/CodeGen/ |
H A D | CGAtomic.cpp | 188 uint64_t Size, unsigned Align, llvm::AtomicOrdering Order) { 207 CGF.Builder.CreateAtomicCmpXchg(Ptr, LoadVal1, LoadVal2, Order); 220 Load->setAtomic(Order); 235 Store->setAtomic(Order); 298 CGF.Builder.CreateAtomicRMW(Op, Ptr, LoadVal1, Order); 351 llvm::Value *Ptr, *Order, *OrderFail = 0, *Val1 = 0, *Val2 = 0; local 361 Order = EmitScalarExpr(E->getOrder()); 497 Args.add(RValue::get(Order), 499 Order = OrderFail; 576 Args.add(RValue::get(Order), 186 EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *E, llvm::Value *Dest, llvm::Value *Ptr, llvm::Value *Val1, llvm::Value *Val2, uint64_t Size, unsigned Align, llvm::AtomicOrdering Order) argument [all...] |