Searched defs:SrcReg (Results 1 - 25 of 73) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DPHIEliminationUtils.cpp17 // findCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
19 // SrcReg, but before any subsequent point where control flow might jump out of
23 unsigned SrcReg) {
37 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(SrcReg),
22 findPHICopyInsertPoint(MachineBasicBlock* MBB, MachineBasicBlock* SuccMBB, unsigned SrcReg) argument
H A DOptimizePHIs.cpp99 unsigned SrcReg = MI->getOperand(i).getReg(); local
100 if (SrcReg == DstReg)
102 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
120 SingleValReg = SrcReg;
H A DRegisterCoalescer.h35 /// SrcReg - the virtual register that will be coalesced into dstReg.
36 unsigned SrcReg; member in class:llvm::CoalescerPair
42 /// SrcIdx - The sub-register index of the old SrcReg in the new coalesced
52 /// Flipped - True when DstReg and SrcReg are reversed from the original
58 /// SrcReg and DstReg.
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible
105 unsigned getSrcReg() const { return SrcReg; }
111 /// getSrcIdx - Return the subregister index that SrcReg wil
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H A DPeepholeOptimizer.cpp150 unsigned SrcReg, DstReg, SubIdx; local
151 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
155 TargetRegisterInfo::isPhysicalRegister(SrcReg))
158 if (MRI->hasOneNonDBGUse(SrcReg))
169 // The ext instr may be operating on a sub-register of SrcReg as well.
172 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
173 // SrcReg:SubIdx should be replaced.
175 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0;
193 UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end();
205 // Only accept uses of SrcReg
381 unsigned SrcReg, SrcReg2; local
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
49 .addReg(SrcReg, getKillRegState(KillSrc));
37 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
H A DAMDGPUInstrInfo.cpp37 unsigned &SrcReg, unsigned &DstReg,
124 unsigned SrcReg, bool isKill,
36 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument
122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg,
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
49 .addReg(SrcReg, getKillRegState(KillSrc));
37 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp43 unsigned DestReg, unsigned SrcReg,
46 .addReg(SrcReg, getKillRegState(KillSrc)));
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
53 unsigned SrcReg, bool isKill, int FI,
57 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
58 isARMLowRegister(SrcReg))) && "Unknown regclass!");
61 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
62 isARMLowRegister(SrcReg))) {
74 .addReg(SrcReg, getKillRegState(isKill))
41 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
52 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DThumb2InstrInfo.cpp115 unsigned DestReg, unsigned SrcReg,
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
119 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
122 .addReg(SrcReg, getKillRegState(KillSrc)));
127 unsigned SrcReg, bool isKill, int FI,
145 .addReg(SrcReg, getKillRegState(isKill))
155 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
159 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
165 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKil
113 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
126 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A DThumb2ITBlockPass.cpp118 unsigned SrcReg = MI->getOperand(1).getReg(); local
121 if (Uses.count(DstReg) || Defs.count(SrcReg))
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp87 // STriw_pred [R30], ofst, SrcReg;
93 int SrcReg = MI->getOperand(2).getReg(); local
94 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
105 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
114 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
123 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
H A DHexagonPeephole.cpp142 unsigned SrcReg = Src.getReg(); local
145 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
149 PeepholeMap[DstReg] = SrcReg;
164 unsigned SrcReg = Src2.getReg(); local
165 PeepholeMap[DstReg] = SrcReg;
181 unsigned SrcReg = Src1.getReg(); local
183 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/);
193 unsigned SrcReg = Src.getReg(); local
196 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
200 PeepholeMap[DstReg] = SrcReg;
216 unsigned SrcReg = Src.getReg(); local
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/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.h87 unsigned SrcReg, bool isKill, int FrameIndex,
90 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
103 unsigned SrcReg, bool isKill, int FrameIndex,
85 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/chromium_org/third_party/mesa/src/src/mesa/main/
H A Datifragshader.h55 struct atifragshader_src_register SrcReg[2][3]; member in struct:atifs_instruction
/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp36 unsigned SrcReg, bool isKill, int FrameIdx,
53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
90 unsigned DestReg, unsigned SrcReg,
93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
101 .addReg(SrcReg, getKillRegState(KillSrc));
34 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
88 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp34 unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
37 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
44 .addReg(SrcReg, getKillRegState(KillSrc));
47 .addReg(SrcReg, getKillRegState(KillSrc));
50 .addReg(SrcReg, getKillRegState(KillSrc));
53 .addReg(SrcReg, getKillRegState(KillSrc));
56 .addReg(SrcReg, getKillRegState(KillSrc));
59 .addReg(SrcReg, getKillRegState(KillSrc));
65 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, argument
80 SrcReg
32 copyPhysReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
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/external/llvm/lib/Target/R600/
H A DR600InstrInfo.cpp52 unsigned DestReg, unsigned SrcReg,
56 AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
59 AMDGPU::R600_Reg64RegClass.contains(SrcReg)) {
68 RI.getSubReg(SrcReg, SubRegIndex))
74 DestReg, SrcReg);
50 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
H A DSIInstrInfo.cpp37 unsigned DestReg, unsigned SrcReg,
43 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
84 if (!I->readsRegister(SrcReg))
93 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
95 .addReg(SrcReg, getKillRegState(KillSrc));
99 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
101 .addReg(SrcReg, getKillRegState(KillSrc));
105 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
110 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
115 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
35 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
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H A DAMDGPUInstrInfo.cpp38 unsigned &SrcReg, unsigned &DstReg,
105 unsigned SrcReg, bool isKill,
37 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument
103 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/mesa3d/src/mesa/main/
H A Datifragshader.h55 struct atifragshader_src_register SrcReg[2][3]; member in struct:atifs_instruction
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
H A Dradeon_program.h66 struct rc_src_register SrcReg[2]; member in struct:rc_presub_instruction
78 struct rc_src_register SrcReg[3]; member in struct:rc_sub_instruction
/external/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp309 unsigned SrcReg = ValueMap[V]; local
310 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
314 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
346 unsigned SrcReg = ValueMap[V]; local
347 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
351 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
H A DInstrEmitter.cpp85 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
87 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
92 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
120 } else if (DestReg != SrcReg)
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
172 VRBase = SrcReg;
177 VRBase).addReg(SrcReg);
481 unsigned SrcReg, DstReg, DefSubIdx;
483 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
485 TRC == MRI->getRegClass(SrcReg)) {
84 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) argument
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/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp274 unsigned DestReg, unsigned SrcReg,
276 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
278 .addReg(SrcReg, getKillRegState(KillSrc));
279 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
281 .addReg(SrcReg, getKillRegState(KillSrc));
282 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
285 .addReg(SrcReg, getKillRegState(KillSrc));
293 unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
301 MovMI->addRegisterKilled(SrcReg, TRI);
309 unsigned SrcReg, boo
272 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
308 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp62 unsigned SrcReg, int Offset, DebugLoc dl,
71 .addReg(SrcReg)
60 storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, int Offset, DebugLoc dl, const TargetInstrInfo &TII) argument

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